Octal buffer/driver with parity; non-inverting; 3-state

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Rev. 6 14 December 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal buffer and line driver with parity generation/checking. The can be used as memory address driver, clock driver and bus-oriented transmitter/receiver. The inclusion of parity generation/checking improves PCB density. Combines 74F244 and 74F280A functions in one device High impedance NPN base inputs for reduced input current (40 A in HIGH and LOW states) I IL =20 A compared to 600 A in FAST family specification For applications with high output drive and light bus loading Non-inverting 3-state output sink capability I OL = 64 ma and source I OH = 15 ma Inputs and outputs on separate sides simplifies board layout Combined functions reduce part count and enhance system performance Industrial temperature range available ( 40 C to+85 C) Table 1. Ordering information Type number Package Temperature range Name Description Version ND 0 C to70 C SO24 plastic small outline package; 24 leads; SOT137-1 ID 40 C to+85 C body width 7.5 mm

4. Functional diagram 2K 3 P3 3, 5, 6, 7, 8, 9, 10, 11, 12 [EVEN] 21 4 5 6 7 8 9 10 11 3, 5, 6, 7, 8, 9, 10, 11, 12 [ODD] 22 3 1 2 23 D0 D1 D2 D3 D4 D5 D6 D7 PI OE0 ΣE OE1 OE2 ΣO Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 21 22 20 19 18 17 16 15 14 13 001aal255 1 2 1 EN4 23 4 Z5 4 20 5 Z6 19 6 Z7 18 7 Z8 17 8 Z9 16 9 Z10 15 10 Z11 14 11 Z12 13 001aal256 Fig 1. Logic symbol Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 2 of 14

3 PI 21 ΣE 22 ΣO 4 D0 20 Q0 5 D1 19 Q1 6 D2 18 Q2 7 D3 17 Q3 8 D4 16 Q4 9 D5 15 Q5 10 D6 14 Q6 11 D7 1 OE0 2 OE1 23 OE2 13 Q7 001aal253 Fig 3. Logic diagram All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 3 of 14

5. Pinning information 5.1 Pinning OE0 1 24 V CC OE1 2 23 OE2 PI 3 22 ΣO D0 4 21 ΣE D1 5 20 Q0 D2 6 19 Q1 D3 7 18 Q2 D4 8 17 Q3 D5 9 16 Q4 D6 10 15 Q5 D7 11 14 Q6 GND 12 13 Q7 001aal254 Fig 4. Pin configuration Table 2. 5.2 Pin description Pin description Symbol Pin Description Unit load HIGH/LOW [1] One FAST Unit Load (UL) is defined as 20 A in HIGH state, 0.6 A in LOW state. Load value [1] HIGH/LOW OE0 1 output enable input (active LOW) 1.0/0.033 20 A/20 A OE1 2 output enable input (active LOW) 1.0/0.033 20 A/20 A PI 3 parity input 1.0/0.033 20 A/20 A D0 to D7 4, 5, 6, 7, 8, 9, 10, 11 data input 2.0/0.066 40 A/40 A GND 12 ground (0 V) Q0 to Q7 20, 19, 18, 17, 16, 15, 14, 13 data output 750/106.7 15 ma/64 ma E 21 even parity output 750/106.7 15 ma/64 ma O 22 odd parity output 750/106.7 15 ma/64 ma OE2 23 output enable input (active LOW) 1.0/0.033 20 A/20 A V CC 24 supply voltage All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 4 of 14

6. Functional description 6.1 Function table Table 3. Function selection [1] Input Output Status OE0 OE1 OE2 Dn Qn L L L L L transparent L L L H H H X X X Z disabled X H X X Z X X H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. Table 4. Function parity outputs [1] Inputs State Parity output E O Even number of inputs H H L (0, 2, 4, 6, 8) Odd number of inputs H L H (1, 3, 5, 7, 9) Any OEn H Z Z [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 5 of 14

7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7.0 V V I input voltage [1] 0.5 +7.0 V V O output voltage output in HIGH-state [1] 0.5 V CC V I IK input clamping current V I < 0 V 30 +5 ma I O output current output in LOW-state - 128 ma T amb ambient temperature in free-air [2] commercial 0 70 C industrial 40 +85 C T stg storage temperature 65 +150 C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 8. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage 4.5 5.0 5.5 V V IH HIGH-level input voltage 2.0 - - V V IL LOW-level input voltage - - 0.8 V I IK input clamping current - - 18 ma I OH HIGH-level output current 15 - - ma I OL LOW-level output current - - 64 ma 9. Static characteristics Table 7. Static characteristics Symbol Parameter Conditions 25 C 40 C to+85 C Unit Min Typ [1] Max Min Max V IK input clamping voltage V CC = 4.5 V; I IK = 18 ma 1.2 0.73-1.2 - V V OH HIGH-level output voltage V CC = 4.5 V; V IL = 0.8 V; V IH = 2.0 V I OH = 3 ma V CC = 10 % - - - 2.4 - V V CC = 5 % - 3.3-2.7 - V I OH = 15 ma V CC = 10 % - - - 2.0 - V All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 6 of 14

Table 7. Static characteristics continued Symbol Parameter Conditions 25 C 40 C to+85 C Unit Min Typ [1] Max Min Max V OL LOW-level output voltage V CC = 4.5 V; V IL = 0.8 V; V IH = 2.0 V I OL =64mA V CC = 10 % - - - - 0.55 V V CC = 5 % - 0.42 - - 0.55 V I I input leakage current V CC =0V; V I =7.0V - - - - 100 A I IH HIGH-level input current V CC = 5.5 V; V I = 2.7 V; commercial pin Dn - - - - 40 A pin PI, OEn - - - - 20 A V CC = 5.5 V; V I = 2.7 V; industrial pin Dn - - - - 80 A pin PI, OEn - - - - 40 A I IL LOW-level input current V CC = 5.5 V; V I =0.5V pin Dn - - - - 40 A pin PI, OEn - - - - 20 A I OZ OFF-state output current V CC = 5.5 V V O = 2.7 V - - - - 50 A V O = 0.5 V - - - - 50 A I O output current V CC = 5.5 V [2] - - - 100 225 ma I CC supply current V CC = 5.5 V; V I = GND or V CC outputs HIGH-state - 50 - - 80 ma outputs LOW-state - 78 - - 110 ma outputs OFF-state - 83 - - 90 ma [1] All typical values are measured at V CC =5V. [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit, see Figure 7. Symbol Parameter Conditions 25 C; V CC =5.0V 0 C to 70 C; V CC =5.0 V 0.5 V 40 C to +85 C; V CC =5.0 V 0.5 V Unit Min Typ Max Min Max Min Max t PLH LOW to HIGH Dn to Qn; 2.0 4.0 6.5 2.0 7.0 2.0 8.0 ns propagation delay see Figure 5 Dn to E, O; see Figure 5 5.5 10.0 13.0 5.5 14.0 4.5 16.5 ns t PHL t PZH HIGH to LOW propagation delay OFF-state to HIGH propagation delay Dn to Qn; see Figure 5 Dn to E, O; see Figure 5 OEn to Qn; see Figure 6 2.5 5.5 7.0 2.5 7.5 2.5 9.0 ns 5.5 11.0 14.5 5.5 16.5 5.5 18.0 ns 3.5 7.0 10.5 3.5 11.5 3.0 13.0 ns All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 7 of 14

Table 8. Dynamic characteristics continued GND = 0 V; for test circuit, see Figure 7. Symbol Parameter Conditions 25 C; 0 C to 70 C; 40 C to +85 C; Unit V CC =5.0V V CC =5.0 V 0.5 V V CC =5.0 V 0.5 V Min Typ Max Min Max Min Max 4.0 8.0 11.0 4.5 12.0 4.0 13.5 ns t PZL t PHZ t PLZ OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay 11. Waveforms OEn to Qn; see Figure 6 OEn to Qn; see Figure 6 OEn to Qn; see Figure 6 1.5 4.5 8.0 1.5 9.0 1.5 10.0 ns 2.0 5.0 8.0 2.0 9.0 1.5 10.0 ns V I Dn GND t PLH t PHL V OH ΣE, ΣO, Qn V OL 001aal257 Fig 5. =1.5V Propagation delay input Dn to output Qn, E, O V I OEn input GND t PLZ t PZL output LOW-to-OFF OFF-to-LOW 3.5 V V OL V OL + 0.3 V t PHZ t PZH output HIGH-to-OFF OFF-to-HIGH V OH GND outputs enabled V OH 0.3 V outputs disabled outputs enabled 001aal293 Fig 6. =1.5V V OL and V OH are typical voltage output levels that occur with the output load. 3-state output enable and disable times All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 8 of 14

V I negative pulse 0 V t W 90 % 90 % 10 % t f t r t r t f G V I V CC DUT V O V EXT RL V I positive pulse 0 V 90 % 10 % 10 % t W 001aac221 RT CL RL mna616 a. Input pulse definition b. Test circuit Fig 7. Test data and V EXT levels are given in Table 9. R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. V EXT = Test voltage for switching times. Test circuit for measuring switching times Table 9. Test data Input Load V EXT V I f I t W t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 3.0V 1MHz 500ns 2.5 ns 50 pf 500 open open 7.0 V All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 9 of 14

12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y H E v M A Z 24 13 Q A 2 A 1 (A ) 3 A pin 1 index L p L θ 1 e b p 12 w M detail X 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A 1 A 2 A 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z 0.3 0.1 0.012 0.004 2.45 2.25 0.096 0.089 0.25 0.01 0.49 0.36 0.019 0.014 0.32 0.23 0.013 0.009 15.6 15.2 0.61 0.60 7.6 7.4 0.30 0.29 1.27 10.65 10.00 0.419 0.394 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 0.05 1.4 0.055 1.1 0.4 0.043 0.016 1.1 1.0 0.043 0.039 0.25 0.25 0.1 0.01 0.01 0.004 θ 0.9 0.4 o 8 o 0.035 0 0.016 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT137-1 075E05 MS-013 99-12-27 03-02-19 Fig 8. Package outline SOT137-1 (SO24) All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 10 of 14

13. Abbreviations Table 10. Acronym DUT ESD HBM MM PCB Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model Printed-Circuit Board 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes v.6 20111214 Product data sheet - v.5 Modifications: Legal pages updated. v.5 20100325 Product data sheet - v.4 v.4 20100205 Product data sheet - v.3 v.3 20000630 Product specification - v.2 v.2 19910717 Product specification - - All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 11 of 14

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17. Contents 1 General description...................... 1 2 Features and benefits.................... 1 3 Ordering information..................... 1 4 Functional diagram...................... 2 5 Pinning information...................... 4 5.1 Pinning............................... 4 5.2 Pin description......................... 4 6 Functional description................... 5 6.1 Function table.......................... 5 7 Limiting values.......................... 6 8 Recommended operating conditions........ 6 9 Static characteristics..................... 6 10 Dynamic characteristics.................. 7 11 Waveforms............................. 8 12 Package outline........................ 10 13 Abbreviations.......................... 11 14 Revision history........................ 11 15 Legal information....................... 12 15.1 Data sheet status...................... 12 15.2 Definitions............................ 12 15.3 Disclaimers........................... 12 15.4 Trademarks........................... 13 16 Contact information..................... 13 17 Contents.............................. 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 December 2011 Document identifier: