8 CHAPTER 6 IMPLEMENTATION OF FPGA BASED CASCADED MULTILEVEL INVERTER 6.1 INTRODUCTION In this part of research, a proto type model of FPGA based nine level cascaded inverter has been fabricated to improve the power quality. Significant improvement in power quality is achieved by minimizing the harmonic content in the output voltage using selective harmonic elimination technique. A model of single phase nine level cascaded inverter with identical dc supply is designed to reduce the harmonic components of the output voltage. Particle Swam Optimization technique is applied to determine the optimum switching angles thereby reducing some higher order harmonics while maintaining the required fundamental voltage. This generalized technique can be extended to multi level inverters with any number of levels. The total harmonic distortion is measured accordingly for different modulation indices. The results of the hardware are presented and analyzed. The results are verified with the simulation results. 6. BLOCK DIAGRAM OF HARDWARE MODEL Figure 6.1 shows the block diagram representation of the proposed hardware model. V 1,V,V 3 and V 4 are the individual source voltage and are of equal value. Vo is the output voltage. FPGA controller is used to generate the required switching signals. Driver circuit is used to give necessary isolation and to amplify the signals for complete turn on of MOSFET switches. The proto type model of a single phase nine level cascaded inverter has been fabricated for an output voltage of 48V (peak to peak). The N-channel power
9 MOSFET (IRF840, 8A, 500V, 0.850Ω) (APPENDIX-1) switches are used in the power circuit. The required gating signals are generated from FPGA controller. Figure 6.1 Block diagram of FPGA based multilevel inverter The switching angles calculated from PSO technique corresponding to minimum THD in the output voltage for varying modulation index (MI) are stored as look-up table in the memory of the FPGA controller for online applications. 6..1 Field Programmable Gate Array (FPGA) FPGA consists of an array of logic blocks, surrounded by programmable I/O blocks, and connected with programmable interconnect shown in figure 6.. A typical FPGA from 64 to tens of thousands of logic blocks and an even greater number of flip-flops. Each logic cell can independently take on any one of a limited set of personalities. The individual cells are interconnected by a matrix of wires and programmable switches. An user's design is implemented by specifying the
80 simple logic function for each cell and selectively closing the switches in the interconnect matrix. The arrays of logic cells and interconnect form a fabric of basic building blocks for logic circuits. Complex designs are created by combining these basic blocks to create the desired circuit. Figure 6. Internal structure of FPGA Figure 6.3 shows the hardware arrangements of FPGA controller. It consists of FPGA controller as CPU, LCD display, the various ports to connect the appropriate devices. Figure 6.3 Hardware arrangement of FPGA controller circuit
81 6.. Key components and features Figure 6.4 shows the Spartan-3E block diagram, which includes the following components and features: Figure 6.4 Block Diagram of FPGA SPARTAN 3e o o o o o Processor CPU SPARTAN 3e Operating frequency-0mhz Switching frequency-6.3khz 100,000-gate Xilinx Spartan-3E XC3S100E FPGA in a 144-Thin Quad Flat Pack Package (XC3S100E-TQ144) Two Digital Clock Managers (DCMs) 3 Mbit Intel Strata Flash On Board programmable oscillator (3 to00mhz)
8 o RS3 UART o 4 Channel 8 Bit I C based ADC & single Channel DAC o On Board configuration Flash PROM XCF01S SPARTAN3E FPGAs usually include on chip PWM controllers making implementation easy. The PWM generator in FPGA produces 16 PWM signals to the bridge circuit and the table 6.1 shows the details of PWM signals applied to the IC. Hence, in the present work, the real time implementation of controllers for chosen the inverter using FPGA is carried. Multicarrier PWM generation and also the control strategies for the chosen inverter are developed using system generator software of Xilinx. Table 6.1 Pin details of PWM output PWM SIGNALS PWM1 PWM PWM3 PWM4 PWM5 PWM6 PWM PWM8 FPGA Pins P93 P94 P96 P9 P98 P103 P104 P105 6.3 SWITCHING SIGNALS GENERATION The figure 6.5 shows the flow chart for generating the switching signals for the nine level inverter using FPGA controller. The algorithm used to generate the signals is illustrated in the flow chart.
83
84 Figure 6.5 Flow chart for switching signal generation The output of multiple output power supply shown in figure 6.6 are +5V, +1V and 1V. Input AC signal is applied to the primary of transformer and the transformer secondary has two outputs; one is 0-9V AC and another is 18-0-18V. Transformer secondary output is connected to the regulator through full bridge rectifier and filtering capacitor. Diode is used for converting the AC voltage to DC
85 voltage with AC ripples; capacitor is used to remove the AC ripples. Regulator IC is for regulating the DC output voltage. This power supply outputs are used to energize the driver circuit, FPGA controller and also the input to the inverter. 6.3.1 Multiple output power supply Figure 6.6 Multiple output power supply Transformer Primary Voltage = 30V AC Secondary Voltage = 0-9V AC and 18-0-18V AC Regulator IC - 805 and 81 = Positive Voltage Regulator (+5V and 1V) IC - 91 = Negative Voltage Regulator (-1V) Diode = 1N400 Capacitor = 400µf/16V, 400µf/5V and 10µf/63V 6.4 HARDWARE MODEL The gate signal generator model developed using system generator is compiled and converted into bits and is downloaded into FPGA for execution in real time. The generated switching pulses are fed to pulse amplifiers through the input/output lines of FPGA before being applied to the gates of MOSFETs of the proto type of the chosen inverter. Proper driver circuit is fabricated to amplify (Gate driver voltage +15V) the signals generated in the FPGA. Necessary isolations using MCTE (APPENDIX-) are also provided which is shown in figure 6..
86 10uF / 63V +15V 4.0 k PWM Input 1 3 4.k PWM Input 3 5 4506 0 1.01u 8 6 8 6 0K 0k +15V 0K 14 0k1 3 4 UA 1 4584 14 UB 10uf/63V +15V 9 3 VDD 0.1uF VCC 1 13 10 11 COM VSS HIN SHDN 1 LIN IR110 U1 HO VB 6 10uf/63V4 VS 5 1 LO 1 0.1uF 18V FR10 10 k 0k FR10 10k 0k 18V 18V G1 S1 G S 4584 5 +15V FR10 4.0 k PWM Input 3 3 4.k PWM Input 4 3 5 4506 8 6 8 6 0K 0k +15V 0K 14 0k1 3 4 UA 1 4584 14 UB 10uf/63V +15V 9 3 VDD 0.1uF VCC 1 13 10 11 COM VSS HIN SHDN 1 LIN IR110 G3 S3 G4 S4 5 U1 HO VB 6 10uf/63V4 VS 5 1 LO 1 0.1uF 18V 10 k 0k FR10 10k 0k 18V 18V 4584 Figure 6. Driver circuit The figure 6.8 shows the hardware model of the cascaded nine level inverter. This model is fabricated and tested in the laboratory.
8 Figure 6.8 Hardware model of proposed multilevel inverter Figure 6.9 shows the gating pulses to the switches of the cascaded bridges. The pulses are produced by SPWM technique. The magnitude of the pulse is 15V, which is obtained across gate and source of each MOSFET of the bridge. The gating pulses are used to drive the switches to conduct as per the conduction periods to produce the required outputs.
Figure 6.9 Switching Signals from FPGA Controller 88
89 Figure 6.10 Output voltage waveform The hardware results obtained are found to be close to the simulation results. Figure 6.10 shows the output voltage waveform of the nine level cascaded inverter. The input voltage to each bridge is 1V which is obtained from multiple output power supply. The output voltage of the inverter is 48V which has nine levels including zero is shown figure 6.10. The corresponding harmonic profile is shown in figure 6.11. Figure 6.11 FFT analysis of output voltage
90 The comparison of hardware results with the simulation results is shown in figure 6.1. From the figure 6.1, it is concluded that for the modulation indices 0.8 to 0.85, the output voltage of hardware model has more THD whereas, for the modulation indices, ranging from 0.86 to 0.91 both hardware and simulation results are very close and almost they agree each other. Figure 6.1 Comparision of simulation and hardware results 6.5 CONCLUSION The performance of multilevel inverter with SPWM switching schemes are studied through simulation using MATLAB/Simulink. The PSO technique has been used to obtain the optimum switching angles to have minimum THD in the output of the multilevel inverter. The simulation has been carried out and the results are presented and analyzed in the chapter 4. The prototype model of FPGA based cascaded nine level inverter is implemented to validate the simulation results. The comparison of hardware results with the simulation results discloses that hardware results closely agree with that of simulation. Hence, it is concluded that the cascaded multilevel inverter with improved harmonic spectrum is prominent converter for all industrial applications.