DATA SHEET Part No. Package Code No. AN781NSP SP-SUA Publication date: October 008 1
Contents Overview. Features.. Applications Package. Type.... Block Diagram.... 4 Pin Descriptions. 5 Absolute Maximum Ratings. 6 Electrical Characteristics. 7 Electrical Characteristics (Reference values for design). 8 Technical Data.. 9
AN781NSP -pin positive output voltage regulator (1 A type) Overview The AN78xxNSP series is a -pin fixed positive output type monolithic voltage regulator housed in surface mounting package. Stabilized fixed output voltage is obtained from unstable DC input voltage with using minimum external components. 9 types of fixed output voltage are available; 5 V, 6 V, 7 V, 8 V, 9 V, 10 V, 1 V, 15 V and 18 V. They can be used widely in power circuits with current capacity up to 1 A. The AN781NSP is the 1 V output voltage type in these series. Features Built-in overcurrent limit circuit Built-in thermal overload protection circuit Built-in ASO (area of safe operation) protection circuit Applications -pin positive output voltage regulator (1 A type) Package -pin Plastic Surface Mount Power Package (SP type) Type Silicon monolithic bipolar IC
Block Diagram Input Starter Voltage Reference C IN 0. μf C OUT 0.1 μf Pass Tr Current Source Error Amp. Thermal Protection Current Limiter 1 C IN + FIN C OUT R R 1 R SC Output 4
Pin Descriptions Pin No. Pin name Type Description 1 Input Input Input voltage GND Ground Ground (FIN) Output Output Output voltage 5
Absolute Maximum Ratings No. Parameter Symbol Rating Unit Note 1 4 5 Note) Supply voltage Supply current Power dissipation Operating ambient temperature Storage temperature V CC I CC P D T opr T stg 5 0 to +85 55 to +150 : The power dissipation shown is the value at T a = 85 C. When using this IC, refer to the P D -T a diagram in the Technical Data and use under the condition not exceeding the allowable value. When T j exceeds 150 C, the internal circuit cuts off the output. *: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for T a = 5 C. 64.9 V mw C C * * 6
Electrical Characteristics Note) Unless otherwise specified, T a = 5 C± C, V IN = 19 V, I OUT = 500, C IN = 0. μf and C OUT = 0.1 μf No. 1 4 5 6 7 8 Output voltage Line regulation Load regulation Bias current Parameter V IN = 15 V to 7 V, Output voltage tolerance V OUT I OUT = 5 to 1 000, 11.4 Bias current fluctuation to input Bias current fluctuation to load Ripple rejection ratio Symbol V OUT1 REG IN1 REG IN REG L1 REG L I Bias ΔI Bias(IN) ΔI Bias(L) RR V IN = 16 V to V, I OUT = 5 to 1 500, I OUT = 50 to 750, Conditions V IN = 14.5 V to 0 V, V IN = 14.5 V to 0 V, I OUT = 5 to 1 000, V IN = 15 V to 5 V, I OUT = 100, f = 10 Hz Note) : The specified condition T j = 5 C means that the test should be carried out within so short a test time (within 10ms) that the characteristic value drift due to the chip junction temperature rise can be ignored. Min 11.5 55 Limits Typ 1.0 10 1 4.0 4.0 Max 1.5 1.6 40 10 40 10 8 1.0 0.5 Unit V V mv mv db Note 7
Electrical Characteristics (Reference values for design) Note) Unless otherwise specified, T a = 5 C± C, V IN = 19 V, I OUT = 500, C IN = 0. μf and C OUT = 0.1 μf The characteristics listed below are reference values for design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to user concerns. No. 1 4 5 6 Parameter Output noise voltage Minimum input/output voltage difference Output short-circuit current Peak output current Output voltage temperature coefficient Thermal protection operating Temperature Symbol Vno V DIF(min) I O(Short) I O(Peak) ΔV OUT Ta T j(th) I OUT = 5, T j = 0 C to 15 C I OUT = 5 Conditions f = 10 Hz to 100 khz I OUT = 1 000, V IN = 5 V, Reference values 75 700 000 0.8 150 μv V mv/ C Note) : The specified condition T j = 5 C means that the test should be carried out within so short a test time (within 10ms) that the characteristic value drift due to the chip junction temperature rise can be ignored. Min Typ Max Unit C Note 8
Technical Data P D T a diagram 9
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