PHP69N3LT, PHB69N3LT FETURES SYMBOL QUICK REFERENCE T Trench technology d V SS = 5 V Very low on-state resistance Fast switching I = 69 Low thermal resistance Logic level compatible g R S(ON) mω (V GS = V) R S(ON) 4 mω (V GS = 5 V) GENERL ESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using trench technology. pplications:- High frequency computer motherboard d.c. to d.c. converters High current switching The PHP69N3LT is supplied in the SOT78 (TOB) conventional leaded package. The PHB69N3LT is supplied in the SOT44 ( PK) surface mounting package. The is supplied in the SOT48 (PK)surface mounting package. PINNING SOT78 (TOB) SOT44 ( PK) SOT48 (PK) s PIN ESCRIPTION tab tab tab gate drain 3 source tab drain 3 3 3 LIMITING VLUES Limiting values in accordance with the bsolute Maximum System (IEC 34) SYMBOL PRMETER CONITIONS MIN. MX. UNIT V SS rain-source voltage T j = 5 C to 75 C - 5 V V GR rain-gate voltage T j = 5 C to 75 C; R GS = kω - 5 V V GS Gate-source voltage (C) - ± 5 V V GSM Gate-source voltage (pulse T j 5 C - ± V peak value) I rain current (C) T mb = 5 C - 69 T mb = C - 48 I M rain current (pulse peak T mb = 5 C - 4 value) P tot Total power dissipation T mb = 5 C - 5 W T j, T stg Operating junction and - 55 75 C storage temperature It is not possible to make connection to pin: of the SOT44 or SOT48 packages. October 999 Rev.6
PHP69N3LT, PHB69N3LTT THERML RESISTNCES SYMBOL PRMETER CONITIONS MIN. TYP. MX. UNIT R th j-mb Thermal resistance junction - -. K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air - 6 - K/W to ambient SOT44 and SOT48 packages, pcb - 5 - K/W mounted, minimum footprint VLNCHE LIMITING VLUE SYMBOL PRMETER CONITIONS MIN. MX. UNIT W SS rain-source non-repetitive I = 5 ; V 5 V; - 6 mj unclamped inductive turn-off V GS = 5 V; R GS = 5 Ω; T mb = 5 C energy ELECTRICL CHRCTERISTICS T j = 5 C unless otherwise specified SYMBOL PRMETER CONITIONS MIN. TYP. MX. UNIT V (BR)SS rain-source breakdown V GS = V; I =.5 m; 5 - - V voltage T j = -55 C - - V V GS(TO) Gate threshold voltage V S = V GS ; I = m.5 V T j = 75 C.5 - - V T j = -55 C - -.3 V R S(ON) rain-source on-state V GS = V; I = 5-8.5 mω resistance V GS = 5 V; I = 5-4 mω V GS = 5 V; I = 5 ; T j = 75 C - - 6 mω g fs Forward transconductance V S = 5 V; I = 5 4 - S I GSS Gate source leakage current V GS = ±5 V; V S = V - n I SS Zero gate voltage drain V S = 5 V; V GS = V; -.5 µ current T j = 75 C - - 5 µ Q g(tot) Total gate charge I = 69 ; V = 5 V; V GS = 5 V - 6 - nc Q gs Gate-source charge - 7.6 - nc Q gd Gate-drain (Miller) charge - - nc t d on Turn-on delay time V = 5 V; I = 5 ; - 7 5 ns t r Turn-on rise time V GS = V; R G = 5 Ω - 5 75 ns t d off Turn-off delay time Resistive load - 8 ns t f Turn-off fall time - 59 75 ns L d Internal drain inductance Measured tab to centre of die - 3.5 - nh L d Internal drain inductance Measured from drain lead to centre of die - 4.5 - nh (SOT78 package only) L s Internal source inductance Measured from source lead to source - 7.5 - nh bond pad C iss Input capacitance V GS = V; V S = V; f = MHz - 7 - pf C oss Output capacitance - 475 - pf C rss Feedback capacitance - 3 - pf October 999 Rev.6
PHP69N3LT, PHB69N3LTT REVERSE IOE LIMITING VLUES N CHRCTERISTICS T j = 5 C unless otherwise specified SYMBOL PRMETER CONITIONS MIN. TYP. MX. UNIT I S Continuous source current - - 69 (body diode) I SM Pulsed source current (body - - 4 diode) V S iode forward voltage I F = 5 ; V GS = V -.9. V I F = 69 ; V GS = V -. - t rr Reverse recovery time I F = ; -di F /dt = /µs; - 83 - ns Q rr Reverse recovery charge V GS = V; V R = 5 V -. - µc 9 8 7 6 5 4 3 Normalised Power erating, P (%) 5 5 75 5 5 75 Mounting Base temperature, Tmb (C) Fig.. Normalised power dissipation. P% = P /P 5 C = f(t mb ) Peak Pulsed rain Current, IM () RS(on) = VS/ I.C. tp = us us ms ms ms rain-source Voltage, VS (V) Fig.3. Safe operating area I & I M = f(v S ); I M single pulse; parameter t p 9 8 7 6 5 4 3 Normalised Current erating, I (%) 5 5 75 5 5 75 Mounting Base temperature, Tmb (C) Fig.. Normalised continuous drain current. I% = I /I 5 C = f(t mb ); V GS 5 V Transient thermal impedance, Zth j-mb (K/W). =.5...5. single pulse T. E-6 E-5 E-4 E-3 E- E- E+ Pulse width, tp (s) Fig.4. Transient thermal impedance. Z th j-mb = f(t); parameter = t p /T P tp = tp/t October 999 3 Rev.6
PHP69N3LT, PHB69N3LTT 5 45 4 rain Current, I () VGS = V 5 V 4.5 V Tj = 5 C 3 V Transconductance, gfs (S) 5 45 4 Tj = 5 C VS > I X RS(ON) 35 3.8 V 35 3 75 C 5.6 V 5 5 5.4 V. V..4.6.8..4.6.8 rain-source Voltage, VS (V) Fig.5. Typical output characteristics, T j = 5 C. I = f(v S ); parameter V GS V 5 5 5 5 5 3 35 4 rain current, I () Fig.8. Typical transconductance, T j = 5 C. g fs = f(i ) rain-source On Resistance, RS(on) (Ohms).. V.4 V.6 V.9.8.7.6.5.4.3...8V Tj = 5 C VGS =4.5 V 5 5 5 3 35 4 45 5 rain Current, I () Fig.6. Typical on-state resistance, T j = 5 C. R S(ON) = f(i ); parameter V GS 5 V 3 V V Normalised On-state Resistance.9.8.7.6.5.4.3...9.8.7.6.5.4.3.. -6-4 - 4 6 8 4 6 8 Junction temperature, Tj (C) Fig.9. Normalised drain-source on-state resistance. a = R S(ON) /R S(ON)5 C = f(t j ) rain current, I () 5 VS > I X RS(ON) 45 4 35 3 5 5 5 75 C Tj = 5 C.5.5.5 3 3.5 4 4.5 5 Gate-source voltage, VGS (V) Fig.7. Typical transfer characteristics. I = f(v GS ) ; conditions: V S = 5 V; parameter T j Threshold Voltage, VGS(TO) (V).5.75.5.5.75.5.5 maximum typical minimum -6-4 - 4 6 8 4 6 8 Junction Temperature, Tj (C) Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I = m; V S = V GS October 999 4 Rev.6
PHP69N3LT, PHB69N3LTT.E-.E-.E-3.E-4.E-5.E-6 rain current, I () VS = 5 V minimum typical maximum.5.5.5 3 Gate-source voltage, VGS (V) Fig.. Sub-threshold drain current. I = f(v GS) ; conditions: T j = 5 C; V S = V GS 5 4 3 9 8 7 6 5 4 3 Gate-source voltage, VGS (V) I = 69 Tj = 5 C V = 5 V 5 5 5 3 35 4 45 5 Gate charge, QG (nc) Fig.3. Typical turn-on gate-charge characteristics. V GS = f(q G ); parameter V S Capacitances, Ciss, Coss, Crss (pf) Ciss Coss Crss. rain-source Voltage, VS (V) Fig.. Typical capacitances, C iss, C oss, C rss. C = f(v S ); conditions: V GS = V; f = MHz 5 45 4 35 3 5 5 5 Source-rain iode Current, IF () VGS = V 75 C Tj = 5 C...3.4.5.6.7.8.9...3.4.5 Source-rain Voltage, VSS (V) Fig.4. Typical reverse diode current. I F = f(v SS ); conditions: V GS = V; parameter T j October 999 5 Rev.6
PHP69N3LT, PHB69N3LTT MECHNICL T Plastic single-ended package; heatsink mounted; mounting hole; 3-lead TO- SOT78 E P q L () L Q L b 3 b c e e 5 mm scale IMENSIONS (mm are the original dimensions) () UNIT b b c E e L L L P 4.5.39.9.3.7 5.8 6.4.3 5. 3.3 3.8 mm.54 3. 4..7.7..4 5. 5.9 9.7 3.5.79 3.6 q 3..7 Q.6. Note. Terminals in this zone are not tinned. OUTLINE VERSION REFERENCES IEC JEEC EIJ EUROPEN PROJECTION ISSUE TE SOT78 TO- 97-6- Fig.5. SOT78 (TOB); pin connected to mounting base (Net mass:g) Notes. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling.. Refer to mounting instructions for SOT78 (TOB) package. 3. Epoxy meets UL94 V at /8". October 999 6 Rev.6
PHP69N3LT, PHB69N3LTT MECHNICL T Plastic single-ended surface mounted package (Philips version of -PK); 3 leads (one lead cropped) SOT44 E mounting base H 3 L p b c e e Q.5 5 mm scale IMENSIONS (mm are the original dimensions) UNIT mm 4.5 4. b c.4.7.85.6.64.46.6. E e L p H Q.3 9.7.54.9. 5.4 4.8.6. OUTLINE VERSION REFERENCES IEC JEEC EIJ EUROPEN PROJECTION ISSUE TE SOT44 98--4 99-6-5 Fig.6. SOT44 surface mounting package. Centre pin connected to mounting base. Notes. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling.. Refer to SM Footprint esign and Soldering Guidelines, ata Handbook SC8. 3. Epoxy meets UL94 V at /8". October 999 7 Rev.6
PHP69N3LT, PHB69N3LTT MOUNTING INSTRUCTIONS imensions in mm.5 9. 7.5. 3.8 5.8 Fig.7. SOT44 : soldering pattern for surface mounting. October 999 8 Rev.6
PHP69N3LT, PHB69N3LTT MECHNICL T Plastic single-ended surface mounted package (Philips version of -PK); 3 leads (one lead cropped) SOT48 seating plane y E b mounting base E H E L 3 L L b b w M c e e mm scale IMENSIONS (mm are the original dimensions) UNIT mm.38. Note. Measured from heatsink back to lead. OUTLINE VERSION ().65.45 b b b.89.7.89.7..9 5.36 5.6 c.4. 6. 5.98 4.8 4.45 REFERENCES E 6.73 6.47 IEC JEEC EIJ E min. 4. H E L e e L min..85 4.57.4 9.6.95.55.5 L.7.5 EUROPEN PROJECTION w y.. ISSUE TE SOT48 98-4-7 Fig.8. SOT48 surface mounting package. Centre pin connected to mounting base. Notes. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling.. Refer to SM Footprint esign and Soldering Guidelines, ata Handbook SC8. 3. Epoxy meets UL94 V at /8". October 999 9 Rev.6
PHP69N3LT, PHB69N3LTT MOUNTING INSTRUCTIONS imensions in mm 7. 7..5.5.5 4.57 Fig.9. SOT48 : soldering pattern for surface mounting. October 999 Rev.6
PHP69N3LT, PHB69N3LTT EFINITIONS ata sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the bsolute Maximum Rating System (IEC 34). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 999 ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT PPLICTIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 999 Rev.6