dvancd G2432B 2-WIRE 32 Bits rial EEPROM opyright 2014 Giantc miconductor Inc. (Giantc). ll rights rsrvd. Giantc rsrvs th right to mak changs to this spcification and its products at any tim without notic. Giantc products ar not dsignd, intndd, authorizd or warrantd for us as componnts in systms or quipmnt intndd for critical mdical or surgical quipmnt, arospac or military, or othr applications plannd to support or sustain lif. It is th customr's obligation to optimiz th dsign in thir own products for th bst prformanc and optimization on th functionality and tc. Giantc assums no liability arising out of th application or us of any information, products or srvics dscribd hrin. ustomrs ar advisd to obtain th latst vrsion of this dvic spcification bfor rlying on any publishd information and prior placing ordrs for products. 2 1/27
abl of ontnts 1. Faturs... 3 2. Gnral Dscription... 3 3. Functional Block Diagram... 4 4. Pin onfiguration... 5 4.1 8-Pin OI, OP, PDIP and MOP... 5 4.2 8-Lad UDFN and XDFN... 5 4.3 5-Pin O23... 5 4.4 Pin Dfinition... 5 4.5 Pin Dscriptions... 6 5. Dvic Opration... 7 5.1 2-WIRE Bus... 7 5.2 h Bus Protocol... 7 5.3 tart ondition... 7 5.4 top ondition... 7 5.5 cknowldg... 7 5.6 Rst... 7 5.7 tandby Mod... 7 5.8 Dvic ddrssing... 7 5.9 Writ Opration... 7 5.10 Rad Opration... 8 5.11 Diagrams... 10 5.12. iming Diagrams... 13 6. Elctrical haractristics... 14 6.1 bsolut Maximum Ratings... 14 6.2 Oprating Rang... 14 6.3 apacitanc... 14 6.4 D Elctrical haractristic... 15 6.5 Elctrical haractristic... 16 7. Ordring Information... 17 8. op Markings... 18 8.1 OI packag... 18 8.2 OP packag... 18 8.3 PDIP packag... 18 8.4 UDFN packag... 18 8.5 MOP Packag... 19 8.6 XDFN Packag... 19 8.7 O23 Packag... 19 9. Packag Information... 20 9.1 OI... 20 9.2 OP... 21 9.3 PDIP... 22 9.4 UDFN... 23 9.5 MOP... 24 9.6 XDFN... 25 9.7 O23... 26 10. Rvision History... 27 2 2/27
1. Faturs wo-wir rial Intrfac, I 2 M ompatibl Bi-dirctional data transfr protocol Wid-voltag Opration V = 1.7V to 5.5V pd: 400 Hz (1.7V) and 1 MHz (2.5V~5.5V) tandby currnt (max.): 1, 5.5V Rad currnt (max.): 0.5 m, 5.5V Writ currnt (max.): 0.8 m, 5.5V Hardwar Data Protction Writ Protct Pin quntial & Random Rad Faturs Mmory organization: 32b (4,096 x 8) Pag iz: 32 byts Pag writ mod Partial pag writs allowd ddition writ lockabl pag (Idntification Pag) lf timd writ cycl: 5 ms (max.) Nois immunity on inputs, bsids chmitt triggr High-rliability Enduranc: 1 million cycls Data rtntion: 100 yars ED Protction > 4000V Industrial grad Packags: OI, OP, PDIP, UDFN, MOP, XDFN and O23 Lad-fr, RoH, Halogn fr, Grn 2. Gnral Dscription h G2432B is an industrial standard lctrically rasabl programmabl rad only mmory (EEPROM) dvic that utilizs th industrial standard 2-wir intrfac for communications. h G2432B contains a mmory array of 32 bits (4,096x8), which is organizd in 32-byt pr pag. h EEPROM oprats in a wid voltag rang from 1.7V to 5.5V, which fits most application. h product provids low-powr oprations and low standby currnt. h dvic is offrd in Lad-fr, RoH, halogn fr or Grn packag. h availabl packag typs ar 8-pin OI, OP, PDIP, UDFN, MOP, XDFN and O23. h G2432B is compatibl to th standard 2-wir bus protocol. h simpl bus consists of rial lock (L) and rial Data (D) signals. Utilizing such bus protocol, a Mastr dvic, such as a microcontrollr, can usually control on or mor lav dvics, alik this G2432B. h bit stram ovr th D lin includs a sris of byts, which idntifis a particular lav dvic, an instruction, an addrss within that lav dvic, and a sris of data, if appropriat. h G2432B also has a Writ Protct function via WP pin to cas from ovrwriting th data stord insid th mmory array. In ordr to rfrain th stat machin from ntring into a wrong stat during powr-up squnc or a powr toggl off-on condition, a powr on rst circuit is mbddd. During powr-up, th dvic dos not rspond to any instructions until th supply voltag (V ) has rachd an accptabl stabl lvl abov th rst thrshold voltag. Onc V passs th powr on rst thrshold, th dvic is rst and ntrs into th tandby mod. his would also avoid any inadvrtnt Writ oprations during powr-up stag. During powr-down procss, th dvic will ntr into standby mod, onc V drops blow th powr on rst thrshold voltag. In addition, th dvic will b in standby mod aftr rciving th top command, providd that no intrnal writ opration is in progrss. Nvrthlss, it is illgal to snd a command unlss th V is within its oprating lvl. his product offrs an additional pag (Idntification Pag) of 32 byts. h Idntification Pag can b usd to stor snsitiv application paramtrs which can b (latr) prmanntly lockd in Rad-only mod. 2 3/27
3. Functional Block Diagram V 8 HIGH VOLGE GENEROR IMING & ONROL D L WP 5 6 7 LVE DDRE REGIER & OMPROR ONROL LOGI X DEODER EEPROM RRY 0 1 2 1 2 3 WORD DDRE OUNER Y DEODER GND 4 nmo LO DI/O D REGIER 2 4/27
4. Pin onfiguration 4.1 8-Pin OI, OP, PDIP and MOP op Viw 4.2 8-Lad UDFN and XDFN op Viw 0 1 8 V 0 1 8 V 1 2 7 WP 1 2 7 WP 2 3 6 L 2 3 6 L GND 4 5 D GND 4 5 D 4.3 5-Pin O23 op Viw L 1 5 WP GND 2 D 3 4 V 4.4 Pin Dfinition Pin No. Pin Nam I/O Dfinition 1 0 I Dvic ddrss Input 2 1 I Dvic ddrss Input 3 2 I Dvic ddrss Input 4 GND - Ground 5 D I/O rial ddrss, Data input and Data output 6 L I rial lock Input 7 WP I Writ Protct Input 8 V - Powr upply 2 5/27
4.5 Pin Dscriptions L his input clock pin is usd to synchroniz th data transfr to and from th dvic. D h D is a bi-dirctional pin usd to transfr addrsss and data into and out of th dvic. h D pin is an opn drain output and can b wird with othr opn drain or opn collctor outputs. Howvr, th D pin rquirs a pull-up rsistor connctd to th powr supply. 0, 1, 2 h 0, 1 and 2 ar th dvic addrss inputs. ypically, th 0, 1, and 2 pins ar for hardwar addrssing and a total of 8 dvics can b connctd on a singl bus systm. Whn 0, 1, and 2 ar lft floating, th inputs ar dfaultd to zro. WP WP is th Writ Protct pin. Whil th WP pin is connctd to th powr supply of G2432B, th ntir array bcoms Writ Protctd (i.. th dvic bcoms Rad only). Whn WP is tid to Ground or lft floating, th normal writ oprations ar allowd. V upply voltag GND Ground of supply voltag 2 6/27
5. Dvic Opration h G2432B srial intrfac supports communications using industrial standard 2-wir bus protocol, such as I 2. 5.1 2-WIRE Bus h two-wir bus is dfind as rial Data (D), and rial lock (L). h protocol dfins any dvic that snds data onto th D bus as a transmittr, and th rciving dvics as rcivrs. h bus is controlld by Mastr dvic that gnrats th L, controls th bus accss, and gnrats th tart and top conditions. h G2432B is th lav dvic. 5.2 h Bus Protocol Data transfr may b initiatd only whn th bus is not busy. During a data transfr, th D lin must rmain stabl whnvr th L lin is high. ny changs in th D lin whil th L lin is high will b intrprtd as a tart or top condition. h stat of th D lin rprsnts valid data aftr a tart condition. h D lin must b stabl for th duration of th High priod of th clock signal. h data on th D lin may b changd during th Low priod of th clock signal. hr is on clock puls pr bit of data. Each data transfr is initiatd with a tart condition and trminatd by a top condition. 5.3 tart ondition h tart condition prcds all commands to th dvic and is dfind as a High to Low transition of D whn L is High. h EEPROM monitors th D and L lins and will not rspond until th tart condition is mt. 5.4 top ondition h top condition is dfind as a Low to High transition of D whn L is High. ll oprations must nd with a top condition. 5.5 cknowldg ftr a succssful data transfr, ach rciving dvic is rquird to gnrat an. h cknowldging dvic pulls down th D lin. 5.6 Rst h G2432B contains a rst function in cas th 2-wir bus transmission on is accidntally intrruptd (.g. a powr loss), or nds to b trminatd mid-stram. h rst is initiatd whn th Mastr dvic crats a tart condition. o do this, it may b ncssary for th Mastr dvic to monitor th D lin whil cycling th L up to nin tims. (For ach clock signal transition to High, th Mastr chcks for a High lvl on D.) 5.7 tandby Mod Whil in standby mod, th powr consumption is minimal. h G2432B ntrs into standby mod during on of th following conditions: a) ftr Powr-up, whil no Op-cod is snt; b) ftr th compltion of an opration and followd by th top signal, providd that th prvious opration is not Writ rlatd; or c) ftr th compltion of any intrnal writ oprations. 5.8 Dvic ddrssing h Mastr bgins a transmission on by snding a tart condition, thn snds th addrss of th particular lav dvics to b communicatd. h lav dvic addrss is 8 bits format as shown in Figur. 5-5. h four most significant bits of th lav addrss ar fixd (1010) for G2432B. h nxt thr bits, 0, 1 and 2, of th lav addrss ar spcifically rlatd to EEPROM. Up to ight G2432B units can b connctd to th 2-wir bus. h last bit of th lav addrss spcifis whthr a Rad or Writ opration is to b prformd. Whn this bit is st to 1, Rad opration is slctd. Whil it is st to 0, Writ opration is slctd. ftr th Mastr transmits th tart condition and lav addrss byt appropriatly, th associatd 2-wir lav dvic, G2432B, will rspond with on th D lin. hn G2432B will pull down th D on th ninth clock cycl, signaling that it rcivd th ight bits of data. h G2432B thn prpars for a Rad or Writ opration by monitoring th bus. 5.9 Writ Opration 5.9.1 Byt Writ In th Byt Writ mod, th Mastr dvic snds th tart 2 7/27
condition and th lav addrss information (with th R/W st to Zro) to th lav dvic. ftr th lav gnrats an, th Mastr snds th byt addrss that is to b writtn into th addrss pointr of th G2432B. ftr rciving anothr from th lav, th Mastr dvic transmits th data byt to b writtn into th addrss mmory location. h G2432B acknowldgs onc mor and th Mastr gnrats th top condition, at which tim th dvic bgins its intrnal programming cycl. Whil this intrnal cycl is in progrss, th dvic will not rspond to any rqust from th Mastr dvic. 5.9.2 Pag Writ h G2432B is capabl of 32-byt Pag-Writ opration. Pag-Writ is initiatd in th sam mannr as a Byt Writ, but instad of trminating th intrnal Writ cycl aftr th first data word is transfrrd, th Mastr dvic can transmit up to 31 mor byts. ftr th rcipt of ach data word, th EEPROM rsponds immdiatly with an on D lin, and th fiv lowr ordr data word addrss bits ar intrnally incrmntd by on, whil th highr ordr bits of th data word addrss rmain constant. If a byt addrss is incrmntd from th last byt of a pag, it rturns to th first byt of that pag. If th Mastr dvic should transmit mor than 32 byts prior to issuing th top condition, th addrss countr will roll ovr, and th prviously writtn data will b ovrwrittn. Onc all 32 byts ar rcivd and th top condition has bn snt by th Mastr, th intrnal programming cycl bgins. t this point, all rcivd data is writtn to th G2432B in a singl Writ cycl. ll inputs ar disabld until compltion of th intrnal Writ cycl. 5.9.3 cknowldg () Polling h disabling of th inputs can b usd to tak advantag of th typical Writ cycl tim. Onc th top condition is issud to indicat th nd of th host's Writ opration, th G2432B initiats th intrnal Writ cycl. polling can b initiatd immdiatly. his involvs issuing th tart condition followd by th lav addrss for a Writ opration. If th EEPROM is still busy with th Writ opration, no will b rturnd. If th G2432B has compltd th Writ opration, an will b rturnd and th host can thn procd with th nxt Rad or Writ opration. 5.9.4 Writ Idntification Pag h Idntification Pag (32 byts) is an additional pag which can b writtn and (latr) prmanntly lockd in Rad-only mod. It is writtn by issuing th Writ Idntification Pag instruction. his instruction uss th sam protocol and format as Pag Writ (into mmory array), xcpt for th following diffrncs: Dvic typ idntifir = 1011b MB addrss bits 14/5 ar don't car xcpt for addrss bit 10 which must b 0. LB addrss bits 4/0 dfin th byt addrss insid th Idntification pag. If th Idntification pag is lockd, th data byts transfrrd during th Writ Idntification Pag instruction ar not acknowldgd (Nock). 5.9.5 Lock Idntification Pag h Lock Idntification Pag instruction (Lock ID) prmanntly locks th Idntification pag in Rad-only mod. h Lock ID instruction is similar to Byt Writ (into mmory array) with th following spcific conditions: Dvic typ idntifir = 1011b. ddrss bit 10 must b 1 ; all othr addrss bits ar don't car. h data byt must b qual to th binary valu xxxx xx1x, whr x is don't car. 5.10 Rad Opration Rad oprations ar initiatd in th sam mannr as Writ oprations, xcpt that th (R/W) bit of th lav addrss is st to 1. hr ar thr Rad opration options: currnt addrss rad, random addrss rad and squntial rad. 5.10.1 urrnt ddrss Rad h G2432B contains an intrnal addrss countr which maintains th addrss of th last byt accssd, incrmntd by on. For xampl, if th prvious opration is ithr a Rad or Writ opration addrssd to th addrss location n, th intrnal addrss countr would incrmnt to addrss location n+1. Whn th EEPROM 2 8/27
rcivs th lav ddrssing Byt with a Rad opration (R/W bit st to 1 ), it will rspond an and transmit th 8-bit data byt stord at addrss location n+1. h Mastr should not acknowldg th transfr but should gnrat a top condition so th G2432B discontinus transmission. If 'n' is th last byt of th mmory, th data from location '0' will b transmittd. (Rfr to Figur 5-8. urrnt ddrss Rad Diagram.) 5.10.2 Random ddrss Rad lctiv Rad oprations allow th Mastr dvic to slct at random any mmory location for a Rad opration. h Mastr dvic first prforms a 'dummy' Writ opration by snding th tart condition, lav addrss and byt addrss of th location it wishs to rad. ftr th G2432B acknowldgs th byt addrss, th Mastr dvic rsnds th tart condition and th lav addrss, this tim with th R/W bit st to on. h EEPROM thn rsponds with its and snds th data rqustd. h Mastr dvic dos not snd an but will gnrat a top condition. (Rfr to Figur 5-9. Random ddrss Rad Diagram.) 5.10.3 quntial Rad quntial Rads can b initiatd as ithr a urrnt ddrss Rad or Random ddrss Rad. ftr th G2432B snds th initial byt squnc, th Mastr dvic now rsponds with an indicating it rquirs additional data from th G2432B. h EEPROM continus to output data for ach rcivd. h Mastr dvic trminats th squntial Rad opration by pulling D High (no ) indicating th last data word to b rad, followd by a top condition. h data output is squntial, with th data from addrss n followd by th data from addrss n+1,n+2... tc. h addrss countr incrmnts by on automatically, allowing th ntir mmory contnts to b srially rad during squntial Rad opration. Whn th mmory addrss boundary of th array is rachd, th addrss countr rolls ovr to addrss 0, and th dvic continus to output data. (Rfr to Figur 5-10. quntial Rad Diagram). 5.10.4 Rad Idntification Pag h Idntification Pag (32 byts) is an additional pag which can b writtn and (latr) prmanntly lockd in Rad-only mod. h Idntification Pag can b rad by issuing an Rad Idntification Pag instruction. his instruction uss th sam protocol and format as th Random ddrss Rad (from mmory array) with dvic typ idntifir dfind as 1011b. h MB addrss bits 14/6 ar don't car, th LB addrss bits 5/0 dfin th byt addrss insid th Idntification Pag. h numbr of byts to rad in th ID pag must not xcd th pag boundary (.g.: whn rading th Idntification Pag from location 10d, th numbr of byts should b lss than or qual to 22, as th ID pag boundary is 32 byts). 5.10.5 Rad th lock status h lockd/unlockd status of th Idntification pag can b chckd by transmitting a spcific truncatd command [Idntification Pag Writ instruction + on data byt] to th dvic. h dvic rturns an acknowldg bit if th Idntification pag is unlockd, othrwis a Nock bit if th Idntification pag is lockd. Right aftr this, it is rcommndd to transmit to th dvic a tart condition followd by a top condition, so that: tart: th truncatd command is not xcutd bcaus th tart condition rsts th dvic intrnal logic, top: th dvic is thn st back into tandby mod by th top condition. 2 9/27
R ONDIION OP ONDIION G2432B 5.11 Diagrams Figur 5-1. ypical ystm Bus onfiguration V D L Mastr ransmittr/rcivr G24XX Figur 5-2. output cknowldg L from Mastr 1 8 9 Data Output from ransmittr Data Output from Rcivr Figur 5-3. tart and top onditions L D Figur 5-4. Data Validity Protocol Data hang L D Data tabl Data tabl 2 10/27
Figur 5-5. lav ddrss Bit 7 6 5 4 3 2 1 0 1 0 1 0 2 1 0 R/W D Bus ctivity R M B Figur 5-6. Byt Writ W R I Dvic ddrss E Word ddrss Word ddrss Data * * * * L B R/W M B * =Don t car bits O P Figur 5-7. Pag Writ D Bus ctivity R M B W R I Dvic ddrss E Word ddrss(n) Word ddrss(n) Data(n) * * * * L B R/W M B * =Don t car bits Data(n+1) Data(n+31) O P Figur 5-8. urrnt ddrss Rad D Bus ctivity R M B Dvic ddrss L B R E D R/W Data N O O P 2 11/27
Figur 5-9. Random ddrss Rad D Bus ctivity R M B Dvic ddrss W R I Word E ddrss(n) * * * * L B R/W DUMMY WRIE Word ddrss(n) * =Don t car bits R Dvic ddrss R E D Data n N O O P Figur 5-10. quntial Rad D Bus ctivity Dvic ddrss R E D R/W Data Byt n Data Byt n+1 Data Byt n+2 Data Byt n+x N O O P 2 12/27
5.12. iming Diagrams Figur 5-11. Bus iming R F HIGH LOW U:O L U: HD: HD:D U:D BUF DIN DH DOU U:WP HD:WP WP Figur 5-12. Writ ycl iming L D Word n WR OP ondition R ondition 2 13/27
6. Elctrical haractristics 6.1 bsolut Maximum Ratings ymbol Paramtr Valu Unit V upply Voltag -0.5 to + 6.5 V V P Voltag on ny Pin -0.5 to + 6.5 V BI mpratur Undr Bias 55 to +125 G torag mpratur 65 to +150 I OU Output urrnt 5 m Not: trss gratr than thos listd undr bsolut Maximum Ratings may caus prmannt damag to th dvic. his is a strss rating only and functional opration of th dvic at ths or any othr condition outsid thos indicatd in th oprational sctions of this spcification is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct rliability. 6.2 Oprating Rang Rang mbint mpratur () V Industrial 40 to +85 1.7V to 5.5V Not: Giantc offrs Industrial grad for ommrcial applications (0 to +70 ). 6.3 apacitanc ymbol Paramtr [1, 2] onditions Max. Unit IN Input apacitanc V IN = 0V 6 pf I/O Input / Output apacitanc V I/O = 0V 8 pf Nots: [1] std initially and aftr any dsign or procss changs that may affct ths paramtrs and not 100% tstd. [2] st conditions: = 25, f = 1 MHz, V = 5.0V. 2 14/27
6.4 D Elctrical haractristic Industrial: = 40 to +85, V = 1.7V ~ 5.5V ymbol Paramtr [1] V st onditions Min. yp. Max. Unit V upply Voltag 1.7 5.5 V V IH Input High Voltag 0.7*V V +1 V V IL Input Low Voltag -0.5 0.3* V V I LI Input Lakag urrnt 5 V V IN = V max 2 μ I LO Output Lakag 5V 2 μ urrnt V OL1 Output Low Voltag 1.7V I OL = 0.15 m 0.2 V V OL2 Output Low Voltag 2.5V I OL = 2.1 m 0.4 V I B1 tandby urrnt 1.7V V IN = V or GND 0.2 1 μ I B2 tandby urrnt 2.5V V IN = V or GND 0.3 1 μ I B3 tandby urrnt 5.5V V IN = V or GND 0.5 1 μ 1.7V Rad at 400 Hz 0.15 m I 1 I 2 Rad urrnt 2.5V Rad at 1 MHz 0.2 m 5.5V Rad at 1 MHz 0.5 m 1.7V Writ at 400 Hz 0.5 m Writ urrnt 2.5V Writ at 1 MHz 0.6 m 5.5V Writ at 1 MHz 0.8 m Not: h paramtrs ar charactrizd but not 100% tstd. 2 15/27
6.5 Elctrical haractristic Industrial: = 40 to +85, upply voltag = 1.7V to 5.5V ymbol Paramtr [1] [2] 1.7V V<2.5V 2.5V V 5.5V Unit Min. Max. Min. Max. F L lock Frquncy 400 1000 Hz LOW lock Low Priod 1200 600 ns HIGH lock High Priod 600 400 ns R Ris im (L and D) 300 300 ns F Fall im (L and D) 300 100 ns U: tart ondition tup im 500 200 ns U:O top ondition tup im 500 200 ns HD: tart ondition Hold im 500 200 ns U:D Data In tup im 100 40 ns HD:D Data In Hold im 0 0 ns DH lock to Output ccss tim (L Low to D Data Out Valid) Data Out Hold im (L Low to D Data Out hang) 100 900 50 400 ns 100 50 ns WR Writ ycl im 5 5 ms BUF Bus Fr im Bfor Nw ransmission 1000 400 ns U:WP WP pin tup im 1000 600 ns HD:WP WP pin Hold im 1000 400 ns Nots: Nois upprssion im 100 50 ns [1] h paramtrs ar charactrizd but not 100% tstd. [2] masurmnt conditions: R L (conncts to V ): 1.3 kω (2.5V, 5.0V), 10 kω (1.7V) L = 100 pf Input puls voltags: 0.3*V to 0.7*V Input ris and fall tims: 50 ns iming rfrnc voltags: half V lvl 2 16/27
7. Ordring Information Industrial Grad: -40 to +85, Lad-fr Voltag Rang Part Numbr* Packag 1.7V to 5.5V G2432B-2GLI-R 150-mil OI G2432B-2ZLI-R 3 x 4.4 mm OP G2432B-2UDLI-R 2 x 3 x 0.55 mm UDFN G2432B-2PLI 300mil PDIP G2432B-2LI-R 3 x 3 mm MOP G2432B-2XDLI-R 1.8 x 2.2 x 0.4 mm XDFN G2432B-2FLI-R 2.9 x 1.6 mm O23 * 1. ontact Giantc als Rprsntativs for availability and othr packag information. 2. h product is packd in tap and rl -R (4 pr rl), xcpt UDFN is 5 pr rl, O23 is 3 pr rl. 3. Rfr to Giantc wbsit for rlatd dclaration documnt on lad fr, RoH, halogn fr or Grn, whichvr is applicabl. 4. Giantc offrs Industrial grad for ommrcial applications (0 to +70 ). 2 17/27
8. op Markings 8.1 OI packag G: Giantc Logo 432B-2GLI: G2432B-2GLI-R YWW: Dat od, Y=yar, WW=wk 8.2 OP packag G: Giantc Logo 432B-2ZLI: G2432B-2ZLI-R YWW: Dat od, Y=yar, WW=wk 8.3 PDIP packag G: Giantc Logo 2432B-2PLI: G2432B-2PLI YWW: Dat od, Y=yar, WW=wk 8.4 UDFN packag G: Giantc Logo 45B: G2432B-2UDLI-R YWW: Dat od, Y=yar, WW=wk 2 18/27
8.5 MOP Packag G: Giantc Logo 432B2U: G2432B-2LI-R YWW: Dat od, Y=yar, WW=wk 8.6 XDFN Packag 45B: G2432B-2XDLI-R YWW: Dat od, Y=yar, WW=wk 8.7 O23 Packag 432B: G2432B-2FLI-R YW: Dat od, Y=yar, WW=wk 2 19/27
9. Packag Information 9.1 OI 8L 150mil OI Packag Outlin Dtail D E1 E ZD b Dtail GUGE PLNE 1 EING PLNE L1 L Θ YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX 1.35 -- 1.75 0.053 -- 0.069 1 0.10 -- 0.25 0.004 -- 0.010 b 0.33 -- 0.51 0.013 -- 0.020 D 4.80 -- 5.00 0.189 -- 0.197 E 5.80 -- 6.20 0.228 -- 0.244 E1 3.80 -- 4.00 0.150 -- 0.157 L 0.38 1.27 B. -- 1.27 0.015 0.050 B. 0.050 L1 ZD Θ 0 0.25 B. 0.545 REF. -- 8 0 0.010 B. 0.021 REF. -- 8 Not: 1. ontrolling Dimnsion:MM 2. Dimnsion D and E1 do not includ Mold protrusion 3. Dimnsion b dos not includ dambar protrusion/intrusion. 4. Rfr to Jdc standard M-012 5. Drawing is not to scal 2 20/27
9.2 OP 8L 3x4.4mm OP Packag Outlin 8 D L E E1 1 12 (4X) Θ b 2 0.10mm Not: 1. ontrolling Dimnsion:MM 2. Dimnsion D and E do not includ Mold protrusion 3. Dimnsion b dos not includ dambar protrusion/intrusion. 4. Rfr to Jdc standard MO-153 5. Drawing is not to scal 6. Packag may hav xposd ti bar. 1 YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX -- -- 1.20 -- -- 0.047 1 0.05 -- 0.15 0.002 -- 0.006 2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 -- 0.30 0.007 -- 0.012 c 0.09 -- 0.20 0.004 -- 0.008 D 2.90 3.00 3.10 0.114 0.118 0.122 E 4.30 4.40 4.50 0.169 0.173 0.177 E1 L 0.45 6.4 B 0.65 B 0.60 0.75 0.018 0.252 B 0.026 B 0.024 0.030 Θ 0 -- 8 0 -- 8 2 21/27
9.3 PDIP 8L 300mil PDIP Packag Outlin D E1 E B ZD 2 1 L b3 b Not: 1. ontrolling Dimnsion:MM 2. Dimnsion D and E1 do not includ Mold protrusion 3. Dimnsion b2 and b3 do not includ dambar protrusion/instrusion 4. Drawing is not to scal YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX 3.60 -- 4.20 0.142 -- 0.165 1 0.38 -- 0.75 0.015 -- 0.030 2 3.25 -- 3.45 0.128 -- 0.136 b 0.36 -- 0.56 0.014 -- 0.022 b2 1.40 -- 1.65 0.055 -- 0.065 b3 0.81 -- 1.17 0.032 -- 0.046 D 9.01 -- 9.53 0.355 -- 0.375 E 7.49 -- 8.26 0.295 -- 0.325 E1 6.20 -- 6.60 0.244 -- 0.260 2.54 B. 0.100 B. B 8.12 -- 9.65 0.320 -- 0.380 L 3.18 -- 3.80 0.125 -- 0.150 ZD 0.825 REF. 0.032 REF. 2 22/27
9.4 UDFN 8L 2x3mm UDFN Packag Outlin D D2 E E2 L PIN#1 IDENIFIION HMFER PIN#1 DO BY MRING OP VIEW BOOM VIEW b 1 2 IDE VIEW YMBOL Not: DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX 0.50 0.55 0.60 0.020 0.022 0.024 1 0.00 -- 0.05 0.000 -- 0.002 b 0.18 0.25 0.30 0.007 0.010 0.012 2 D D2 1.25 0.152 REF 2.00 B 1.40 1.50 0.049 0.006 REF 0.079 B 0.055 0.059 E 3.00 B 0.118 B E2 1.15 1.30 1.40 0.045 0.051 0.055 0.40 0.50 B. -- -- 0.016 0.020 B. -- -- L 0.20 0.30 0.40 0.008 0.012 0.016 1. ontrolling Dimnsion:MM 2. Drawing is not to scal 2 23/27
9.5 MOP 8L 120mil MOP packag Outlin D L E E1 12 (4X) 2 θ 1 b YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX -- -- 1.10 -- -- 0.043 1 0.05 -- 0.15 0.002 -- 0.006 2 0.75 0.85 0.95 0.030 0.033 0.037 b 0.25 -- 0.40 0.010 -- 0.016 0.13 -- 0.23 0.005 -- 0.009 D 2.90 3.00 3.10 0.114 0.118 0.122 E 2.90 3.00 3.10 0.114 0.118 0.122 E1 L -- 4.90 B 0.65 B -- 0.55 -- 0.193 B 0.026 B -- 0.022 Θ 0 -- 7 0 -- 7 Not: 1. ontrolling Dimnsion:MM 2. Dimnsion D and E do not includ Mold protrusion 3. Rfr to Jdc standard MO187 4. Drawing is not to scal 2 24/27
9.6 XDFN 8L 1.8x2.2mm XDFN Packag Outlin 1 D L E E1 0.10 0.10 PIN#1 ID 0.15 b PIN#1 DO BY MRING OP VIEW D1 BOOM VIEW 1 YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX -- -- 0.40 -- -- 0.016 1 0.00 -- 0.05 0.000 -- 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 1.70 1.80 1.90 0.067 0.071 0.075 E 2.10 2.20 2.30 0.083 0.087 0.091 D1 E1 1 1.30B 1.00B 1.20REF 0.05B 0.04B 0.047REF L 0.26 0.40YP 0.30 0.35 0.010 0.02YP 0.012 0.014 IDE VIEW Not: 1. ontrolling Dimnsion:MM 2. Drawing is not to scal 2 25/27
9.7 O23 5L 2.9x1.6mm O23 Packag Outlin D b 0.25 L E1 E Θ c 1 2 Not: 1. Dimnsion D and E1 do not includ Mold protrusion 2. Dimnsion b dos not includ dambar protrusion/intrusion. 3. Rfr to Jdc standard MO-193 B 4. Drawing is not to scal 1 YMBOL DIMENION IN MILLIMEER DIMENION IN INHE MIN NOM MX MIN NOM MX -- -- 1.250 -- -- 0.049 1 0.000 -- 0.150 0.000 -- 0.006 2 1.000 1.100 1.200 0.039 0.043 0.047 b 0.360 -- 0.500 0.014 -- 0.020 c 0.140 -- 0.200 0.006 -- 0.008 D 2.826 2.926 3.026 0.111 0.115 0.119 E 2.600 2.800 3.000 0.102 0.110 0.118 E1 1.526 1.626 1.726 0.060 0.064 0.068 1 L 0.350 0.95(B) 1.90(B) 0.450 0.600 0.014 0.037(B) 0.075(B) 0.018 0.024 Θ 0 -- 8 0 -- 8 2 26/27
10. Rvision History Rvision Dat Dscriptions 0 May. 2014 Initial vrsion 1 Oct. 2015 Updat Vpmax & Vilmin 2 Jun. 2016 Updat tabl6.1 and tabl6.4 2 27/27