Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source Up To 00 ma description/ordering information These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of V CC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and SLFS0D SEPTEMBER 9 REVISED JUNE 00 NE...D, P, PS, OR PW PACKAGE SA...D OR P PACKAGE SE... D, JG, OR P PACKAGE (TOP VIEW) GND TRIG OUT RESET NC TRIG NC OUT NC the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 00 ma. Operation is specified for supplies of V to V. With a -V supply, output levels are compatible with TTL inputs. 8 0 9 8 8 9 0 V CC DISCH THRES CONT SE... FK PACKAGE (TOP VIEW) NC GND NC RESET NC NC VCC NC CONT NC NC No internal connection NC DISCH NC THRES NC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 00, Texas Instruments Incorporated On products compliant to MIL-PRF-8, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 ORDERING INFORMATION TA VTHRES MAX VCC = V PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING 0 C to0 C. V 0 C to 8 C C to C. V 0. V PDIP (P) Tube of 0 NEP NEP Tube of NED SOIC (D) NE Reel of 00 NEDR SOP (PS) Reel of 000 NEPSR N Tube of 0 NEPW TSSOP (PW) N Reel of 000 NEPWR PDIP (P) Tube of 0 SAP SAP SOIC (D) Tube of Reel of 000 SAD SADR SA PDIP (P) Tube of 0 SEP SEP SOIC (D) Tube of Reel of 00 SED SEDR SED CDIP (JG) Tube of 0 SEJG SEJG LCCC (FK) Tube of SEFK SEFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE RESET TRIGGER VOLTAGE THRESHOLD VOLTAGE OUTPUT DISCHARGE SWITCH Low Irrelevant Irrelevant Low On High </ VDD Irrelevant High Off High >/ VDD >/ VDD Low On High >/ VDD </ VDD As previously established Voltage levels shown are nominal. POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 functional block diagram VCC 8 CONT RESET THRES R R Î Î OUT S TRIG Î GND Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: RESET can override TRIG, which can override THRES. DISCH absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note )............................................................ 8 V Input voltage (CONT, RESET, THRES, and TRIG).............................................. V CC Output current......................................................................... ± ma Package thermal impedance, θ JA (see Notes and ): D package............................ 9 C/W P package............................ 8 C/W PS package........................... 9 C/W PW package......................... 9 C/W Package thermal impedance, θ JC (see Notes and ): FK package.......................... C/W JG package.......................... C/W Operating virtual junction temperature, T J................................................... 0 C Case temperature for 0 seconds: FK package.............................................. 0 C Lead temperature, mm (/ inch) from case for 0 seconds: D, P, PS, or PW package........ 0 C Lead temperature, mm (/ inch) from case for 0 seconds: JG package.................... 00 C Storage temperature range, T stg................................................... C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values are with respect to GND.. Maximum power dissipation is a function of TJ(max), θ JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/θ JA. Operating at the absolute maximum TJ of 0 C can affect reliability.. The package thermal impedance is calculated in accordance with JESD -.. Maximum power dissipation is a function of TJ(max), θ JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) TC)/θ JC. Operating at the absolute maximum TJ of 0 C can affect reliability.. The package thermal impedance is calculated in accordance with MIL-STD-88. POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 recommended operating conditions MIN MAX UNIT VCC Supply voltage SA, NE. SE. 8 V VI Input voltage (CONT, RESET, THRES, and TRIG) VCC V IO Output current ±00 ma NE 0 0 TA Operating free-air temperature SA 0 8 C SE POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 electrical characteristics, V CC = V to V, T A = C (unless otherwise noted) PARAMETER THRES voltage level NE SE TEST CONDITIONS SA MIN TYP MAX MIN TYP MAX VCC = V 9. 0 0. 8.8 0. VCC = V..... THRES current (see Note ) 0 0 0 0 na TRIG voltage level VCC =V VCC =V TA = C to C TA = C to C.9.8......9... TRIG current TRIG at 0 V 0. 0.9 0. µa RESET voltage level RESET current TA = C to C. 0. 0. 0. 0. RESET at VCC 0. 0. 0. 0. RESET at 0 V 0. 0.. DISCH switch off-state current 0 00 0 00 na CONT voltage (open circuit) Low-level output voltage VCC =V VCC =V TA = C to C 9. 0. TA = C to C.9.8 9. 0 0. 9 0.9..8.. VCC = V, 0. 0. 0. 0. IOL = 0 ma TA = C to C 0. VCC = V, 0. 0. 0. 0. IOL = 0 ma TA = C to C VCC = V,.. IOL = 00 ma TA = C to C. VCC = V, IOL = 00 ma.. VCC = V, IOL =. ma TA = C to C 0. VCC = V, 0. 0. 0. 0. IOL = ma TA = C to C 0.8 VCC = V, IOL = 8 ma 0. 0. 0. 0. VCC = V,... IOH = 00 ma TA = C to C High-level output voltage VCC = V, IOH = 00 ma.. V Supply current VCC = V,... IOH = 00 ma TA = C to C Output low, VCC = V 0 0 No load VCC = V Output high, VCC = V 9 0 9 No load VCC = V UNIT V V V ma V V ma NOTE : This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure. For example, when VCC = V, the maximum value is R = RA + RB. MΩ, and for VCC = V, the maximum value is 0 MΩ. POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 operating characteristics, V CC = V and V Initial error of timing interval Temperature coefficient of timing interval Supply-voltage sensitivity of timing interval Output-pulse rise time Output-pulse fall time PARAMETER Each timer, monostable Each timer, astable Each timer, monostable Each timer, astable Each timer, monostable Each timer, astable TEST CONDITIONS TA = C TA = MIN to MAX TA = C CL = pf, TA = C CL = pf, TA = C SE NE SA MIN TYP MAX MIN TYP MAX 0..*.. 0 00* 0 90 0 0.0 0.* 0. 0. 0. 0. UNIT % ppm/ C %/V 00 00* 00 00 ns 00 00* 00 00 ns * On products compliant to MIL-PRF-8, this parameter is not production tested. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = kω to 00 kω, C = 0. µf. Values specified are for a device in an astable circuit similar to Figure, with the following component values: RA = kω to 00 kω, C = 0. µf. POST OFFICE BOX 0 DALLAS, TEXAS
TYPICAL CHARACTERISTICS SLFS0D SEPTEMBER 9 REVISED JUNE 00 0 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VCC = V 0 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VCC = 0 V Low-Level Output Voltage V 0. 0. 0. 0. 0.0 TA = C TA = C TA = C Low-Level Output Voltage V 0. 0. 0. 0. 0.0 ÏÏÏÏ TA = C ÏÏÏÏ TA= C ÏÏÏÏ TA = C V OL 0.0 V OL 0.0 0.0 0.0 0.0 0 0 0 0 00 IOL Low-Level Output Current ma Figure 0.0 0 0 0 0 00 IOL Low-Level Output Current ma Figure Low-Level Output Voltage V V OL 0 0. 0. 0. 0. 0.0 0.0 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VCC = V TA = C TA = C TA = C ( V CC V ) OH Voltage Drop V DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT vs HIGH-LEVEL OUTPUT CURRENT.0 TA = C.8... 0.8 0. 0. ÏÏÏÏ TA = C TA = C 0.0 0.0 0 0 0 0 00 IOL Low-Level Output Current ma 0. 0 VCC = V to V 0 0 0 0 IOH High-Level Output Current ma 00 Figure Figure Data for temperatures below 0 C and above 0 C are applicable for SE circuits only. POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 TYPICAL CHARACTERISTICS Supply Current ma ICC 0 9 8 Output Low, No Load TA = C SUPPLY CURRENT vs SUPPLY VOLTAGE TA = C TA = C Pulse Duration Relative to Value at VCC = 0 V.0.00.00 0.99 0.990 NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs SUPPLY VOLTAGE 0 8 9 0 VCC Supply Voltage V Figure 0.98 0 0 VCC Supply Voltage V Figure 0 Pulse Duration Relative to Value at T A = C.0.00.00 0.99 0.990 NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs FREE-AIR TEMPERATURE VCC = 0 V Propagation Delay Time ns t PD 00 0 00 0 00 0 PROPAGATION DELAY TIME vs LOWEST VOLTAGE LEVEL OF TRIGGER PULSE TA = C TA = 0 C TA = C TA = 0 C TA = C 0.98 0 0 0 00 TA Free-Air Temperature C Figure 0 0 0. x VCC 0. x VCC 0. x VCC 0. x VCC Lowest Voltage Level of Trigger Pulse Figure 8 Data for temperatures below 0 C and above 0 C are applicable for SE series circuits only. 8 POST OFFICE BOX 0 DALLAS, TEXAS
APPLICATION INFORMATION SLFS0D SEPTEMBER 9 REVISED JUNE 00 monostable operation For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q. Capacitor C then is charged through R A until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q. VCC ( V to V) RA = 9. kω CL = 0.0 µf RL = kω See Figure 9 RA Input 8 CONT VCC RESET DISCH OUT THRES TRIG GND RL Output Voltage V/div Input Voltage Output Voltage Capacitor Voltage Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 9. Circuit for Monostable Operation Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high at the end of the timing interval. Because of the threshold level and saturation voltage of Q, the output pulse duration is approximately t w =.R A C. Figure is a plot of the time constant for various values of R A and C. The threshold levels and charge rates both are directly proportional to the supply voltage, V CC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to V CC. Output Pulse Duration s tw Time 0. ms/div Figure 0. Typical Monostable Waveforms 0 0 0 0 0 0 0.00 RA = 0 MΩ RA = MΩ 0.0 0. RA = 0 kω RA = kω C Capacitance µf RA = 00 kω Figure. Output Pulse Duration vs Capacitance 0 00 POST OFFICE BOX 0 DALLAS, TEXAS 9
SLFS0D SEPTEMBER 9 REVISED JUNE 00 astable operation APPLICATION INFORMATION As shown in Figure, adding a second resistor, R B, to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through R A and R B and then discharges through R B only. Therefore, the duty cycle is controlled by the values of R A and R B. This astable connection results in capacitor C charging and discharging between the threshold-voltage level ( 0. V CC ) and the trigger-voltage level ( 0. V CC ). As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. 0.0 µf VCC ( V to V) ÏÏÏÏ RA = k RL = k ÏÏÏÏ RB = k See Figure C = 0. µf RA RB C Open (see Note A) 8 CONT VCC RESET DISCH OUT THRES TRIG GND RL Output Voltage V/div t H tl Output Voltage Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Figure. Circuit for Astable Operation Capacitor Voltage Time 0. ms/div Figure. Typical Astable Waveforms 0 POST OFFICE BOX 0 DALLAS, TEXAS
APPLICATION INFORMATION SLFS0D SEPTEMBER 9 REVISED JUNE 00 astable operation (continued) Figure shows typical waveforms generated during astable operation. The output high-level duration t H and low-level duration t L can be calculated as follows: 00 k RA + RB = kω t H 0.9 (R A R B) C t L 0.9 (R B) C Other useful relationships are shown below. period t H t L 0.9 (R A R B )C frequency. (R A R B )C Output driver duty cycle t L t H t L Output waveform duty cycle t R H t H B t L R A R B Low-o- t high ratio t L R B t H R A R B R B R A R B f Free-Running Frequency Hz 0 k k 00 0 RA + RB = MΩ RA + RB = 0 MΩ 0. 0.00 0.0 0. RA + RB = 0 kω C Capacitance µf RA + RB = 00 kω 0 Figure. Free-Running Frequency 00 POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 missing-pulse detector APPLICATION INFORMATION The circuit shown in Figure can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure. Input 0.0 µf VCC ( V to V) 8 RL RESET VCC OUT TRIG DISCH CONT THRES GND RA Output C Voltage V/div VCC = V RA = kω C = 0. µf See Figure Input Voltage Output Voltage AT Capacitor Voltage Pin numbers shown are shown for the D, JG, P, PS, and PW packages. Figure. Circuit for Missing-Pulse Detector Time 0. ms/div Figure. Completed-Timing Waveforms for Missing-Pulse Detector POST OFFICE BOX 0 DALLAS, TEXAS
APPLICATION INFORMATION SLFS0D SEPTEMBER 9 REVISED JUNE 00 frequency divider By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency divider. Figure shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. VCC = V RA = 0 Ω C = 0.0 µf See Figure 9 Voltage V/div Input Voltage Output Voltage Capacitor Voltage Time 0. ms/div Figure. Divide-by-Three Circuit Waveforms pulse-width modulation The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 8 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 9 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is illustrated, any wave shape could be used. POST OFFICE BOX 0 DALLAS, TEXAS
SLFS0D SEPTEMBER 9 REVISED JUNE 00 APPLICATION INFORMATION VCC ( V to V) RA = kω ÏÏÏÏ C = 0.0 µf ÏÏÏÏ RL = kω See Figure 8 Clock Input Modulation Input (see Note A) TRIG CONT 8 RESET GND VCC OUT DISCH THRES RL RA Output C Voltage V/div ÏÏÏ Modulation Input Voltage Ï Clock Input Voltage Output Voltage Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 8. Circuit for Pulse-Width Modulation Capacitor Voltage Time 0. ms/div Figure 9. Pulse-Width-Modulation Waveforms pulse-position modulation As shown in Figure 0, any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. VCC ( V to V) 8 RL RA RA = kω RB = 00 Ω RL = kω See Figure 0 Modulation Input (see Note A) TRIG CONT RESET GND VCC OUT DISCH THRES RB C Output Voltage V/div ÏÏÏ Modulation Input Voltage Output Voltage Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 0. Circuit for Pulse-Position Modulation Ï Capacitor Voltage Time 0. ms/div Figure. Pulse-Position-Modulation Waveforms POST OFFICE BOX 0 DALLAS, TEXAS
APPLICATION INFORMATION SLFS0D SEPTEMBER 9 REVISED JUNE 00 sequential timer Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure shows a sequencer circuit with possible applications in many systems, and Figure shows the output waveforms. VCC S 0.0 µf 8 RESET VCC TRIG OUT DISCH CONT THRES GND CA RA kω 0.00 µf 0.0 µf 8 RESET VCC OUT TRIG DISCH CONT THRES GND CB RB kω 0.00 µf 0.0 µf 8 RESET VCC TRIG OUT CONT GND DISCH THRES CC RC CA = 0 µf RA = 00 kω Output A Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0. CB =. µf RB = 00 kω Output B CC =. µf RC = 00 kω Output C Figure. Sequential Timer Circuit Voltage V/div See Figure Output A ÏÏÏÏ Output B ÏÏ t wa twa =. RACA ÏÏ t wb twb =. RBCB Output C twc twc =. RCCC t = 0 t Time s/div Figure. Sequential Timer Waveforms POST OFFICE BOX 0 DALLAS, TEXAS
MECHANICAL DATA MCER00A JANUARY 99 REVISED JANUARY 99 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.00 (0,) 0. (9,00) 8 0.80 (,) 0. (,) 0.0 (,) 0.0 (,) 0.0 (,0) 0.0 (0,8) 0.00 (0,) MIN 0.0 (,8) 0.90 (,) 0.00 (,08) MAX Seating Plane 0.0 (,0) MIN 0.00 (,) 0.0 (0,8) 0.0 (0,8) 0.0 (0,) 0.008 (0,0) 0 000/C 08/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 8 GDIP-T8 POST OFFICE BOX 0 DALLAS, TEXAS
MECHANICAL DATA MLCC00B OCTOBER 99 FK (S-CQCC-N**) 8 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 8 NO. OF TERMINALS ** MIN A MAX MIN B MAX 9 0 0. (8,9) 0.8 (9,09) 0.0 (,80) 0.8 (9,09) A SQ B SQ 0 8 0 9 8 8 8 8 0. (,) 0.0 (,) 0.9 (8,8) 0.98 (,8). (8,99) 0.8 (,) 0.0 (,) 0. (9,) 0.9 (,). (9,9) 0.0 (0,) 0.9 (,8) 0.9 (,8) 0.80 (,).0 (,) 0.8 (,) 0.0 (,) 0.0 (,) 0.88 (,8).0 (,0) 0.00 (0,) 0.00 (0,) 0.080 (,0) 0.0 (,) 0.00 (0,) 0.00 (0,) 0.0 (,0) 0.0 (,) 0.0 (,) 0.0 (0,89) 0.08 (0,) 0.0 (0,) 0.00 (,) 0.0 (,) 0.0 (0,89) 000/ D 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-00 POST OFFICE BOX 0 DALLAS, TEXAS
MECHANICAL DATA MPDI00A JANUARY 99 REVISED JUNE 999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 8 0.00 (0,0) 0. (9,0) 0.0 (,0) 0.0 (,0) 0.00 (,8) MAX 0.00 (0,) MIN 0. (8,) 0.00 (,) 0.0 (0,8) 0.00 (,08) MAX Gage Plane Seating Plane 0. (,8) MIN 0.00 (0,) NOM 0.0 (0,) 0.0 (0,8) 0.00 (,) 0.00 (0,) M 0.0 (0,9) MAX 0008/D 0/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 0 DALLAS, TEXAS
MPDI00C JANUARY 99 REVISED DECEMBER 000 N (R-PDIP-T**) PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** 8 0 A A MAX 0. (9,9) 0. (9,9) 0.90 (,).00 (,9) 9 A MIN 0. (8,9) 0. (8,9) 0.80 (,9) 0.90 (,88) 0.0 (,0) 0.0 (,0) C MS-00 VARIATION AA BB AC AD 0.00 (,8) 0.0 (,) D 8 0.0 (,) 0.00 (0,) D 0.00 (0,) MIN 0. (8,) 0.00 (,) 0.0 (0,8) 0.00 (,08) MAX Gauge Plane Seating Plane 0. (,8) MIN 0.00 (0,) NOM 0.0 (0,) 0.0 (0,8) 0.00 (0,) 0.00 (,) M 0.0 (0,9) MAX /8 PIN ONLY 0 pin vendor option D 0009/E /00 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00, except 8 and 0 pin minimum body lrngth (Dim A). D. The 0 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 0 DALLAS, TEXAS
MECHANICAL DATA MPDI008 OCTOBER 99 N (R-PDIP-T**) PIN SHOWN PLASTIC DUAL-IN-LINE PACKAGE A 0.0 (,) 0.0 (,) 0.00 (,) TYP 0.00 (,08) MAX 0.00 (0,) MIN 0.0 (,9) 0.90 (,99) Seating Plane 0.0 (0,) 0.0 (0,8) 0.00 (0,) M 0.00 (,) 0. (,8) MIN 0.00 (0,) NOM 0 DIM PINS ** 8 0 8 A MAX.0.0 (,) (,8).0 (,9).090.0.0 (,09) (,) (,) A MIN.0 (,).0 (,8).0 (0,89).00 (,8).90 (0,).90 (,9) 000/ B 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-0 D. Falls within JEDEC MS-0 ( pin only) POST OFFICE BOX 0 DALLAS, TEXAS
MECHANICAL DATA MSOI00B JANUARY 99 REVISED SEPTEMBER 00 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.00 (,) 0.00 (0,) 0.0 (0,) 0.00 (0,) 8 0. (,0) 0.8 (,80) 0.008 (0,0) NOM 0. (,00) 0.0 (,8) Gage Plane A 0 8 0.00 (0,) 0.0 (,) 0.0 (0,0) Seating Plane 0.09 (,) MAX 0.00 (0,) 0.00 (0,0) 0.00 (0,0) DIM PINS ** 8 A MAX 0.9 (,00) 0. (8,) 0.9 (0,00) A MIN 0.89 0. (,80) (8,) 0.8 (9,80) 000/E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.00 (0,). D. Falls within JEDEC MS-0 POST OFFICE BOX 0 DALLAS, TEXAS
MECHANICAL DATA MTSS00C JANUARY 99 REVISED FEBRUARY 999 PW (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,0 0, 0,0 M 0,9 8,0,0,0,0 0, NOM Gage Plane A 0 8 0, 0, 0,0,0 MAX 0, 0,0 Seating Plane 0,0 DIM PINS ** 8 0 8 A MAX,0,0,0,0,90 9,80 A MIN,90,90,90,0,0 9,0 000/F 0/9 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,. D. Falls within JEDEC MO- POST OFFICE BOX 0 DALLAS, TEXAS
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