ECE Digital VLSI Design Course Syllabus Fall 2017

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ECE484-001 Digital VLSI Design Course Syllabus Fall 2017 Instructor: Dr. George L. Engel Phone: (618) 650-2806 Office: Email: URLs: Engineering Building Room EB3043 gengel@siue.edu http://www.siue.edu/~gengel http://www.ee.siue.edu/~cdsadmin Lecture: M, W: 3:00 pm 4:15 pm (EB 2150) Office Hours: See Dr. Engel s website. Course Description: Discussion of CMOS circuits, MOS transistor theory, CMOS processing technology, circuit characterization, CMOS circuit and logic design. Design and synthesis of digital systems. Laboratory exercises using Cadence design software (Composer, Virtuoso, Spectre, RTL Compiler, Silicon Encounter, etc.) Course Text: CMOS Digital Integrated Circuits, 4 th Edition Sung-Mo Kang, Yusuf Leblebici, and Chulwoo Kim Publisher: McGraw Hill (Copyright: 2015) ISBN: 978-0-07-338062-9 Grading Policy: First Exam 20% Second Exam 20% Final Exam 20% Lab and HW 20% Final project 20%

Lectures M Aug 21 W Aug 23 M Aug 28 W Aug 30 Chapter 1: Introduction Moore s Law History of IC Design Chapter 1: Introduction RE and NRE costs The Economics of ICs Section 3.1: Basic Semiconductor Theory Section 3.2: Depletion Regions Section 3.3: MOSFET structure Section 3.3: MOSFET Threshold Voltages M Sep 04 *** LABOR DAY NO CLASSES *** W Sep 06 M Sep 11 W Sep 13 M Sep 18 W Sep 20 M Sep 25 Section 3.4: MOSFET I-V Characteristics Resistive Region Section 3.4: MOSFET I-V Characteristics Saturation and Channel Length Modulation Section 3.5: Short Channel Effects Section 3.5: Short Channel Effects Chapter 2: Manufacturing Process Chapter 5: MOS Inverters Static Characteristics W Sep 27 Exam #1 (Chapters 1, 2, and 3) M Oct 02 W Oct 04 Chapter 5: MOS Inverters Static Characteristics

M Oct 09 W Oct 12 M Oct 16 W Oct 18 M Oct 23 W Oct 25 M Oct 30 Exam #2 (Chapters 5 and 6) W Nov 01 M Nov 06 W Nov 08 M Nov 13 W Nov 15 Chapter 8: Sequential MOS Logic Circuits Chapter 8: Sequential MOS Logic Circuits M Nov 20 *** THANKSGIVING BREAK *** W Nov 22 *** THANKSGIVING BREAK *** M Nov 27 W Nov 29 M Dec 04 W Dec 06 Chapter 9: Dynamic Logic Circuits Chapter 9: Dynamic Logic Circuits Project Presentations Project Presentations

Class Attendance Policy: Based on University Class Attendance Policy 1I9: It is the responsibility of students to ascertain the policies of instructors with regard to absence from class, and to make arrangements satisfactory to instructors with regard to missed course work. Failure to attend the first session of a course may result in the student s place in class being assigned to another student. Class Policies: If you have a documented disability that requires academic accommodations, please go to Disability Support Services for coordination of your academic accommodations. DSS is located in the Student Success Center, Room 1270; you may contact them to make an appointment by calling (618) 650-3726 or sending an email to disabilitysupport@siue.edu. Please visit the DSS website located online at www.siue.edu/dss for more information. Students are expected to be familiar with and follow the Student Academic Code. It is included in the SIUE Policies and Procedures under Section 3C2.2. Graduate students enrolled in the course will have an increased workload compared to undergraduates. Graduate and undergraduates will be assigned different final projects and may be asked to do an additional problem on the exams.

Laboratory Exercises M Aug 21 ***** N0 LABS (Determine Lab Times) ***** M Aug 28 ***** Setup Accounts and Introduction to LINUX ***** M Sep 04 M Sep 11 M Sep 18 M Sep 25 M Oct 02 M Oct 09 M Oct 16 M Oct 23 M Oct 30 M Nov 06 M Nov 13 Schematic Capture, Symbol Creation and Simulation Schematic Capture, Symbol Creation and Simulation Schematic Capture, Symbol Creation and Simulation Layout, DRC, and LVS using Virtuoso Layout, DRC, and LVS using Virtuoso Layout, DRC, and LVS using Virtuoso Post-Layout Simulation Using Virtuoso Using NClaunch for HDL creation and Simulation Using RTL Compiler for Synthesis Using Silicon Encounter for Place and Route M Nov 20 *** THANKSGIVING BREAK *** M Nov 27 M Dec 04

MOSIS PARAMETRIC TEST RESULTS RUN: T2AE TECHNOLOGY: SCN025 VENDOR: TSMC FEATURE SIZE: 0.25 microns INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached. COMMENTS: TSMC 0251P5M TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 0.36/0.24 Vth 0.51-0.44 volts SHORT 20.0/0.24 Idss 580-280 ua/um Vth 0.55-0.51 volts Vpt 7.5-7.2 volts WIDE 20.0/0.24 Ids0 4.8-4.5 pa/um LARGE 50/50 Vth 0.45-0.56 volts Vjbkd 4.8-5.0 volts Ijlk <50.0 <50.0 pa Gamma 0.44 0.61 V^0.5 K' (Uo*Cox/2) 115.8-24.6 ua/v^2 Low-field Mobility 382.30 81.21 cm^2/v*s COMMENTS: Poly bias varies with design technology. To account for mask and etch bias use the appropriate value for the parameters XL and XW in your SPICE model card. Design Technology XL XW ----------------- ------- ------ SCN5M_DEEP (lambda=0.12) 0.03-0.04 thick oxide, NMOS 0.02-0.04 thick oxide, PMOS -0.03-0.04 TSMC25 0.03 0.00 thick oxide, NMOS 0.03 0.00 thick oxide, PMOS 0.03 0.00 SCN5M_SUBM (lambda=0.15) -0.03 0.00 thick oxide, NMOS 0.02 0.00 thick oxide, PMOS -0.03 0.00 FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >6.6 <-6.6 volts

PROCESS PARAMETERS N+ACTV P+ACTV POLY PLY+BLK MTL1 MTL2 N+BLK UNITS Sheet Resistance 4.4 3.5 3.9 176.9 0.08 0.07 59.4 ohms/sq Contact Resistance 5.8 5.0 4.9 2.66 ohms Gate Oxide Thickness 57 angstrom PROCESS PARAMETERS MTL3 MTL4 MTL5 N_WELL UNITS Sheet Resistance 0.07 0.07 0.03 1133 ohms/sq Contact Resistance 5.40 8.03 8.05 ohms COMMENTS: BLK is silicide block. CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY M1 M2 M3 M4 M5 N_WELL UNITS Area (substrate) 1699 1899 102 31 19 11 12 9 62 af/um^2 Area (N+active) 6079 50 21 14 11 10 af/um^2 Area (P+active) 5802 af/um^2 Area (poly) 61 18 11 8 6 af/um^2 Area (metal1) 40 16 10 7 af/um^2 Area (metal2) 44 16 10 af/um^2 Area (metal3) 43 16 af/um^2 Area (metal4) 42 af/um^2 Area (no well) 484 af/um^2 Fringe (substrate) 319 337 76 61 42 28 14 af/um Fringe (poly) 67 41 31 25 22 af/um Fringe (metal1) 59 38 25 af/um Fringe (metal2) 58 38 30 af/um Fringe (metal3) 56 39 af/um Fringe (metal4) 60 af/um Overlap (N+active) 599 af/um Overlap (P+active) 674 af/um CIRCUIT PARAMETERS UNITS Inverters K Vinv 1.0 1.02 volts Vinv 1.5 1.11 volts Vol (100 ua) 2.0 0.13 volts Voh (100 ua) 2.0 2.25 volts Vinv 2.0 1.17 volts Gain 2.0-16.76 Ring Oscillator Freq. DIV1024 (31-stg,2.5V) 272.85 MHz D1024_THK (31-stg,3.3V) 211.03 MHz Ring Oscillator Power DIV1024 (31-stg,2.5V) 0.06 uw/mhz/gate D1024_THK (31-stg,3.3V) 0.09 uw/mhz/gate COMMENTS: DEEP_SUBMICRON

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