Interleaved PFC technology bring up low ripple and high efficiency

Interleaved PFC technology bring up low ripple and high efficiency Tony Huang 黄福恩 Texas Instrument Sept 12,2007 1

Presentation Outline Introduction to Interleaved transition mode PFC Comparison to single-channel CCM PFC Comparison to so-called master/slave architecture Interleave technology benefit us. Ripple cancellation to drive lower system cost Improved efficiency via enhanced phase management to drive higher system performance Continuous Transition Mode operation minimizes switching losses associated with MOSFET junction capacitors (result of DCM operation) TI Interleave solution: UCC28060 Faster transient response via slew rate comparator Fail Safe OVP pin to provide additional system safety Implementation of current limiting drives lower system costs, improved reliability and higher efficiency Additional Backup Material 2

Interleaved transition mode PFC: High Performance at Low System Cost 3

Interleaved PFC Concept reduced input current ripple DM filter can be reduced Reduced output current ripple Bulk capacitor size can be reduced Distributed magnetics Improved thermal management phase management is possible Improved partial load efficiency Interleaved PFC becomes an attractive solution for power supply industry Debate turning to implementation method 4

No diode reverse recovery Less switching loss Less EMI Noise 25% Size reduction in inductor size due to transition mode operation 26.5% Size reduction in output capacitor due to ripple current cancellation Similar EMI filter size because of interleaving Phase management improves partial load efficiency (typically 5%) Comparing Performance with CCM PFC Better thermal Management and improved Reliability due to two phases with lower current operation 5

Methods of Interleaving TM PFC Master-slave method Natural Interleaving Simple control method if done discretely Master channel operates at transition mode Slave channel operates at DCM Non-optimal phase shift Complex control if done discretely (simplified with use of TI s UCC28060!) Both channel operate at transition mode (minimizes switching losses!) Optimized phase shift (minimizes ripple current!) 6

Input Ripple Cancellation Normalized Normalized Input Ripple Ripple Current Current Comparing with Master Slave solution, Natural interleaving can further reduce ripple current by 50% 7

Input Ripple Cancellation Master-slave Natural interleaving 100V input, 600W output Simulation results verifies better performance of Natural interleaving solution 8

Other Considerations Comparing with Natural Interleaving Solution Smaller inductor is required for slave channel, two different inductors are required Higher Inventory costs and possible manufacturing risk two different inductors make the slave channel always operate at DCM mode. higher switching loss To prevent slave channel falling into CCM operation, current sharing is worse 9

Introducing TI s UCC28060: The Industry s Only Natural Interleaving Solution 10

UCC28060 Features & Benefits Natural Interleaving from TI featuring: Flexible Phase Management to facilitate 80+ and Energy Star designs FailSafeOVP with dual paths which prevent any voltage loop failure from causing an output over voltage condition SensorlessCurrent Shaping to simplify board layout and improve efficiency In-rush Safe Current Limiting to prevent MOSFET conduction during in-rush and eliminate reverse recovery events in output rectifiers. 11

Natural Interleaving: What is it? Phase-I current Phase-II current Phase-I gate Phase-II gate Phase error 50% duty 12

Natural Interleaving: What benefits does it deliver? q System Features Stable operation over wide dynamic range Matched current sharing with matched inductors Averages two-channel natural frequencies Realize 180-degree phase shift Transition mode operation for both channels q End Benefits Lower system cost thanks to ripple cancellation Improved system efficiency Minimized switching losses 13

Current Ripple Cancellation Total Phase A 2A/div Phase B 2mS/div 180 phase error and transition mode operation can be realized for whole line cycle 14

Ripple cancellation effects 50% Duty Cycle Total Phase A Phase B 180 phase error and transition mode operation can be realized for whole line cycle 15

Ripple cancellation effects Lower Part of Line Voltage Total Phase A Phase B 180 phase error and transition mode operation can be realized for whole line cycle 16

Ripple cancellation effects Zero Crossing Total Phase A Phase B 180 phase error and transition mode operation can be realized for whole line cycle 17

Ripple cancellation effects Peak of the Line Total Phase A Phase B 180 phase error and transition mode operation can be realized for whole line cycle 18

Housekeeping and Protection Features Output voltage sensing Improved transient response Output over voltage protection with fail-safe pin Open loop protection Communication with downstream DC/DC converter Input voltage sensing Brown out protection Input range detect Over current protection Enhanced phase management 19

UCC28060 Error Amplifier Transconductance amplifier, VSENSE pin proportional to output voltage Simplifies output protection functions Open Loop Over voltage 20

Improved Transient Response OV stop 25µA ICOMP 5.75V6V6.25V -25µA -125µA -175µA Transient Operation Normal Operation VSENSE Nonlinear error amplifier, improves transient response Slew rate error amplifier is activated when output has dip during load step up or line drop out Maximum voltage limited by OV stop 21

Load transient waveform Vo 100V/div COMP 1V/dib Total current 4A/div Phase A current 4A/div Phase B current 4A/div Due to fast response error amplifier, transient response can be finished in 120mS Phase error can be kept even during transient 22

Load Step Down Transient Vo 100V/div COMP 1V/dib Total current 4A/div Phase A current 4A/div Phase B current 4A/div Maximum output voltage is regulated by OV stop 23

Communication with Downstream DC/DC Converter Vout 3Meg HVSEN 30.1k 8 4.87V 4.67V + Safety Fault PWMCNTL 9 33µA 2.5V + Phase OK Dedicated PWMCNTL signal for turning on and off downstream DC/DC converter Programmable on and off thresholds 24

Fail-safe OVP Vout 3Meg HVSEN 30.1k 8 4.87V 4.67V + Safety Fault PWMCNTL 9 + 2.5V Phase OK 33µA Safety is a critical concern for commercial products Fail-safe OVP enhance UCC28060 safety feature 25

Over Current Protection for Single PFC Converter Simply sense the inductor current and turn off MOSFET when over current occurs under In rush current Saturated inductor 26

Over Current Protection for Interleaved PFC Circuit Single Sensing Resistor Sensing total inductor current Sensing in rush current Sensing two-phase total current Keep MOSFETs off during inrush conditions and brown out recovery Dual Sensing Resistors Sensing each phase MOSFET current Not sensing in rush current Not sensing inductor current Turning on MOSFETs to detect in rush current MOSFET and diode subject to failure because of CCM inductor current 27

UCC28060 Current Sensing Solution Located at inductor current return path Sensing total inductor current Low threshold, 0.2V, less sensing loss Over current protection is released when current returns to zero, preventing CCM inductor current 28

Startup Waveform Total current (4A/div) COMP 5V/div Phase A, B current 4A/div 20mS/div During start up, inductor current is limited by current limiting 29

Start up waveform Total current 4A/div COMP pin 5V/div Phase currents 4A/div At in rush, turning on MOSFET is prohibited because of single resistor current sensing technique 30

Phase Management Improves Light Load Efficiency Efficiency 110V input 220V input Single-phase operation at light load conditions improves system efficiency Phase management strategy is to optimize the system efficiency at different line and load conditions With phase management 31

Phase Management Options Connect PHB pin with COMP pin, phase management is automaticallyenabled PHB can be driven by external logic signal to allow customized phasemanagement 32

Summary TI s recommended Interleaved PFC implementation achieves Natural Interleaving Dual-phase true transition mode operation Natural interleaving delivers best input and output current ripple cancellation for maximum EMI filter reduction and improved system reliability The UCC28060 provides complete range of protection functions, including fail safe OVP pin The UCC28060 current sensing method protects MOSFET during brown-out recovery with minimal sensing loss The UCC28060 features an enhanced, and flexible, phase management for optimal efficiency HIGH SYSTEM PERFORMANCE WITH LOW COST 33

Additional Backup Material 34

Inductors for Master-slave Interleaving Lm Ls More of the time, two inductors wouldn t be identical because of the tolerance L S > L m Slave channel operates in CCM To prevent CCM operation of slave channel Smaller inductor need to be used in slave channel Smaller current reference need to be used in slave channel Slave channel operates in DCM 35

Issues of DCM Operation Transition mode DCM mode With proper delay, switching loss can be minimized by valley switching Large switching loss caused by energy stored in MOSFET junction capacitor 36

Current Sharing on Master Slave Method ( ) L m L = 1 e S 1 I m I ref 2 = I = I ( 1 e) S 1 2 ref Current sharing is proportional to inductor value To prevent CCM operation, inductor value is required to be different Master slave method has worst current sharing property comparing with Natural interleaving 37

Phase Management Optimization 220V input efficiency Two-phase One-phase 1 0.98 0.96 0.94 0.92 0.9 0.88 0.86 0.84 0.82 0.8 110V input efficiency Two-phase One-phase 0 100 200 300 400 500 600 PHB thresholds (H-L / L-H) VACrms Comments COMP voltage at full power (V) PHB thld voltage (V) % Full Power Watts (600W design) H-L L-H H-L L-H H-L L-H 110 LL nom 3.0 0.8 1.0 27% 33% 161 201 220 HL nom 2.2 1.1 1.3 49% 58% 295 348 Phase management threshold is designed to optimize both high line and low line efficiency 38

Output Capacitor Ripple Current Comparison Normalized Output Capacitor Ripple Current Master-slave Natural Interleaving By using Natural interleaving control, less ripple current can be achieved on output capacitor at high input line Because two solutions have same ripple current at 85V input, same output capacitor should be used Because of less ripple current, higher reliability can be expected for Natural interleaving solution 39

Efficiency Measurement efficiency Without phase management High efficiency can be realized by using interleaved transitionmode PFC 40

Efficiency at 220V with Phase Management 0.99 0.98 0.97 0.96 0.95 0.94 0.93 0.92 0.91 0.9 0.89 no phase management With phase management 0 100 200 300 400 500 600 700 Output Power Because of phase management, light load efficiency is dramatically improved 41

Power Factor Measurement Power factor Without phase management High power factor can be achieved 42

High efficiency power converter Active Clamping Design consideration 43

Presentation Content High efficiency with wide loading range The general requirement for low voltage and high loading current in Mid Power market : PC ATX 85+; LCDTV ACDC; Telecom Power module etc Review of Active Clamp and Reset Technique in Single-Ended Forward Converters Low cost solution to save Energy in the power stage and rectifier. Design consideration: Main switch ZVS / VVS Common Problems in Self-driven Sync Rectifier Control-driven and customized driver solution. Gate Drive Signals Solution to the problem of power-off oscillation Comparison ACFC and HB in telecom applications TI Active Clamping Solution: Schematic and test results in ATX 85+ Solution. Integrated solution for Telecom 48V powered DCDC. 44

High efficiency requirement Wide loading ATX 500W Specification:(Efficiency>85%@Loading>20%) OUTPUT LOAD ATX12V V2.2 SPEC 20% 50% 100% Peak +5Vdc 2.16A 5.4A 10.8A 20A +12V1dc 3A 7.5A 15A 30A +12V2dc 3A 7.5A 15A 30A +3.3Vdc 4A 10A 20A 30A +5Vsb 0.6A 1.5A 3A 3A -12Vdc 0.08A 0.2A TOTAL Total power of +5V and +3.3V shall be less than 120W 500W Total power of +12V1 and +12V2 shall be less than 360VA Max. power shall be less than 500W Power Supply Design Guide for Desktop Platform Form Factors Revision 1.0 -[1 MB] This Power Supply Design Guide for Desktop Form Factors combinesdesign guidelines for the ATX12V, CFX12V, LFX12V, TFX12V and SFX12V power supply form factors into one comprehensive power supply design guide. 0.4A 1A 45

Low voltage and high current loading Telecocmand DatacomPower: Input 36~72VDC; Output: 3.3V/30A 46

Review of Active Clamp Reset Technique Low cost solution to increase the efficiency Typical configurations (a) Low side clamp (b) high side clamp -Detailed comparison can be found in TI Application Note ( SLUA322) Active Clamp Transformer Reset: High Side or Low Side? -Main differences: (a) Gate driving scheme (b) Clamp and Reset voltage ratings (c) MOSFET type for clamping 47

Review of Active Clamp Reset Technique Comparison of High-and Low-Side Clamp 48

Review of Active Clamp Reset Technique -Voltage Clamp -Transformer reset 49

Design Procedures and Concerns Power stage design Program IC Switching frequency, magnetizing inductance, two resonant frequencies, and deadtime Switching losses and ZVS/VVS Capacitance at Vref and VDD should be minimum ratio 1:10 (e.g. if Vref cap is.1uf then VDD cap minimum 1.0uF) Observing Vref maximum load capability, less than 5mA. If tie a resistor between FB and Vref, that resistor typical value is about 2k ohm. Duty cycle (D) and turns ratio (N) to balance MOSFET voltage ratings -N D more stress on main FET (primary) -N D more stress on catch FET (secondary) (a) forward FET Vds= (Vin/N) x D/(1-D) + Vo; (b) catch FET Vds= Vin/N; (c) primary main FET Vds= Vin x 1/(1-D); (d) clamp FET Vds= Vin x 1/(1-D) -Vin = Vinx D/(1-D) 50

How to achieve primary main switch ZVS / VVS If the secondary side leakage is small the magnetizing energy necessary to turn D1 on will be diverted through D3 (Q3) during the reverse recovery of D4 (or Q4 reverse conduction) After the reverse recovery of D4, the magnetizing energy will continue discharging through the loop shown in blue Since there is no energy to turn D1 ON, ZVS of Q1 does not take place. 51

Principle of ZVS/VVS turning on Vdsreversed and clamped by the body diode. 52

Fundamentals of LC Resonance LC resonance as its nature can recycle the energy back to the source. MOSFET turn-on at reduced voltages will make less power losses. Efficiency is then improved. 53

How to realize achieves ZVS / VVS Two resonance present: Magnetizing inductance and clamp capacitor Magnetizing inductance and equivalent Cds ω CL = M 1 L C CL ω R = M 1 L C DS L C M DS N 2 ( VO + VO, misc L M f sw ) cos( L M 1 C CL t off ) I O N V in + V CL 54

Review of Active Clamp Reset Technique Vdsreversed, body diode clamped ω CL = L C M 1 CL ω R = L C M 1 DS ω CL = M 1 L C CL -Voltage Clamp -Transformer reset 55

How to get ZVS? Magnetizing current direction reversed before clamp FET turns off Magnetic field energy (current) sufficient: - lower the magnetizing inductance Primary side: a higher primary leakage or an external saturable inductor (MagAmp) Secondary side: an external saturable inductor (MagAmp) to block magnetizing current discharging from the secondary loop for a short time. 56

Switching Power Loss due to CdsEnergy Discharged at Turn-on with respect to the Vds Comparison of Efficiency Drops Vds The efficiency drops when turn on at different Vdsfrom a 300W converter at 20% load level: Turn on at Vds= 350V, -2.64% Efficiency drop 0.00% -0.50% -1.00% -1.50% -2.00% -2.50% -3.00% -3.50% 0 50 100 150 200 250 300 350 400 450 0.00% -0.12% -0.71% -0.37% -1.11% -1.57% -2.08% -2.64% -3.23% Turn on at Vds= 150V, -0.71% -4.00% -4.50% MOSFET Vds (V) at turn-on -3.87% Efficiency Drops In lower voltage applications, efficiency improvement may not be significant. Efficiency drop vsvdsvariation. fsw = 200kHz and Cds= 500pF @ Vds= 25V. 57

ZVS / VVS Observation Using UCC2894 ZVS/VVS can be achieved by properly and adequately lowering the magnetizing inductance Lm to improve the efficiency in off-line applications. Vin = 390V, Vo = 12V, Lm = 0.65 mh ZVS achieved at Io = 1.5A VVS achieved at Io = 26A Vgs Vds 58

ZVS observations on ACFC (UCC2891/7 EVM) Lm = 95 µh Lm = 25 µh Vin = 42V, Vo = 3.3V, Io = 0A Vin = 40V, Vo = 3.3V, Io = 0A 59

ZVS observations on Active Clamp Forward Converter Lm = 95 µh Lm = 25 µh Vin = 42V, Vo = 3.3V, Io = 15A Vin = 40V, Vo = 3.3V, Io = 10A 60

Issues from self-driven SR in ACFC Power shutdown oscillation * cause: self-driven SR feedback the capacitor stored energy to the primary * solutions: -soft stop to control secondary capacitor discharge most effective way -using control-driven SR - rating the avalanche energy high enough ( ), or the voltage rating high enough Oscillation from fast load step down change1 2 2C O V O * cause: -control lost after duty cycle reached zero from the load step down change -self-driven SR feedback the capacitor stored energy to the primary * solutions: -slower loop response design; -higher Dmaxdesign Reversing current at light load and no load * cause: self-driven SR catch FET conducting * Solutions: -Using control-driven SR -Turning off SR 61

Power Shutdown (LineUV) Oscillation Observations 62

Mechanism of the Oscillation during Power Shutdown Oscillation from secondary energy feedback to the primary from self-driven SR during power shutdown T1 LineUV(power shutdown) T1 a(+) and c(+) Q4 on and reverse Lo current T1 b(+) and d(+) Q3 on (energy transfer to primary) Magnetizing current reduction T1 a(+) and c(+) Loop With soft stop, both Q1 and Q2 are controlled during power down. The secondary stored energy will be discharged in control manner. The oscillation then will be eliminated, refer to the 2nd slide. 63

Power Shutdown (LineUV) Oscillation Oscillation appears during power shutdown without soft stop Oscillation does not appear during power shutdown with soft stop -using SS/SD pin and a comparator -feature to be added 64

Load Transient Ringing Load step down change (30A to 3A) at 72Vin, 3.3Vo: High voltage swing across Q1 drain and source 65

Load Transient Ringing Mechanism -control lost after duty cycle reached from load step down change -secondary self-driven SR oscillation Fast loop compensation, or High maximum duty cycle setup zero With slower loop compensation or reduced maximum duty cycle - Vdsswing peak reduced - Vo load transient response becomes slower 66

TPS28225 used for the control drive 67

Active Clamp single-ended forward converter in telecom applications EVM Specs: Vin = 36V to 75V, Vo = 3.3V, Io = 30A, Po = 100W UCC2891 EVM UCC2897 EVM 68

Low voltage and high current loading Telecocmand DatacomPower: Input 36~72VDC; Output: 3.3V/30A 69

UCC2894 EVM for 85+ ATX Application Input voltage: 390Vdc Rated Power: 320W Output voltage: 12Vdc Output current: 26A 70

UCC2894 EVM Efficiency Test Results and Comparison Efficiency results from different design of magnetizing inductance: Lm = 3.08mH, valley voltage about 350V Lm = 0.65mH, valley voltage about 180V test conditions: -fsw= 160kHz -Vin = 390V -Vo = 12V -Full load = 320W E ffi c i e n c y 95% 90% 85% 80% 75% 70% Efficiency Comparison 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Load Level Load Level = 1 representing full load 320W Lm = 3.08 mh Lm = 0.65 mh 71

THANK YOU! Contact Info: Tony Huang +86-21-23073602 tony-huang@ti.com 72