Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000, pp. 822 827 Design of a Temperature-Compensated Crystal Oscillator Using the New Digital Trimming Method Minkyu Je, Kyungmi Lee, Joonho Gil, Hoi-Jun Yoo and Hyungcheol Shin Divison of Electrical Engineering, Department of Electrical Engineering and Computer Sciences, Korea Advanced Institute of Science and Technology, Taejon 305-701 (Received 12 April 2000) Recently, the demand for stable temperature-compensated crystal oscillators (TCXO) has been increasing more and more, and digital TCXOs (DTCXO) have been studied extensively because of their higher frequency accuracy and one-chip implementation possibility. A DTCXO using a capacitor array which is directly controlled by a digital code from the memory has been proposed for developing a VLSI TCXO, and the way to organize the capacitor array has been studied. In this work, a new capacitor array scheme, called TACA (temperature adaptive capacitor array), is proposed. It guarantees monotonicity and saves the silicon area at the same time. We also have developed a TCXO that can be used over a wide range of frequencies. The oscillator and the capacitor array were fabricated with a 0.5-µm CMOS process and their operation was characterized at 10 and 20 MHz. Complete digital trimming of the DTCXO was achieved with a 0.2-ppm trimming accuracy. I. INTRODUCTION Crystal oscillators play an important role in modern electronic systems. Since a precise oscillation frequency, low phase noise, and low power are required for all paging applications, a crystal oscillator is the best candidate. The frequency stability of a crystal is limited by its temperature-frequency characteristics. The untrimmed accuracy of crystal resonators is about ±30 ppm, mostly due to temperature variations and aging. If a high accuracy of the oscillation frequency is to be obtained, the temperature compensation is indispensable. The frequency shift due to the temperature variation can be compensated for by controlling the value of the load capacitance connected to the crystal. The frequency stability of analog temperature-compensated crystal oscillators (TCXO) has been limited to a range of a few ppms. Recently, more stable TCXOs have come to be required, and digital TCXOs (DTCXO) have been studied extensively because of their higher frequency accuracy and one-chip implementation possibility. Since implementing varactor diodes and digital-to-analog converters (DAC) used in conventional digital compensation systems is very difficult for VLSI TCXOs, DTCXOs using capacitor arrays which are directly controlled by a digital code from the memory, as shown in Fig. 1, have been proposed [1]. How to organize the capacitor array for DTCXOs was E-mail: felix@inca.kaist.ac.kr, Fax: +82-42-869-8590, Tel: +82-42-869-8059 studied in Ref. 2, in which two different ways were proposed. One was to organize it as a binary weighted array, and the other as a parallel array of unit capacitors. The binary weighted array design is the most straightforward way and keeps the overhead of switches, decoding logic circuits, and interconnections very small. However, because of the monotonicity restriction, there is a lower limit to the size of the least significant bit (LSB) Fig. 1. Block diagrams of the conventional DTCXO and the DTCXO using a capacitor array. The digital TCXO can achieve a higher accuracy of the oscillation frequency by using an on-chip memory that contains compensation data for each temperature. Since implementing good varactor diodes for VLSI TCXO is very difficult, the digital TCXO using a capacitor array, as shown in this figure, was proposed. -822-
Design of a Temperature-Compensated Crystal Oscillator Using the Minkyu Je et al. -823- Fig. 2. Basic structure of a Pierce oscillator. The transconductance of M 1 is converted to a frequency-dependent negative resistance by the functional capacitances C A and C B. If the transconductance of M 1 is sufficiently large, this negative resistance compensates for the loss of the crystal and sustains the oscillation. The oscillation frequency can be adjusted by controlling the value of the load capacitance, which is a series combination of C A and C B. capacitor to ensure sufficient matching accuracy. That causes the total capacitance of the array, and thus the power consumption, to be large. On the other hand, a parallel array of unit capacitors guarantees monotonicity, so the total capacitance and the power consumption can be minimized. However, the silicon area overhead of switches, decoding logic circuits, and wiring interconnections is significant. To solve the above-mentioned problems, we propose a new capacitor array scheme, which we call a temperature adaptive capacitor array (TACA), that guarantees monotonicity and saves the silicon area at the same time. In Section II, we describe the oscillator design related to digital trimming for a high accuracy of the oscillation frequency and frequency selection in communication systems. The TACA scheme is explained in detail in Section III. The oscillator and the capacitor array were fabricated with 0.5-µm CMOS technology, and the experimental results are presented in the Section IV. A complete digital trimming of the TCXO was achieved with a 0.2-ppm trimming accuracy. II. DESIGN CONSIDERATION FOR CRYSTAL OSCILLATOR Low-noise and low-power oscillators can be implemented by using essentially a single transconductance device, such as a MOS transistor [3,4]. Figure 2 shows the basic structure of a Pierce oscillator. The transconductance of M 1 is converted to a frequency-dependent negative resistance by the functional capacitances C A and C B. From the small-signal analysis, the effective negative resistance is shown to be R = g m ω 2 oc A C B. (1) Fig. 3. Frequency deviation as a function of the load capacitance for several frequencies. Since the fractional frequency change due to C L becomes larger as the center frequency increases, the load capacitance must be increased as the frequency increases in order to obtain the same trimming resolution over the required frequency range. This equation can be used to estimate the critical transconductance (g mc ) to compensate for the loss of the crystal and to sustain oscillation as follows: g mc = R m ω 2 oc A C B. (2) The oscillation frequency of the circuit, f, is given by 1 f = (3) C 2π L m(c 0+C L ) m C m+c 0+C L where R m, L m, C m, C 0 and C L are the resonator s motional resistance, inductance, capacitance, shunt capacitance, and load capacitance, respectively. The load capacitance C L is a series combination of C A and C B. C A and C B should be equal for the best trade-off between the transconductance (related to current) and frequency stability [5]. This equation means that the oscillation frequency can be tuned by changing C L ; the tuning method is mentioned in the next section. In our application, the oscillator is designed to operate over the range from 10 MHz to 25 MHz, depending on the crystal parameters. About a 0.7-V peak-to-peak amplitude and the same trimming resolution is required over the entire range of frequencies. To cover the frequency range from 10 MHz to 25 MHz, we must properly control the critical transconductance required to cause the oscillation. Figure 3 shows the frequency deviation as a function of the load capacitance C L for several frequencies. Since the fractional frequency change due to C L becomes larger as the center frequency increases, the load capacitance should be increased as the frequency increases to obtain the same trimming resolution over the required frequency range. To do this, we added a frequency selection capacitor array block (FCB). The capacitance of the FCB is determined by the oscillation frequency and takes the largest portion of C L. In our design, the total capacitance of FCB is 8 pf, and the unit capacitance is 0.5 pf.
-824- Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000 Fig. 4. Critical transconductance as a function of the frequency. The increase in both the load capacitance and the frequency increases the critical transconductance. According to Eq. (2), the increase in both the load capacitance and the frequency increases the critical transconductance as shown in Fig. 4. To deal with the increase in the critical transconductance with frequency, we controlled the bias current, I bias, by using a current mirror connected to switches. The control of the bias current makes it possible to obtain the proper transconductance required to oscillate and sustain the proper peak-to-peak amplitude over the whole frequency range. III. NEW TRIMMING METHOD USING TACA Figure 5 shows typical temperature-frequency characteristics of a crystal resonator, from which the amount of frequency deviation can be decided from the present temperature. In this work, we propose to divide the whole trimming range into two regions: region I of negative frequency deviation and region II of positive frequency deviation. A plot of Eq. (3) gives the curves in Fig. 6. Curve Fig. 5. Temperature-frequency characteristics of a typical crystal resonator from which the amount of the frequency deviation can be decided from the present temperature. In this work, we propose to divide the whole trimming range into two regions: region I of negative frequency deviation and region II of positive frequency deviation. Fig. 6. Frequency deviation as a function of the total capacitance of the capacitor array C L for three different cases. Curve B is for the nominal condition without a frequency deviation. Curve A and curve C correspond to the cases of maximum positive frequency deviation and maximum negative frequency deviation, respectively. B is for the nominal condition without a frequency deviation. Curve A and curve C correspond to the cases of maximum positive frequency deviation and maximum negative frequency deviation, respectively. In the parallel capacitor array scheme, the whole array is composed of identical capacitors, and the size of the unit capacitance is determined by the largest tuning slope at point X of curve C in Fig. 6 to get the desired trimming resolution over the whole trimming range. However, since the tuning slope for positive frequency deviation is smaller than that for negative frequency deviation, the unit capacitance used for tuning in region II can be larger than that used for tuning in region I. Therefore, in this work, we propose to divide the whole trimming range into two regions: region I of negative frequency deviation and region II of positive frequency deviation. In our new TACA scheme, the capacitor array consists of two array blocks. Block 1 consists of minimum-size unit capacitors used for tuning in region I, and the size of the capacitors is the same as those used in the parallel array scheme. However, block 2 consists of larger unit capacitors, which are used for tuning in region II. Therefore, a less number of unit capacitors is used for tuning in region II than in the parallel array scheme, so silicon area is saved. If the trimming range of ±35 ppm is to be covered, the total capacitance of the capacitor array C L should be varied from 15.0 pf to 19.7 pf, as indicated in Fig. 3. The largest tuning slope at point X is 2.066 10 13 ppm/f. For the simple parallel array structure, a unit capacitance of 19.4 ff is used for a 0.2-ppm accuracy. The same capacitance step is used in the array block 1 in the TACA structure. However, the tuning slope at point Y, which is 1.521 10 13 ppm/f, determines the unit capacitance in block 2 (26.3 ff). In the simple parallel array implementation, 485 unit capacitors (206 for region I and 279 for region II) are needed. In the TACA scheme, only 412 unit capacitors (206 unit capacitors for each block) are needed. As a result, the number of cells is
Design of a Temperature-Compensated Crystal Oscillator Using the Minkyu Je et al. -825- Fig. 9. Photograph of the test board designed for chip characterization. DIP switches were used to set the digital input codes of each capacitor array block. Fig. 7. Pierce-type oscillator connected with capacitor banks: (a) simplified schematic diagram and (b) simulation result. reduced by 63, which is about 15 %, and fewer switch transistors, smaller decoding logic circuits, and smaller wiring areas are needed. IV. CIRCUIT IMPLEMENTATION AND EXPERIMENTAL RESULTS Figure 7(a) shows the schematic diagram of the designed Pierce-type oscillator. A current mirror connected with switches was used to control the transconductance of M 1. The transistor, M Rf, plays a role as a resistance to bias M 1 in the active region, and the value of the Fig. 8. Microphotograph showing the oscillator and capacitor arrays. C A,V and C B,V are the voltage-controlled capacitor array blocks, and C A,F and C B,F are the frequency selection capacitor array blocks. resistance should be large in order to reduce the resistive loading on the crystal [5,6]. The load capacitance, C L, consists of the frequency selection capacitor array block (FCB), the temperature-compensation capacitor array block (TCB), and the voltage-controlled capacitor array block (VCB). The TCB consists of the proposed TACA block 1 and TACA block 2. Aging causes a frequency deviation, but the voltage-controlled capacitor array block (VCB) is designed to compensate for the frequency deviation due to aging or to adjust the oscillation frequency slightly from the outside. The digital data converted from the applied analog voltage determine the capacitance of the VCB. The size of the unit capacitance in the VCB is 13.3 ff in order to obtain a resolution of 0.15 ppm/bit. R sw in Fig. 7(a) is the equivalent resistance of the switch. Also shown in Fig. 7(b) is the waveform simulated with HPADS for the 20-MHz case. The capacitor arrays including the proposed TACA and the designed Pierce-type oscillator were fabricated with a 0.5-µm n-well CMOS process. The temperature sensor, the analog-to-digital converter, and the memory were not fabricated. Figure 8 shows a chip photograph. To minimize the mismatch due to the process variation, we the chip carefully laid out in common centroid structures. The total area of the chip was 1.05 mm 2. To characterize the chip, we used the test board shown in Fig. 9. The fabricated oscillator and the capacitor arrays were connected with a proper crystal. DIP switches were used to set the digital input codes for each capacitor array block. Figure 10 shows the measured waveform of the oscillator output for the 20-MHz case. It was obtained using a digital oscilloscope. A sinusoidal waveform with about a 0.7-V peak-to-peak amplitude was observed. We measured the harmonic and the phase noise characteristics by using a spectrum analyzer, HP8564E. The oscillator
-826- Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000 Fig. 10. Experimental results for the oscillator output waveform. A sinusoidal waveform with about a 0.7-V peakto-peak amplitude is observed. output spectrum in Fig. 11 shows the harmonic characteristics of the oscillator. The difference between the fundamental and the third harmonic components is 11.7 db. The phase noise characteristics of the oscillator are illustrated in Fig. 12, which shows a phase noise value of 104 dbc/hz at a 1-kHz offset. By changing the digital code of the TACAs, we also measured the tuning characteristics to examine the trimming accuracy and the monotonicity of the frequencytuning scheme. The results, as well as the prediction from Eq. (3), are shown in Fig. 13. Figure 13(a) is for the 10-MHz case, and Fig. 13(b) is for the 20MHz case. The measured results match very well with the prediction. For 10 MHz and 20 MHz, about a ±35-ppm tuning range was successfully covered and a resolution of less than 0.2 ppm was obtained for both cases. For comparison with the previous work by Huang and Fig. 11. Oscillator output spectrum showing the harmonic characteristics. The difference between the fundamental and the third harmonic components is 11.7 db. Fig. 12. Phase noise performance vs. offset frequency. A phase noise value of 104 dbc/hz at a 1-kHz offset was obtained. Basedau [2], values of some important parameters are summarized in Table 1. Huang and Basedau fabricated and characterized a Pierce-type oscillator connected with a binary-weighted array and one connected with a simple parallel array [2]. The 1-µm CMOS technology was used in Ref. 2 rather than the 0.5-µm CMOS technol- Fig. 13. Digital trimming characteristics of the proposed TACA connected to the designed crystal oscillator circuit: (a) 10-MHz case and (b) 20-MHz case. A resolution of 0.2 ppm was obtained for both cases.
Design of a Temperature-Compensated Crystal Oscillator Using the Minkyu Je et al. -827- Table 1. Summary of the measurement results compared with the results in Ref. 2. This Work Ref. 2 Binary-weighted Simple parallel Proposed array array array Oscillation frequency 10 25 MHz 78 MHz 78 MHz Active area 1.05 mm 2 0.99 mm 2 1.58 mm 2 Oscillation amplitude 0.7 V pp 0.32 V pp 0.4 V pp Maximum curret 965 µa 1.85 ma 714 µa consumption Trimming accuracy 0.2 ppm 0.29 ppm 0.2 ppm Phase noise 104 dbc/hz 113 dbc/hz 113 dbc/hz @1 khz @300 Hz @300 Hz and temperature-frequency characteristics of a crystal. By using different unit capacitors for positive frequency deviation and for negative frequency deviation, we could reduce the number of unit capacitors, guaranteeing monotonicity and saving the silicon area consumption at the same time. We also added a frequency-selection capability to the crystal oscillator, which operated over a wide range of frequencies. The FCB and the VCB were designed to obtain the same trimming resolution over the whole frequency range and to compensate for the frequency deviation due to aging, respectively. A Pierce-type crystal oscillator connected with the proposed TACA was fabricated using a 0.5-µm CMOS process. Crystal oscillators at 10 MHz and 20 MHz were characterized. The oscillator characteristics and complete digital trimming with a 0.2-ppm trimming accuracy were verified for both cases. The measured phase noise was 104 dbc/hz at a 1-kHz offset. ogy used in this work. However, in Ref. 2, the capacitor array blocks that correspond to the FSB and the VCB in this work were not included. The maximum current consumption means the bias current level required to sustain the proper oscillation amplitude when all the capacitors in the capacitor array blocks have been switched in. Although the different conditions between the two works make it difficult to compare the values in Table 1 directly, we can roughly conclude that the proposed TACA scheme reduces the silicon area compared to the binary-weighted array scheme and the power consumption compared to the simple array scheme. The trimming accuracies in the two works are almost the same, and the phase noise level obtained in this work is worse than that obtained in Ref. 2. V. CONCLUSIONS We proposed a new TACA scheme inspired from the slope variation in the oscillation frequency tuning curve ACKNOWLEDGMENTS This research is supported by the Institute of Information Technology Assessment and by the Tera-level Nanodevices project of the Ministry of Science and Technology. REFERENCES [1] T. Uno and Y. Shimoda, in Proceedings of the 37th Ann. Symp. Freq. Control (1983), p. 434. [2] Q. Huang and P. Basedau, IEEE Trans. VLSI Systems 5, 408 (1997). [3] B. Parzen, Design of Crystal and Other Harmonic Oscillators (Wiley, New York, 1983). [4] M. E. Frerking, Crystal Oscillator Design and Temperature Compensation (Van Nostrand Reinhold, New York, 1978). [5] R. G. Meyer and D. C.-F. Soo, IEEE J. Solid-State Circ. SC-15, 222 (1980). [6] M. A. Unkrich and R. G. Meyer, IEEE J.Solid-State Circ. SC-17, 87 (1982).