HA-533 Data Sheet February 6, 26 FN2924.8 25MHz Video Buffer The HA-533 is a unity gain monolithic IC designed for any application requiring a fast, wideband buffer. Featuring a bandwidth of 25MHz and outstanding differential phase/ gain characteristics, this high performance voltage follower is an excellent choice for video circuit design. Other features, which include a minimum slew rate of /µs and high output drive capability, make the HA-533 applicable for line driver and high speed data conversion circuits. The high performance of this product is a result of the Intersil Dielectric Isolation process. A major feature of this process is that it produces both PNP and NPN high frequency transistors which makes wide bandwidth designs, such as the HA-533, practical. Alternative process methods typically produce a lower AC performance. Ordering Information PART NUMBER Pinouts PART MARKING TEMP. RANGE ( C) HA-533 (PDIP) TOP VIEW PACKAGE PKG. DWG. # HA2-533-2 HA2-533-2-55 to 25 2 Pin Metal Can T2.C HA3-533-5 HA3-533-5 to 75 8 Ld PDIP E8.3 Features Differential Phase Error.................2 Degrees Differential Gain Error.......................3% High Slew Rate......................... /µs Wide Bandwidth (Small Signal).............. 25MHz Wide Power Bandwidth.............. DC to 7.5MHz Fast Rise Time.............................. 3ns High Output Drive.............. ± With Ω Load Wide Power Supply Range............. ±5V to ±6V Replace Costly Hybrids Applications Video Buffer High Frequency Buffer Isolation Buffer High Speed Line Driver Impedance Matching Current Boosters High Speed A/D Input Buffers Related Literature - AN548, Designer s Guide for HA-533 V+ 8 OUT 2 7 3 6 SUB- STRATE IN 4 5 V- HA-533 (METAL CAN) TOP VIEW V+ CASE 2 2 OUT V- 3 9 4 +IN 5 6 7 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or -888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 23, 25, 26. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Absolute Maximum Ratings Voltage Between V+ and V- Pins........................ 4 DC Input Voltage................................. V+ to V- Output Current (Peak) (5ms On/ Second Off)......... ±2mA ESD Rating Human Body Model (Per MIL-STD-883 Method 35.7).... 2 Operating Conditions Temperature Ranges (Note 3) HA-533-2.............................. -55 C to 25 C HA-533-5................................. C to 75 C Thermal Information Thermal Resistance (Typical, Note 2) θ JA ( C/W) θ JC ( C/W) Metal Can Package............... 65 34 PDIP Package................... 2 N/A Maximum Junction Temperature (Note )................. 75 C Maximum Junction Temperature (Plastic Packages)....... 5 C Maximum Storage Temperature Range......... -65 C to 5 C Maximum Lead Temperature (Soldering s)............ 3 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 75 C for the metal can package, and below 5 C for the plastic packages (See Figure 5.). 2. θ JA is measured with the component mounted on an evaluation PC board in free air. 3. The maximum operating temperature may have to be derated depending on the output load condition. See Figure 5 for more information. Electrical Specifications V SUPPLY = ±2V, R S = 5Ω, R L = Ω, C L = pf, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( C) HA-533-2 HA-533-5 MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage 25-5 5-5 5 mv Full - 6 25-6 25 mv Average Offset Voltage Drift Full - 33 - - 33 - µv/ C Bias Current 25-2 35-2 35 µa Full - 3 5-3 5 µa Input Resistance 25-3 - - 3 - MΩ Input Capacitance 25 -.6 - -.6 - pf Input Noise Voltage Hz to MHz 25-2 - - 2 - µv P-P TRANSFER CHARACTERISTICS Voltage Gain R L = Ω 25.93 - -.93 - - V/V R L = kω 25.93.99 -.93.99 - V/V R L = Ω Full.92 - -.92 - - V/V -3dB Bandwidth 25-25 - - 25 - MHz OUTPUT CHARACTERISTICS Output Voltage Swing R L = Ω Full ±8 ± - ±8 ± - V R L = kω, V S = ±5V Full ± ±2 - ± ±2 - V Output Current 25 ±8 ± - ±8 ± - ma Output Resistance 25-8 - - 8 - Ω Full Power Bandwidth V OUT = V RMS, R L = kω 25-46 - - 46 - MHz Full Power Bandwidth (Note 4) 25 5.9 7.5-5.9 7.5 - MHz TRANSIENT RESPONSE Rise Time V OUT = 5mV 25-4.6 - - 4.6 - ns Propagation Delay 25 - - - - ns 2 FN2924.8
Electrical Specifications V SUPPLY = ±2V, R S = 5Ω, R L = Ω, C L = pf, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP. ( C) HA-533-2 HA-533-5 MIN TYP MAX MIN TYP MAX UNITS Overshoot 25-3 - - 3 - % Slew Rate (Note 4) 25. -. - V/ns Settling Time to.% 25-5 - - 5 - ns Differential Phase Error (Note 5) 25 -.2 - -.2 - Degree Differential Gain Error (Note 5) 25 -.3 - -.3 - % POWER SUPPLY CHARACTERISTICS Supply Current 25-2 25-2 25 ma Full - 2 3-2 3 ma Power Supply Rejection Ratio Full 54 - - 54 - - db Harmonic Distortion = V RMS at khz 25 - <. - - <. - % NOTES: 4. V SUPPLY = ±5V, V OUT = ±, R L = kω. 5. Differential gain and phase error are nonlinear signal distortions found in video systems and are defined as follows: Differential gain error is defined as the change in amplitude at the color subcarrier frequency as the picture signal is varied from blanking to white level. Differential phase error is defined as the change in the phase of the color subcarrier as the picture signal is varied from blanking to white level. R L = 3Ω. Test Circuits and Waveforms +5V.µF +2V.µF IN OUT IN OUT R L Ω.µF.µF -5V -2V FIGURE. SLEW RATE AND SETTLING TIME FIGURE 2. TRANSIENT RESPONSE 5mV INPUT 9% OUTPUT V % ERROR BAND SLEW ±mv FROM t RATE = FINAL VALUE V/ t SETTLING TIME INPUT 9% OUTPUT % OVERSHOOT NOTE: Measured on both positive and negative transitions. FIGURE 3. SETTLING TIME AND SLEW RATE FIGURE 4. RISE TIME AND OVERSHOOT 3 FN2924.8
Test Circuits and Waveforms (Continued) V OUT V OUT T A = 25 C, R S = 5Ω, R L = Ω T A = 25 C, R S = 5Ω, R L = kω + RESPONSE + RESPONSE 5mV 5mV V OUT T A = 25 C, R S = 5Ω, R L = Ω PULSE RESPONSE Schematic Diagram V+ R 5 R 4 R 2 R 2 Q 5 Q Q 6 Q Q 6 Q 2 Q R 9 Q 9 Q 7 R R 6 Q 3 R 8 Q 4 Q 8 V OUT R Q 7 Q 3 Q 5 Q 9 Q 2 Q 8 Q 4 R R 3 V- R 3 4 FN2924.8
Application Information Layout Considerations The wide bandwidth of the HA-533 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. IC sockets contribute inter-lead capacitance which limits device bandwidth and should be avoided. Pin 6 can be tied to either supply, grounded, or simply not used. But to optimize device performance and improve isolation, it is recommended that this pin be grounded. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimum device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from.µf to.µf will minimize high frequency variations in supply voltage. Solid tantalum capacitors µf or larger will optimize low frequency performance. It is also recommended that the bypass capacitors be connected close to the HA-533 (preferably directly to the supply pins). Figure 5 is based on: T P JMAX T A DMAX = ------------------------------ θ JA Where: T JMAX = Maximum Junction Temperature of the Device T A = Ambient Temperature MAXIMUM TOTAL POWER DISSIPATION (W) 2.4 2.2 2..8.6.4.2..8.6.4.2 θ JA = Junction to Ambient Thermal Resistance PDIP CAN QUIESCENT P D =.72W AT V S = ±2V, I CC = 3mA 25 45 65 85 5 25 TEMPERATURE ( C) FIGURE 5. MAXIMUM POWER DISSIPATION vs TEMPERATURE Typical Applications (Also see Application Note AN548) R S +2V.µF 2 5.µF -2V R M 5Ω RG -58 5Ω R L VIDEO SIGNAL INPUT V+ HA-2539 R + 6Ω - R 2 5Ω V- 9Ω V+ VIDEO HA-533 OUTPUT 75Ω V- 75Ω Ω FIGURE 6. VIDEO COAXIAL LINE DRIVER 5Ω SYSTEM FIGURE 7. VIDEO GAIN BLOCK 5 FN2924.8
Typical Applications (Also see Application Note AN548) (Continued) V OUT V OUT T A = 25 C, R S = 5Ω, R M = R L = 5Ω T A = 25 C, R S = 5Ω, R M = R L = 5Ω R L V O = ---------------------- = R L + R M -- V 2 IN R L V O = ---------------------- = R L + R M -- V 2 IN POSITIVE PULSE RESPONSE NEGATIVE PULSE RESPONSE Typical Performance Curves 4 OFFSET VOLTAGE (mv) 8 7 6 5 4 3 2 V S = ±2V V S = ±5V V S = ± INPUT BIAS CURRENT (µa) 3 2 V S = ±2V V S = ± V S = ±5V V S = ±5V V S = ±5V -8-4 4 8 2 6 TEMPERATURE ( C) FIGURE 8. INPUT OFFSET VOLTAGE vs TEMPERATURE -55-25 25 75 25 TEMPERATURE ( C) FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE 3 V S = ±5V 3 V S = ±5V, = ± SUPPLY CURRENT (ma) 2 V S = ±2V V S = ± V S = ±5V SLEW RATE (V/µs) 2 FALL (R L = kω) FALL (R L = Ω) RISE (R L = kω) RISE (R L = Ω) -55-25 25 75 25 TEMPERATURE ( C) FIGURE. SUPPLY CURRENT vs TEMPERATURE -55-25 25 75 25 TEMPERATURE ( C) FIGURE. SLEW RATE vs TEMPERATURE 6 FN2924.8
Typical Performance Curves (Continued) SLEW RATE (V/µs) 24 22 2 8 6 4 2 8 6 4 2 V S = ±5V, R L = kω T A = 25 C, = ± RISE FALL SLEW RATE (V/µs) 4 3 2 9 8 7 6 5 4 3 2 RISE FALL V S = ±5V, R L = Ω T A = 25 C, = ± CAPACITAE (pf) 5, CAPACITAE (pf) 5, FIGURE 2. SLEW RATE vs LOAD CAPACITAE FIGURE 3. SLEW RATE vs LOAD CAPACITAE 8 6 V S = ±5V, T A = 25 C R L = kω 9 7 V S = ±5V, T A = 25 C R L = 5Ω OUTPUT INPUT V OS (mv) 4 2-2 -4 R L = kω R L = kω OUTPUT INPUT V OS (mv) 5 3 - -3-5 R L = Ω R L = Ω -6-8 - R L = kω -8-6 -4-2 +2 +4 +6 +8 + INPUT VOLTAGE (V) -7-9 - -8 R L = 5Ω -6-4 -2 +2 +4 +6 +8 + INPUT VOLTAGE (V) FIGURE 4. GAIN ERROR vs INPUT VOLTAGE FIGURE 5. GAIN ERROR vs INPUT VOLTAGE 6 4 V S = ±5V, V O = ± 8 V S = ±5, T A = 25 C OUTPUT INPUT V OS (mv) 2 8 6 4 R L = kω - V OUT (mv) 7 6 5 4 3 2 V OUT = SINKING CURRENT V OUT = - V OUT = + V OUT = SOURCING CURRENT 2-55 -25 25 75 25 TEMPERATURE ( C) 2 3 4 5 6 7 8 9 I OUT (ma) 2 FIGURE 6. GAIN ERROR vs TEMPERATURE FIGURE 7. - V OUT vs I OUT 7 FN2924.8
Typical Performance Curves (Continued) PHASE ANGLE (DEGREES) 8 35 9 45-45 -9-35 Y 22 Y 2 Y Y 2 MAGNITUDE (S) - -2-3 -4 Y Y 2 Y 2, Y 22 Y Y 2 Y 22 Y 2-8 6 7 8 9 FREQUEY (Hz) -5 6 8 7 FREQUEY (Hz) 9 FIGURE 8. Y - PARAMETERS PHASE vs FREQUEY FIGURE 9. Y - PARAMETER MAGNITUDE vs FREQUEY POWER SUPPLY REJECTION RATIO (db) 7 6 5 4 3 2 V S = ±2V, T A = 25 C TOTAL HARMONIC DISTORTION (%)..9.8.7.6.5.4.3.2. V S = ±2V, R L = Ω = V RMS K K K M M FREQUEY (Hz) K K FREQUEY (Hz) K FIGURE 2. POWER SUPPLY REJECTION RATIO vs FREQUEY FIGURE 2. TOTAL HARMONIC DISTORTION vs FREQUEY TOTAL HARMONIC DISTORTION (%)... V S = ±2V R L = ±V Ω = ±2V, R L = Ω f = khz PEAK TO PEAK OUTPUT VOLTAGE (V) 28 24 2 6 2 8 4 T A = 25 C V S = ±5V V S = ±5V V S = ±2V V S = ± 2 3 INPUT VOLTAGE (RMS) FIGURE 22. TOTAL HARMONIC DISTORTION vs INPUT VOLTAGE 2 3 4 5 6 7 8 9 K LOAD RESISTAE (Ω) FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD RESISTAE 8 FN2924.8
Typical Performance Curves (Continued) OUTPUT VOLTAGE (V RMS ) 6. 5.5 V S = ±5V, R L = Ω 5. 4.5 4. 3.5 NO HEAT SINK IN 3. FREE AIR 2.5 2..5..5 K K M M M G FREQUEY (Hz) OUTPUT VOLTAGE (V RMS ) 6. 5.5 V S = ±5V, R L = kω 5. 4.5 NO HEAT SINK 4. IN FREE AIR 3.5 3. 2.5 2..5..5 K K M M M G FREQUEY (Hz) FIGURE 24. OUTPUT SWING vs FREQUEY (NOTE) FIGURE 25. OUTPUT SWING vs FREQUEY (NOTE) NOTE: This curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. If higher distortion is acceptable, then a higher output voltage for a given frequency can be obtained. However, operating the HA-533 with increased distortion (to the right of curve shown), will also be accompanied by an increase in supply current. The resulting increase in chip temperature must be considered and heat sinking will be necessary to prevent thermal runaway. This characteristic is the result of the output transistor operation. If the signal amplitude or signal frequency or both are increased beyond the curve shown, the NPN, PNP output transistors will approach a condition of being simultaneously on. Under this condition, thermal runaway can occur. 9 FN2924.8
Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 2 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-533 IN V+ OUT V- FN2924.8
Metal Can Packages (Can) ØD ØD A F L Øb REFEREE PLANE A A BASE METAL NOTES:. The reference, base, and seating planes are the same for this variation. 2. Measured from maximum diameter of the product. 3. N is the maximum number of terminal positions. 4. Dimensioning and tolerancing per ANSI Y4.5M - 982. 5. Controlling dimension: IH. e SECTION A-A LEAD FINISH Øb2 2 N k e k T2.C 2 LEAD METAL CAN PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.3.5 3.3 3.8 - Øb.6.9.4.48 - Øb2.6.2.4.53 - ØD.585.65 4.86 5.62 - ØD.54.56 3.72 4.22 - e.4 BSC.6 BSC - e. BSC 2.54 BSC - F.2.4.5.2 - k.27.34.69.86 - k.27.45.69.4 2 L.5.56 2.7 4.22 - N 2 2 3 Rev. 5/8/94 FN2924.8
Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N 2 3 N/2 B D e D E -B- A. (.25) M C A A2 L B S NOTES:. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y4.5M-982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.25mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/2 and N/2 + ) for E8.3, E6.3, E8.3, E28.3, E42.6 will have a B dimension of.3 -.45 inch (.76 -.4mm). A e C E C L e A C e B E8.3 (JEDEC MS--BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -.2-5.33 4 A.5 -.39-4 A2.5.95 2.93 4.95 - B.4.22.356.558 - B.45.7.5.77 8, C.8.4.24.355 - D.355.4 9..6 5 D.5 -.3-5 E.3.325 7.62 8.25 6 E.24.28 6. 7. 5 e. BSC 2.54 BSC - e A.3 BSC 7.62 BSC 6 e B -.43 -.92 7 L.5.5 2.93 3.8 4 N 8 8 9 Rev. 2/93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 2 FN2924.8