ADC Resolution: Myth and Reality Mitch Ferguson, Applications Engineering Manager Class ID: CC19I Renesas Electronics America Inc.
Mr. Mitch Ferguson Applications Engineering Manager Specializes support design teams develop analog and lownoise systems using MCUs. Over 15 years of system-level design experience Over 10 years of experience as an application engineer. As a hardware engineer and engineering manager, he has been involved in design in power distribution controls, automotive and fire alarm systems. Bachelor of science in electrical engineering from Cleveland State University 2 2
Renesas Technology & Solution Portfolio 3
8/16-bit 32-bit Microcontroller and Microprocessor Line-up 2010 2012 1200 DMIPS, Superscalar Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 500 DMIPS, Low Power Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 165 DMIPS, FPU, DSC Industrial, 90nm 200µA/MHz, 1.6µA deep standby 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 10 DMIPS, Capacitive Touch Wide Industrial Format & LCDs Automotive, 130nm 350µA/MHz, 1µA standby 1200 DMIPS, Performance Automotive, 40nm 500µA/MHz, 35µA deep standby 165 DMIPS, FPU, DSC Industrial, 40nm 200µA/MHz, 0.3µA deep standby Embedded Security, ASSP Industrial, 90nm 1mA/MHz, 100µA standby 44 DMIPS, True Low Power Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 4
Enabling The Smart Society Collecting, analyzing and transmitting real-world signals is a major focus of the smart society. Real-world signals are analog, so converting these signals to digital is a key focus for the smart Understanding the specifications and hidden errors in ADC circuits will enable designs that meet the intended specifications 5
Agenda What does the resolution spec really mean Some standard converters and resolution DC accuracy specifications Review offset, gain, DNL and INL errors How the ADC is tested What those errors don t tell you AC specifications SNR ENOB System errors and resolution requirements ADC required accuracy Reference errors Source impedance errors 6
Resolution What does the term resolution mean to you? 7
Successive Approximation (SAR) ADC ADC Register Vref AVss DAC (R2R Ladder) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Comparator Input Analog Mux Sample and Hold Circuit DC Specs primarily define this section of ADC performance 8 8
Slope Converter Vcc Measure value R Thermistor or sensor 9 9 R CPU Operation Stopped L GPIO GPIO = L Timer stopped Begin conversion Vref GPIO = Hi-Z Timer started Comp out = H Conversion ends Vc > Vref Comp out = L Timer stops Timer value is proportional to RC time constant Resolution? Start Conversion Timer Enable H L Started Stopped Clock
Delta Sigma Converter 5V 0V Vin 4V +V Ref H D H Digital Filter Result Register CK 10
Delta Sigma Converter Vin Ref D Digital Filter Result Register CK Oversampling frequency (flip flop clock rate, e.g. RX21A 3.125MHz) Minimum Conversion time rate the result register is updated (81.92 us or 12.2 khz on RX21A ) This is based on the decimation factor of the digital filter Some converters allow reducing decimation factor Faster conversion Lower resolution 11
Oversampling Oversampling can increase resolution of ADC 03 ADC Transition Voltages 02 01 S1 S2 S3 S4 x x x x S1 S2 S3 S4 x x x x ADC Input Voltage 00 Result will be 04 when samples are added Result will still be 04 when samples are added if no noise 12
Oversampling How noise helps oversampling 03 02 01 00 x S1 S2 x S3 x x S4 ADC Input Voltage ADC Transition Voltages ADC Input Voltage with noise Result is now 06 13
Oversampling 03 ADC Transition Voltages 02 x S1 S3 x 01 S2 x x S4 ADC Input Voltage 00 ADC Input Voltage with noise Result is now 04 Oversample 2X results in ½ bit increase resolution To increase resolution by n bits Oversample 4 n and decimate 2 n 14
ADC Accuracy Specifications 15
An Explanation of DC Specifications DC accuracy specifications These specifications look at DC or very low frequency input errors Full Scale Non-Linearity Error Ideal Curve ADC Counts Corrected Curve Absolute Error Real Curve 0V Offset Error Input Voltage Vfull Scale 16
AC Specifications DC testing does not describe dynamic characteristic Sample and hold errors AC noise errors Comparator hysteresis AC testing method Input sine wave to ADC input Perform FFT Measure SNDR, SNR and/or Spurious Free Dynamic Range SNR, SNDR Ratio of RMS value to noise SNDR (SINAD) includes harmonics or distortion SFDR - ratio of the RMS value of input sine wave to the RMS value of the largest spur 17
Level[dB] SNDR Results (PGA x1) 200 FFT plot PGA Gain SNDR 180 x1 86.58dB 160 140 x2 86.37dB 120 100 80 x4 x8 81.38dB 78.37dB 60 40 20 x16 x32 74.71dB 71.49dB 0 17Hz 1.71kHz 1 10 100 1000 10000 Frequency[Hz] x64 64.74dB SNDR calculation range Why does SNDR go down as PGA gain goes up 18
Interpreting We can calculate the equivalent perfect ADC from equation ENOB = (SNDR -1.76)/ 6.02 The 6.02 term in the divisor converts decibels (a log 10 representation) to bits (a log 2 representation). The 1.76 term comes from quantization error in an ideal ADC 86 db would then have the equivalent resolution of a 14 bit perfect ADC ENOB = log 2 [full-scale input voltage range/(adc RMS noise 12)] 19
Interpreting Specification AC testing does not provide linearity data DNL and INL do affect SNDR DNL affects SNR INL affect THD Oversampling is still valid and reduces the average noise if Gaussian distribution 20
Example 21
Understanding the Errors an Example Requirements Input = 0V 2.0V +/-.25% of full scale accuracy (+/- 5 mv) Vref = 3.0V Vdd Vdd ADC range and resolution LSB must be < 10 mv 3 V AV REFP AV REFM 0.25% * 2.0V = 10 mv A MCU 10 mv / 3.0V = 1/300 9 bit ADC required 0-2 V ADCin Vss Decreasing Vref to 2.5V 10 mv / 2.5V = 1/250 8 bit ADC meets resolution requirement A D 22
Understanding the Errors an Example Assume Vref = 2.56V, 8 Bit ADC (10 mv per step) Output Code Indicated Voltage (mv) 04 40 mv 03 30 mv 02 20 mv 01 10 mv 00 ½ LSB Offset 0 5 10 15 20 30 40 0 Actual Voltage (mv) 23
Understanding the Errors an Example Can we use a 10 bit ADC with +/- 2 bits INL Each LSB error = 2.5mV (2.56V / 1024) Error for 2 LSB = 5 mv 5 mv/2.0v = 0.25% But there is still an additional ½ LSB quantization error 6.25 mv total error = 0.31% What about 1 bit of error Worst case ADC error is 2.5 mv + 1.25 mv 0.1875% error 24
Understanding the Errors an Example Assume Vref = 2.56V, 10 Bit ADC (2.5 mv per step) Output Code 1.251 mv code 01 Indicated Voltage (mv) 04 10 mv 03 With 2 LSB error 7.5 mv 02 5 mv 01 2.5 mv 00 0 0 1.2 5 2.5 5 7.5 10 Actual Voltage (mv) 25
When is a 16 Bit ADC Not 16 Bit? Specification Condtion Min Typ Max Units TUE - Unadjusted 12 Bit Mode - ± 4 ± 6.8 LSB DNL 12 Bit Mode - ± 0.7-1.1 to +1.9 LSB INL 12 Bit Mode - ± 1.0-2.7 to +1.9 LSB Efs -Full Scale 12 Bit Mode - ± 4 ± 6.8 LSB Eq - Quantization 16 Bit Mode - -1 to 0 13 Bits - ± 0.5 LSB 16 bit single ENOB ended mode avg = 32 12.2 13.9 - bits avg = 4 11.4 13.1 - bits SINAD See ENOB 6.02 X ENOB + 1.76 db THD 16 bit single ended mode - -85 - db 26
System Considerations 27
Errors That Are Sometimes Forgotten System noise Clocks IO port toggles Sensor and reference error Accuracy vs. drift Temperature, age and voltage effects Calibration Vdd Vdd Vref AV REFP Input system effects A AV REFM MCU ADCin T GPIO Vss A D 28
Check Accuracy Conditions Specification may expect: MCU in a sleep mode No IO toggling Specified ADC clock speed 29
What is the ADC Reading for the Circuit Below? 1. Depends on Vref 2. Depends on Vcc 3. Need to know resistor values 4. 512 5. Ask the HW engineer R1 R2 R1=R2 +Vref Vref +V Vcc MCU 10 bit AD Input 30
Ratiometric and Non-Ratiometric Conversions +V +Vref +V +V +Vref +V Vcc Vcc Vcc Vcc Vref Vref Vref Vref MCU MCU MCU MCU AD Input AD Input AD Input AD Input a) ratiometric b) ratiometric c) non-ratiometric d) non-ratiometric 31
Understanding Reference Errors Vref is a power supply pin +V Zt Vref powers R2R ladder Treat as power supply pin Vref Vcc Typically <100 ua Bypass properly Rt T Vm MCU AD Input 3 mv ripple = 1 LSB error on 10bit 3V ADC Rref 32
Understanding Ratiometric Reference Errors Vcc Vref +V Sensor biased from Vref Loads Vcc Vref can pick up noise C2 Vref C1 Bypassing ADC input can help MCU Rt T AD Input Rref C3 33
Reference Errors External References Consider design example Measure 0 2V with < 0.5% FS error 2.5V reference This measurement is non-ratiometric Vcc Vref MCU AD In Assume 10 bit ADC with 1 LSB INL used Previously calculate 0.1875% error from ADC Can I use a 2.56V 0.5% accurate reference diode? 34
Reference Errors Reference Accuracy Can use 0.5% accuracy diode? If no calibration no If calibrate is performed? Depends on drift and temp range LM4040 0.5% accuracy w/ 100 ppm/c 20 ppm typical If operating range is 0-50C max drift 100 ppm/c * 25C =.25% drift Total error still only 0.4375% 35
Source Resistance Errors Vref 10k 10k Rs ADC Input Ckt Equivalent Req S1 Ceq To AD Converter Block For M16C/62P Req = 7.8k Ceq = 1.5 pf S1 closed for 3 fad cycles RC time constant of source resistance and sampling cap can cause error 36
Source Resistance Limitation (An Intuitive Approach) Desired charge error much less than 1/1024 (0.1%) Allow 10 time constants (0.005%) Sampling occurs for 300 nsec (3 cycles of 10 MHz AD clock) 10 time constants = 300 nsec 1 TC = 30 nsec C = 1.5 pf so Rtotal (Rs + Req) must be 20Kohm or less (300 nsec/1.5 pf) Rsource can not be greater than 12.2 K ohms Equivalent resistance of the AD circuit is 7.8K (Strict analysis indicated 13.8 kohm) 37
Source Resistance Errors What can we do? Decrease Rs Could add buffer Vref Buffer adds offset Increase sampling time Add capacitor 40k Rs To AD Converter Block 30k C1 Req S1 Ceq For M16C/62P Req = 7.8k Ceq = 1.5 pf S1 closed for 3 fad cycles 38
Summary What does the resolution spec really mean Some standard converters and resolution DC accuracy specifications Review offset, gain, DNL and INL errors How the ADC is tested What those errors don t tell you AC specifications SNR THD ENOB How does this affect my application Errors and considerations 39
Questions? 40
Enabling The Smart Society Collecting, analyzing and transmitting real-world signals is a major focus of the smart society. Real-world signals are analog, so converting these signals to digital is a key focus for the smart Understanding the specifications of an ADC and the effects of system device selections will help the information delivered by the smart society provide an accurate picture of the world 41
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Also Check the Conditions K10P100M100SF2 Data Sheet Rev 6 44
Delta Sigma Converter 49
Effect of Adding Capacitor to Input Pin Adding capacitor creates a low pass filter fc Rs To AD Converter Block Gain C1 Req S1 Ceq Freq fc = 1/2πRC 20k Rs and.0015 uf = 5.3 khz corner 50
Notes Below a certain frequency, THD is only dependent on the overall INL of the converter For an example, if the converter depicted in Figure 2 is being used to digitize a signal which can slew at an equivalent rate to that of a 10kHz signal, then the "THD" performance of the converter will be roughly -86dB. This figure means that the harmonic distortion is 86dB below the converter's full-scale range. Since the full-scale range of this 16-bit converter is ±32,768, then the harmonic distortion represents roughly ±1.6 LSB of error. 51