EE 330 Lecture 27 Bipolar Processes Comparison of MOS and Bipolar Proces JFET Special Bipolar Processes Thyristors SCR TRIAC
Review from a Previous Lecture B C E E C vertical npn B A-A Section B C E C B E lateral pnp C B E B C E B-B Section
Review from Previous Lecture D S A-A Section S D p-channel JFET B-B Section
Review from Previous Lecture B C E E C vertical npn B B C E C B lateral pnp E C B E E B C
Review from Previous Lecture Diode (capacitor) S W L D D S D Resistor S n-channel JFET
Will consider next the JFET but first some additional information about MOS Devices Enhancement and Depletion MOS Devices Enhancement Mode n-channel devices V T > 0 Enhancement Mode p-channel devices V T < 0 Depletion Mode n-channel devices V T < 0 Depletion Mode p-channel devices V T > 0
Enhancement and Depletion MOS Devices n-channel p-channel Enhancement Depletion Depletion mode devices require only one additional mask step Older n-mos and p-mos processes usually had depletion device and enhancement device Depletion devices usually not available in CMOS because applications usually do not justify the small increasing costs in processing
S The JFET D With V S =0, channel exists under gate between D and S S D Under sufficiently large reverse bias (channel disappears - pinches off )
S The JFET D S D Under smaller reverse bias (channel thins)
S The JFET D S D Under small reverse bias and large negative V DS (channel pinches off)
The JFET D D S D S n-channel S p-channel p-channel JFET Square-law model of p-channel JFET 0 VS VP 2IDSSp VDS I 0.3 2 V -V - V V V V S+0.3 V > V -V VP 2 2 V S IDSSp 1-0.3 VS VP V DS< V S-VP VP D S P DS S P DS S P (I DSSp carries negative sign) Functionally identical to the square-law model of MOSFET Parameters I DSS and V P characterize the device I DSS proportional to W/L where W and L are width and length of n+ diff V P is negative for n-channel device, positive for p-channel device thus JFET is depletion mode device Must not forward bias S junction by over about 300mV or excessive base current will flow (red constraint) Widely used as input stage for bipolar op amps
The JFET D D S D S n-channel S p-channel n-channel JFET (not available in this process) Square-law model of n-channel JFET 0 VS VP 2IDSS VDS I 0.3 0.3 2 V -V - V V V VS V < V -V VP 2 2 V S IDSS 1-0.3 VS VP VDS > VS -VP VP D S P DS S P DS S P Functionally identical to the square-law model of MOSFET Parameters I DSS and V P characterize the device I DSS proportional to W/L where W and L are width and length of n+ diff V P is negative for n-channel device, positive for p-channel device thus JFET is depletion mode device Must not forward bias S junction by over about 300mV or excessive base current will flow (red constraint) Widely used as input stage for bipolar op amps
The Schottky Diode C A Metal-Semiconductor Junction One contact is ohmic, other is rectifying Not available in all processes Relatively inexpensive adder in some processes Lower cut-in voltage than pn junction diode High speed
The MESFET S D Metal-Semiconductor Junction for ate Drain and Source contacts ohmic, other is rectifying Usually not available in standard CMOS processes Must not forward bias very much Lower cut-in voltage than pn junction diode High speed
The Thyristor A bipolar device in CMOS Processes Consider a Bulk-CMOS Process S D S D p n p n Have formed a lateral pnpn device! Will spend some time studying pnpn devices
MOS and Bipolar Area Comparisions How does the area required to realize a MOSFET compare to that required to realize a BJT? Will consider a minimum-sized device in both processes
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 5 10 Consider Initially the Emitter in the BJT surrounded by a base region 15 20 25 30 35 40 45 50 55
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 5 From design rules (left to right) 4.3, 5.1, 5.4, 5.6, 5.5 10 15 20 25 4 30 35 2 3 2 2 12 40 19 45 50 55
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 5 10 Add n+ buried for collector From design rule 1.2 15 20 23 25 2 30 35 40 45 50 55
1 5 10 Add n-epi region from design rules 2.3 and 3.3 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 51 15 20 23 25 30 14 14 14 14 35 40 45 50 55
1 5 Add contact to n-epi region from design rules 2.3 and 3.3 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 51 10 15 20 23 25 14 14 30 4 3 2 35 40 45 50 55
1 5 But, there are some rather strict rules relating to the epi contact 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 from (left to right) rules 4.4, 5.4, 4.6 10 61 15 20 25 30 12 2 14 2 19 14 35 4 6 40 45 50 NOT TO SCALE Note: 26 required Between p-base and isolation diffusion 55
1 5 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 Consider a structure with a collector contact on both sides of epi 10 71 15 20 14 Note: Not to vertical Scale 25 30 35 44 12 2 19 26 40 2 6 45 50 55 Note: 26 required Between p-base and isolation diffusion
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 71 5 10 Note: Not to vertical Scale 15 4 20 19 25 30 44 12 2 6 26 35 26 40 45 Note: 26 required Between p-base and isolation diffusion 50 55
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 71 5 10 15 20 25 30 44 75 48 35 40 45 Note: Not to vertical Scale 50 55
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 5 10 15 20 25 75 48 30 35 40 45 Note: Not to vertical Scale Bounding Area = 3600 2 50 55 Major contributor to large size of BJT is the isolation diffusion which diffuses laterally a large distance beyond the drawn edges of the isolation mask
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 5 10 15 Comparison with Area for n-channel MOSFET in Bulk CMOS 20 16 25 30 13 35 40 Bounding Area = 208 2 45 50 55
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 5 10 15 Minimum-Sized MOSFET 20 14 25 30 12 35 40 45 Bounding Area = 168 2 Active Area = 6 2 50 55
1 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 5 10 15 20 25 75 48 30 35 40 45 MOSFET BJT 50 55 Note: Not to vertical Scale
Area Comparison between BJT and MOSFET BJT Area = 3600 2 n-channel MOSFET Area = 168 2 Area Ratio = 21:1
Thyristors The good and the bad!
Thyristors The good SCRs Triacs The bad Parasitic Device that can destroy integrated circuits
The SCR Silicon Controlled Rectifier Widely used to switch large resistive or inductive loads Widely used in the power electronics field Widely used in consumer electronic to interface between logic and power Anode A ate C Cathode Usually made by diffusions in silicon p n p n A A A C C C Symbols Consider first how this 4-layer 3-junction device operates
Operation of the SCR A I F A p n p I C V F n V C A I F A C 1 n n B 1 p p C 2 E 1 n C Not actually separated but useful for describing operation p E 2 B 2 I C1 Q 1 I B2 C Q 2 I C2 I B1 I
Variation of Current ain (β) with Bias for BJT Note that current gain gets very small at low base current levels
I Operation of the SCR I A C I F p n p n C 1 n n B 1 p p C 2 E 1 n V F C I C1 Q 1 I B2 I F I B1 A p Q 2 A I C2 I E 2 B 2 Consider a small positive bias (voltage or current) on the gate (V C <0.5V) and a positive and large voltage V F Will have VC1 VF - 0.5V Thus Q 1 has a large positive voltage on its collector Since VB E1 is small, I C1 will be small as will I C2 so diode equation governs BE junction of Q 1 I F will be very small C
Operation of the SCR A I F C 1 n n B 1 p p C 2 E 1 n C I F A p A E 2 B 2 I I C p n p n V F I C1 Q 1 I B2 C I B1 Q 2 I C2 I Now let bias on the gate increase (V C around 0.6V) so Q 1 and Q 2 in FA V V - 0.5V C1 F From diode equation, base voltage V BE1 will increase and collector current I C1 will increase Thus base current I B2 will increase as will the collector current of I C2 Under assumption of operation in FA region get expression I = I + β β I B1 1 2 B1 This is regenerative feedback (actually can show pole in RHP)
Very Approximate Analysis Showing RHP Pole A R L I C1 I B2 I F A Q 2 C 1 n n B 1 p p C 2 E 1 n C p E 2 B 2 V CC V F Q 1 I C2 V C I B1 CB I I V I RBE sr C 1 BE B 1 2 V sc I I I I B B1 C 2 I C2 1 2 B1 I R V B1 BE p 1 2 1 R C BE B
End of Lecture 27