SupIRBuck TM PD-600 HIGHLY INTEGRATED 4A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR eatures Wide Input Vltage Range 2.5V t 2V Wide Output Vltage Range 0.6V t 2V Cntinuus 4A Lad Capability 00kHz High requency Operatin Prgrammable Over-Current Prtectin Prgrammable PGd Output Hiccup Current Limit Precisin Reference Vltage (0.6V) Prgrammable Sft-Start Pre-Bias Start-up Thermal Prtectin Thermally Enhanced Package Small Size 5mmx6mm QN Pb-ree (RHS Cmpliant) Applicatins Distributed Pint-f-Lads Server and Wrkstatins Embedded Systems Strage Systems DDR Applicatins Graphics Cards Game Cnsles Cmputing Peripheral Vltage Regulatrs Descriptin The IR820A SupIRBuck TM is an easy-t-use, fully integrated and highly efficient DC/DC regulatr. The nbard switching cntrller and MOSETs make the IR820A a space-efficient slutin, prviding accurate pwer delivery fr lw utput vltage applicatins. The IR820A perates frm a single 4.5V t 4V input supply and generates an utput vltage adjustable frm 0.6V t 0.8*Vin at lads up t 4A. A versatile regulatr ffering prgrammability f startup time, pwer gd threshld and current limit, the IR820A s fixed 00kHz switching frequency allws the use f small external cmpnents. The IR820A als features imprtant prtectin functins, such as Pre-Bias startup, hiccup current limit and thermal shutdwn t prvide the required system level security in the event f fault cnditins. ig.. Typical applicatin diagram /04/08
ABSOLUTE MAXIMUM RATINGS (Vltages referenced t GND) PACKAGE INORMATION 5mm x 6mm POWER QN PD-600 V IN Supply Vltage -0.V t 24V Vcc Supply Vltage -0.V t 6V Vc Supply Vltage -0.V t 0V SW -0.V t 0V PGd -0.V t 6V b,comp,ss,vsns -0.V t.5v OCSet 0mA AGnd t PGnd -0.V t +0.V Strage Temperature Range -65 C T 50 C Operating Junctin Temperature Range -40 C T 50 C ESD Classificatin JEDEC, JESD22-A4 Misture Sensitivity Level JEDEC Level @ 260 C Cautin: Stresses beynd thse listed under Abslute Maximum Rating may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins is nt implied. Expsure t Abslute Maximum Rating cnditins fr extended perids may affect device reliability. 2 V IN SW 0 PGnd θ θ JA J-PCB 5 C / W 2 C / W HG 5 AGnd 9 PGd V C 4 8 V CC 2 4 5 6 7 Vsns B COMP AGnd AGnd SS OCSet ig. 2: Package utline (Tp view) ORDERING INORMATION PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR820AMTRPb 5 4000 M IR820AMTRPb 5 750 /04/08 2
Blck Diagram PD-600 ig.. Simplified blck diagram f the IR820A. /04/08
Pin Descriptin PD-600 Pin Name Descriptin Vsns PGd sense pin. Use tw external resistrs t prgram the pwer gd threshld. 2 b Inverting input t the errr amplifier. This pin is cnnected directly t the utput f the regulatr via resistr divider t set the utput vltage and prvide feedback t the errr amplifier. Cmp Output f errr amplifier. 4 AGnd Signal grund fr internal reference and cntrl circuitry. 5 AGnd Signal grund fr internal reference and cntrl circuitry. 6 SS/SD Sft start / shutdwn. This pin prvides user prgrammable sft-start functin. Cnnect an external capacitr frm this pin t signal grund (AGnd) t set the start up time f the utput vltage. The cnverter can be shutdwn by pulling this pin belw 0.V. 7 OCSet Current limit set pint. A resistr frm this pin t SW pin will set the current limit threshld. 8 V CC This pin prvides biasing vltage fr the internal blcks f the IC. It als pwers the lw side driver. A minimum f 0.u, high frequency capacitr must be cnnected frm this pin t pwer grund (PGnd). 9 PGd Pwer Gd status pin. Output is pen cllectr. Cnnect a pull up resistr frm this pin t Vcc. 0 PGnd Pwer Grund. This pin serves as a separated grund fr the MOSET drivers and shuld be cnnected t the system s pwer grund plane. SW Switch nde. This pin is cnnected t the utput inductr 2 V IN Input vltage cnnectin pin HG This pin is cnnected t the high side Msfet gate. Cnnect a small capacitr frm this pin t switch nde (SW). 4 V C This pin pwers the high side driver and must be cnnected t a vltage higher than input vltage. A minimum f 0.u high frequency capacitr must be cnnected frm this pin t the pwer grund (PGnd). 5 AGnd Signal grund fr internal reference and cntrl circuitry. Pins 4, 5 and 5 need t be cnnected tgether n system bard. /04/08 4
Recmmended Operating Cnditins PD-600 Symbl Definitin Min Max Units V in Input Vltage 2.5 2 V cc Supply Vltage 4.5 4 V c Supply Vltage Vin + 5V 28 V V Output Vltage 0.6 2 I Nte Output Current 0 4 A T j Junctin Temperature -40 25 C Electrical Specificatins Unless therwise specified, these specificatin apply ver VinV cc V c 2V, 0 C<T j (Ic)<05 C. Typical values are specified at T a 25 C. Pwer Lss Parameter Symbl Test Cnditin Min TYP MAX Units Pwer Lss P lss VccV in 2V, Vc24V, V.8V, I 4A, L.0uH, Nte.7 W MOSET R ds(n) Tp Switch R ds(n)_tp I D A, Tj(MOSET)25 C 6.9 8.7 Bttm Switch R ds(n)_bt I D A, Tj(MOSET)25 C 6.9 8.7 mω Reference Vltage eedback Vltage V B 0.6 V Accuracy 0 C<Tj<05 C -.5 +.5 % -40 C<Tj<05 C, Nte2 -.5 +.5 % Supply Current V CC Supply Current (Static) I CC(Static) SS0V, N Switching 0 V C Supply Current (Static) V CC Supply Current (Dynamic) V C Supply Current (Dynamic) Under Vltage Lckut I C(Static) SS0V, N Switching 4.5 7 I CC(Dynamic) I C(Dynamic) SSV, V c 24V, V cc V in 2V. V.8V, I0A SSV, V c 24V, V cc V in 2V. V.8V, I0A 5 22 5 22 ma V CC -Start-Threshld V CC _UVLO(R) Supply ramping up 4.0 4.4 V CC -Stp-Threshld V CC _UVLO() Supply ramping dwn.7 4. V CC -Hysteresis Supply ramping up and dwn 0.5 0.25 0. V C -Start-Threshld V C _UVLO(R) Supply ramping up..5 V V C -Stp-Threshld V C _UVLO() Supply ramping dwn 2.85.25 V C -Hysteresis Supply ramping up and dwn 0.5 0.2 0.25 /04/08 5
PD-600 Parameter SYM Test Cnditin Min TYP MAX Units Oscillatr requency S 270 00 0 khz Ramp Amplitude V ramp Nte.25 V Min Pulse Width D min(ctrl) Nte 80 ns Max Duty Cycle D max b0v 80 % Errr Amplifier Input Bias Current I B SSV -0. -0.5 Input Bias Current I B2 SS0V 20 5 50 Surce/Sink Current I(surce/Sink) 50 70 90 μa Transcnductance gm 000 00 600 μmh Sft Start/SD Sft Start Current I SS SS0V 5 20 28 μa Shutdwn Output Threshld SD 0.25 V Pwer Gd Vsns Lw Trip Pint Vsns(trip) Vsns Ramping Dwn 0.5 0.8 0.4 V Hysteresis PGd(Hys) 5 27.5 40 mv PGd Output Lw Vltage PG(vltage) I PGd 4mA 0.25 0.5 V Input Bias Current Isns 0 0. μa Over Current Prtectin OCSET Current I OCSET 5 20 26 Hiccup Current I Hiccup Nte μa Hiccup Duty Cycle Hiccup(duty) I Hiccup / I SS, Nte 5 % Thermal Shutdwn Thermal Shutdwn Threshld Thermal Shutdwn Hysteresis 40 Nte Nte 20 C Nte: Cntinuus utput current determined by input and utput vltage setting and the thermal envirnment. Nte2: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin. Nte: Guaranteed by Design but nt tested in prductin. /04/08 6
TYPICAL OPERATING CHARACTERISTICS (-40 C - 25 C) PD-600 Icc(static) Ic(static) [ma].0 2.0.0 0.0 9.0 8.0 7.0-40 -20 0 20 40 60 80 00 20 Temp[C] [ma] 7.0 6.0 5.0 4.0.0 2.0-40 -20 0 20 40 60 80 00 20 Temp[C] Icc(dynamic) Ic(dynamic) [ma] 22.0 2.0 20.0 9.0 8.0 7.0 6.0 5.0 4.0.0-40 -20 0 20 40 60 80 00 20 Temp[C] [ma] 22.0 2.0 20.0 9.0 8.0 7.0 6.0 5.0 4.0.0-40 -20 0 20 40 60 80 00 20 Temp[C] Vfb ISS [mv] 605.0 600.0 595.0 590.0 585.0-40 -20 0 20 40 60 80 00 20 Temp[C] [ua] 27.0 25.0 2.0 2.0 9.0 7.0 5.0-40 -20 0 20 40 60 80 00 20 Temp[C] Transcnductance IOCSET [mmh].60.55.50.45.40.5.0.25.20.5.0.05.00-40 -20 0 20 40 60 80 00 20 Temp[C] [ua] 26.0 25.0 24.0 2.0 22.0 2.0 20.0 9.0 8.0 7.0 6.0 5.0-40 -20 0 20 40 60 80 00 20 Temp[C] /04/08 7
Circuit Descriptin THEORY O OPERATION The IR820A is a vltage mde PWM synchrnus regulatr and perates with a fixed 00kHz switching frequency, allwing the use f small external cmpnents. The utput vltage is set by feedback pin (b) and the internal reference vltage (0.6V). These are tw inputs t errr amplifier. The errr signal between these tw inputs is amplified and it is cmpared t a fixed frequency linear sawtth ramp. A trailing edge mdulatin is used fr generating fixed frequency pulses (PWM) which drives the internal N-channel MOSETs. The internal scillatr circuit uses n-chip circuitry, eliminating the need fr external cmpnents. The IR820A perates with single input vltage frm 4.5V t 4V allwing an extended perating input vltage range. The ver-current prtectin is perfrmed by sensing current thrugh the R DS(n) f lw side MOSET. This methd enhances the cnverter s efficiency and reduces cst by eliminating a current sense resistr. The current limit is prgrammable by using an external resistr. Under-Vltage Lckut The under-vltage lckut circuit mnitrs the tw input supplies (Vcc and Vc) and assures that the MOSET driver utputs remain in the ff state whenever the supply vltage drps belw set threshlds. Lckut ccurs if Vcc r Vc fall belw 4.V and.v respectively. Nrmal peratin resumes nce Vcc and Vc rise abve the set values. Thermal Shutdwn Temperature sensing is prvided inside the IR820A. The trip threshld is typically set t 40 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSETs. Thermal shutdwn is nt latched and autmatic restart is initiated when the sensed temperature drps within the perating range. There is a 20 C hysteresis in the thermal shutdwn threshld. PD-600 Pre-Bias Startup The IR820A is able t start up int pre-charged utput, which prevents scillatin and disturbances f the utput vltage. The utput starts in asynchrnus fashin and keeps the synchrnus MOSET ff until the first gate signal fr cntrl MOSET is generated. igure 4 shws a typical Pre-Bias cnditin at start up. Depending n system cnfiguratin, a specific amunt f utput capacitrs may be required t prevent discharging the utput vltage. V Pre-Bias Vltage ig. 4: Pre-Bias start up V Time Shutdwn The utput can be shutdwn by pulling the sftstart pin belw 0.V. This can easily be dne by using an external small signal transistr. During shutdwn bth MOSET drivers will be turned ff. Nrmal peratin will resume by cycling sft start pin. Pwer Gd The IR820A prvides an pen cllectr pwer gd signal which reprts the status f the utput. The utput is sensed thrugh the dedicated Vsns pin. The pwer gd threshld can be externally prgrammed using tw external resistrs. The pwer gd cmparatr is internally set t 0.8V (typical). /04/08 8
Sft-Start The IR820A has prgrammable sft-start t cntrl the utput vltage rise and limit the inrush current during start-up. T ensure crrect start-up, the sft-start sequence initiates when Vcc and Vc rise abve their threshld and generate the Pwer On Ready (POR) signal. The sft-start functin perates by surcing current t charge an external capacitr t abut V. Initially, the sft-start functin clamps the utput f errr amplifier by injecting a current (40uA) int the b pin and generates a vltage abut 0.96V (40ux24K) acrss the negative input f errr amplifier (see figure 5). The magnitude f the injected current is inversely prprtinal t the vltage at the sft-start pin. As the sft-start vltage ramps up, the injected current decreases linearly and s des the vltage at negative input f errr amplifier. When the sft-start capacitr is arund V, the vltage at the psitive input f the errr amplifier is apprximately 0.6V. The utput f errr amplifier will start increasing and generating the first PWM signal. As the sftstart capacitr vltage cntinues t rise up, the current flwing int the b pin will keep decreasing. The feedback vltage increases linearly as the sft start vltage ramps up. When sft-start vltage is arund 2V, the utput vltage reaches the steady state and the injected current is zer. igure 6 shws the theretical perating wavefrms during sft-start. The utput vltage start-up time is the time perid when sft-start capacitr vltage increases frm V t 2V. The start-up time will be dependent n the size f the external sft-start capacitr and can be estimated by: T 20μA C start ss 2V V SS/SD Cmp 0.6V b POR 20uA PD-600 24K 24K V 40uA Errr Amp ig. 5: Sft-Start circuit fr IR820A Output f UVLO POR Sft-Start Vltage Current flwing int b pin Vltage at negative input 0.96V f Errr Amp Vltage at b pin 0V 40uA 0V 0uA 0.6V 0.6V V 2V V ig. 6: Theretical peratin wavefrms during sft-start r a given start-up time, the sft-start capacitr can be estimated as: CSS 20μA * Tstart( ms) --( ) /04/08 9
Over-Current Prtectin PD-600 The ver-current prtectin is perfrmed by sensing current thrugh the R DS(n) f the lw side MOSET. This methd enhances the cnverter s efficiency and reduces cst by eliminating a current sense resistr. As shwn in figure 7, an external resistr (R SET ) is cnnected between OCSet pin and the inductr pint which sets the current limit set pint. The internal current surce develps a vltage acrss R SET. When the lw side MOSET is turned n, the inductr current flws thrugh the Q2 and results a vltage which is given by: VOCSet (IOCSet ROCSet ) (RDS(n) IL ) --( 2) ig. 8: ua current surce fr discharging sft-start capacitr during hiccup The OCP circuit starts sampling current when the lw gate drive is abut V. The OCSet pin is internally clamped abut.5v during n time f high side gate t prevent false trigging, figure 9 shws the OCSet pin during ne switching cycle. As shwn, there is abut 50ns delay t mask the dead time. Since this nde cntains switching nises, this delay als functins as a filter. Deadtime ig. 7: Cnnectin f ver current sensing resistr I OCSet *R OCSet Blanking time Clamp vltage The critical inductr current can be calculated by setting: VOCSet (IOCSet ROCSet) (RDS(n) IL) 0 I SET I L( critical ) R OCSet --( ) An ver-current is detected if the OCSet pin ges belw grund. This trips the OCP cmparatr and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by charging and discharging the sft-start capacitr in a certain slpe rate. As shwn in figure 8 a ua current surce is used t discharge the sft-start capacitr. The OCP cmparatr resets after every sft start cycle. The cnverter stays in this mde until the verlad r shrt circuit is remved. The cnverter will autmatically recver. R I DS ( n ) OCSet ig. 9: OCset pin during nrmal cnditin Ch: Inductr pint, Ch:OCSet The value f R SET shuld be checked in an actual circuit t ensure that the ver-current prtectin circuit activates as expected. The IR820A current limit is designed primarily as disaster preventing, and desn't perate as a precisin current regulatr. /04/08 0
Applicatin Infrmatin Design Example: The fllwing example is a typical applicatin fr the IR820A. The applicatin circuit is shwn in page 7. V V I ΔV in s 2V,(.2V, max.8v 4 A 0 mv 00 khz Output Vltage Prgramming Output vltage is prgrammed by reference vltage and external vltage divider. The b pin is the inverting input f the errr amplifier, which is internally referenced t 0.6V. The divider is ratied t prvide 0.6V at the b pin when the utput is at its desired value. The utput vltage is defined by using the fllwing equatin: V V ref R + R 8 9 When an external resistr divider is cnnected t the utput as shwn in figure 0. IR624 IR820A b ) --(4 ) VOUT R8 R9 PD-600 Sft-Start Prgramming The sft-start timing can be prgrammed by selecting the sft-start capacitance value. The start-up time f the cnverter can be calculated by using: CSS 20μA * T Where T start is the desired start-up time (ms) r a start-up time f ms, the sft-start capacitr will be 0.22u. Vc supply fr single input vltage T drive the high-side switch, it is necessary t supply a gate vltage at least 4V greater than the bus vltage. This is achieved by using a charge pump cnfiguratin as shwn in figure. This methd is simple and inexpensive. The peratin f the circuit is as fllws: when the lwer MOSET is turned n, the capacitr (C) is pulled dwn t grund and charges, up t V BUS value, thrugh the dide (D). The bus vltage will be added t this vltage when upper MOSET turns n in next cycle, and prviding supply vltage (Vc) thrugh dide (D2). Vc is apprximately: ( V V ) --(6 ) V 2 V + C bus D D2 --( ) Capacitrs in the range f 0.u are generally adequate fr mst applicatins. The dides must be a fast recvery device t minimize the amunt f charge fed back frm the charge pump capacitr int V BUS. The dides need t be able t blck the full pwer rail vltage, which is seen when the high-side MOSET is switched n. r lw-vltage applicatin, schttky dides can be used t minimize frward drp acrss the dides at start up. start ig. 0: Typical applicatin f the IR820A fr prgramming the utput vltage Equatin (4) can be rewritten as: Vref R9 R8 --(5 ) V V O ref r the calculated values f R 8 and R 9 feedback cmpensatin sectin. see ig. : Charge pump circuit t generate Vc vltage /04/08
Input Capacitr Selectin The input filter capacitr shuld be selected based n hw much ripple the supply can tlerate n the DC input line. The ripple current generated during the n time f upper MOSET shuld be prvided by the input capacitr. The RMS value f this ripple is expressed by: V Where: D Vin D is the Duty Cycle I RMS is the RMS value f the input capacitr current. I is the utput current. r I4A and D0.5, the I RMS 5A. Ceramic capacitrs are recmmended due t their peak current capabilities. They als feature lw ESR and ESL at higher frequency which enables better efficiency. Use x0u, 6V ceramic capacitrs. Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. A lw inductr value causes a large ripple current, resulting in the smaller size, faster respnse t a lad transient but pr efficiency and high utput nise. Generally, the selectin f the inductr value can be reduced t the desired maximum ripple current in the inductr ( Δi ). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. r the buck cnverter, the inductr value fr the desired perating ripple current can be determined using the fllwing: L V Where: V in IRMS I D ( D) Δ i V V L t D in ; Δ Δt Δt Turn n time V V Δi * --(7) ( V ) --(8 ) V Output Vltage in Maximum input vltage Δi Inductr ripple current Switching frequency s D Duty cycle in s s PD-600 If Δi 40%( I), then the utput inductr will be: L.0uH Delta MPL-04 series prvides a range f inductrs in different values and lw prfile suitable fr large currents. Output Capacitr Selectin The vltage ripple and transient requirements determine the utput capacitrs type and values. The criteria is nrmally based n the value f the Effective Series Resistance (ESR). Hwever the actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing cmpnents. These cmpnents can be described as: ΔV ΔV ΔV ΔV ΔV ( ESR) ( ESL) ( C) + ΔV ΔI * ESR Vin * ESL L ΔIL 8 * C * + ΔV - -(9) ΔV Output vltage ripple ΔI Inductr ripple current L ( ESR) L s ( ESL) ( C) Since the utput capacitr has a majr rle in the verall perfrmance f the cnverter and determine the result f transient respnse, selectin f the capacitr is critical. The IR820A can perfrm well with all types f capacitrs. As a rule the capacitr must have lw enugh ESR t meet utput ripple and lad transient requirements, yet have high enugh ESR t satisfy stability requirements. The gal fr this design is t meet the vltage ripple requirement in the smallest pssible capacitr size. Therefre, a ceramic capacitr is selected due t its lw ESR and small size. Six f the Panasnic ECJ2B0J226M (22u, 6.V, X5R and EIA 0805 case size) are a gd chice. In the case f tantalum r lw ESR electrlytic capacitrs, the ESR dminates the utput vltage ripple, equatin (9) can be used t calculate the required ESR fr the specific vltage ripple. /04/08 2
eedback Cmpensatin The IR820A is a vltage mde cntrller; the cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed lp transfer functin with the highest 0dB crssing frequency and adequate phase margin (greater than 45 ). The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure ). The resnant frequency f the LC filter expressed as fllws: PD-600 The ESR zer f the utput capacitr expressed as fllws: - - - (2) ESR 2 π * ESR* C VOUT R8 R9 VRE H(s) db b Gain(dB) E/A Cmp R C4 Ve CPOLE LC 2 π L C - - - () Z requency igure shws gain and phase f the LC filter. Since we already have 80 phase shift frm the utput filter alne, the system risks being unstable. 0dB Gain LC -40dB/decade requency Phase The IR820A s errr amplifier is a differentialinput transcnductance amplifier. The utput is available fr DC gain cntrl r AC phase cmpensatin. The errr amplifier can be cmpensated either in type II r type III cmpensatin. When it is used in type II cmpensatin the transcnductance prperties f the errr amplifier becme evident and can be used t cancel ne f the utput filter ples. This will be accmplished with a series RC circuit frm Cmp pin t grund as shwn in figure 4. This methd requires that the utput capacitr shuld have enugh ESR t satisfy stability requirements. In general the utput capacitr s ESR generates a zer typically at 5kHz t 50kHz which is essential fr an acceptable phase margin. 0-80 LC ig. : Gain and Phase f LC filter requency ig. 4: TypeII cmpensatin netwrk and its asympttic gain plt The transfer functin (Ve/V) is given by: H(s) R9 gm * R + R 9 + src 4 * sc - - - () The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: R 9 gm * * R R9 R + 8 z * R * C [ H( s) ] The gain is determined by the vltage divider and errr amplifier s transcnductance gain. irst select the desired zer-crssver frequency (): > and /5 ~/0 * ESR Use the fllwing equatin t calculate R: V R sc 8 4 Where: V in Maximum Input Vltage V sc Oscillatr Ramp Vltage Crssver requency ESR Zer requency f the Output Capacitr LC Resnant requency f the Output ilter R 8 and R 9 eedback Resistr Dividers g m Errr Amplifier Transcnductance 4 - - - (5) - - - (4) ( ) s * * * (R + R ) ESR 8 9 2 V * * R * g in LC 9 m - - - (6) /04/08
PD-600 T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: ZIN VOUT C 75% z LC z 0. 75 * L * C - - - (7) C7 R0 R8 R C4 Zf Use equatins (5) and (6) t calculate C4. One mre capacitr is smetimes added in parallel with C4 and R. This intrduces ne mre ple which is mainly used t suppress the switching nise. The additinal ple is given by: P C4 * CPOLE * R * C + C POLE The ple sets t ne half f switching frequency which results in the capacitr C POLE : C POLE π * R * s r << P 2 r a general slutin fr uncnditinal stability fr any type f utput capacitrs, in a wide range f ESR values we shuld implement lcal feedback with a cmpensatin netwrk (type III). The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 5. In such a cnfiguratin, the transfer functin is given by: V g Z e m f V + g Z The errr amplifier gain is independent f the transcnductance under the fllwing cnditin: By replacing Z in and Z f accrding t figure 5, the transfrmer functin can be expressed as: s 4 C gm * Zf >> and gm * Zin >> m 4 π * R * IN s - - - (8) [ + sc ( R + R )] ( + src4 ) * 7 8 H( s) * sr ( C + C ) 8 4 C * C 4 + sr * ( + sr C C + 4 0 0 C ) 7 H(s) db ig.5: Cmpensatin netwrk with lcal feedback and its asympttic gain plt As knwn, the transcnductance amplifier has high impedance (current surce) utput, therefre, cnsideratin shuld be taken when lading the errr amplifier utput. It may exceed its surce/sink utput current capability, s that the amplifier will nt be able t swing its utput vltage ver the necessary range. The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: P P 2 P z z2 Gain(dB) 0 * R 0 7 R9 * C 4 7 C * C * R 4 * R C C + 4 * R * C * C * ( R + R ) * C * R 8 VRE Crss ver frequency is expressed as: V in R * C * * 7 V * L * C sc b 0 E/A Z Z2 P2 P * C 7 8 Cmp requency Ve /04/08 4
PD-600 Based n the frequency f the zer generated by the utput capacitr and its ESR versus crssver frequency, the cmpensatin type can be different. The table belw shws the cmpensatin types and lcatin f crssver frequency. Cmpensatr type Type II(PI) Type III (PID) Methd A Type III(PID) Methd B ESR vs. LC < ESR < < s/2 LC < < ESR < s/2 LC < < s/2 < ESR Output capacitr Electrlytic, Tantalum Tantalum, ceramic Ceramic Table- The cmpensatin type and lcatin f ESR versus The details f these cmpensatin types are discussed in applicatin nte AN-04 which can be dwnladed frm IR s website at www.irf.cm. r this design we have: V in 2V V.8V V sc.25v V ref 0.6V g m 000umh L.0uH C 6x22u, ESR0.5mOhm s 00kHz The value f the capacitance used in the cmpensatr design must be the small signal value. r instance, the small signal capacitance f the 22u capacitr used in this design is 2u at.8 VDC bias and 600 khz frequency. It is this value that must be used fr all cmputatins related t the cmpensatin. The small signal value may be btained frm the manufacturer s datasheets, design tls r SPICE mdels. Alternatively, they may als be inferred frm measuring the pwer stage transfer functin f the cnverter and measuring the duble ple frequency LC and using equatin () t cmpute the small signal C. These result t: LC 8.76kHz ESR 4.4MHz s/2 00kHz Select crssver frequency: 60kHz Since: LC<<s/2<ESR, type III methd B is selected t place the ples and zers. The fllwing design rules will give a crssver frequency apprximately ne-tenth f the switching frequency. The higher the band width, the ptentially faster the lad transient respnse. The DC gain will be large enugh t prvide high DC-regulatin accuracy (typically -5dB t -2dB). The phase margin shuld be greater than 45 fr verall stability. Desired Phase Bst: R Z2 Z2 P2 P2 -SinΘ * + SinΘ 0.58kHz + SinΘ * -SinΘ 40.28kHz Select: CalculateC CalculateR 0.5* Select: C 80p * * L * C *V R C *V Select: R 5.80KΩ C4 * * R C * * R 0 * C * Select: R R8 * C * Vref R9 V -V Z 7 0 ref Z P andc,r : andr ; R 2.6K Ω 7 4 0 7 7 P2 Z2 and : 0.5* ;C.9n, Select: C ;C 67.5p,Select: C 2.60KΩ, checkr * R ; R 40.0KΩ,Select: R 8 8 in ( /5 ~/0) s < and * ESR 2.2n 9p g -R ; R 80.97KΩ,Select: R 80.6K Ω 9 Z2 4 0 0 OSC 9 8 Θ max 70 P, R 5.7KΩ, checkr 4 s 0 9 m 8 40.2K Ω 2 g m /04/08 5
PD-600 Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr (R SET ) frm drain f the lw-side MOSET t the OCSet pin. The resistr can be calculated by using equatin (). The R DS(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrse case peratin. This resistr must be placed clse t the IC, place a small ceramic capacitr frm this pin t pwer grund (PGnd) fr nise rejectin purpses. I I I R R SET Δi I where : L(critical ) R ROCSet I R Δi ISET (I.5) + 2 where : 2.KΩ DS(n) : Max Output Current OCSet υ : Temperature Dependency if 5V is used fr V : Inductr ripple current V Δi (Vin -V ) V L - -() 6.9mΩ υ 6.9mΩ.5 0.5mΩ Nte : Use 9. mω fr lw - side DS(n) SET (4A*.5) + 2.55A 2.55A OCSet 7 in MOSET Setting the Pwer Gd Threshld Pwer Gd threshld can be prgrammed by using tw external resistrs (see figure 6). s cc Layut Cnsideratin The layut is very imprtant when designing high frequency switching cnverters. Layut will affect nise pickup and can cause a gd design t perfrm with less than expected results. Start t place the pwer cmpnents, making all the cnnectin in the tp layer with wide, cpper filled areas. The inductr, utput capacitr and the IR820A shuld be as clse t each ther as pssible. This helps t reduce the EMI radiated by the pwer traces due t the high switching currents thrugh them. Place the input capacitr directly t the Vin pin f IR820A. T reduce the ESR replace the single input capacitr with tw parallel units. The feedback part f the system shuld be kept away frm the inductr and ther nise surces. The critical bypass cmpnents such as capacitrs fr Vcc and Vc shuld be clse t their respective pins. It is imprtant t place the feedback cmpnents including feedback resistrs and cmpensatin cmpnents clse t b and Cmp pins. In a multilayer PCB use ne layer as a pwer grund plane and have a cntrl circuit grund (analg grund), t which all signals are referenced. The gal is t lcalize the high current path t a separate lp that des nt interfere with the mre sensitive analg cntrl functin. These tw grunds must be cnnected tgether n the PC bard layut at a single pint. The Pwer QN is a thermally enhanced package. Based n thermal perfrmance it is recmmended t use at least a 4-layers PCB. T effectively remve heat frm the device the expsed pad shuld be cnnected t the grund plane using vias. The fllwing frmula can be used t set the threshld: 0.8V *R 0.9*V -0.8V R 2 ut --( 9) Where: 0.8V is reference f the internal cmparatr 0.9*Vut is selectable threshld fr pwer gd, fr this design it is.62v. Select R 0KOhm Using (8): R 2.06KOhm Select R 2.09K Use a pull up resistr (4.99K) frm PGd pin t Vcc. /04/08 6
Typical Applicatin fr IR820A 2V t.8v @ 4A PD-600 ig.6: Typical Applicatin circuit fr 2V t.8v at 4A using ceramic utput capacitrs /04/08 7
PD-600 PCB Metal and Cmpnents Placement The lead lands (the IC pins) width shuld be equal t the nminal part lead width. The minimum lead-t-lead spacing shuld be 0.2mm t minimize shrting. Lead land length shuld be equal t the maximum part lead length + 0. mm utbard extensin. The utbard extensin ensures a large and inspectable te fillet. The pad lands (the 4 big pads ther than the IC pins) length and width shuld be equal t maximum part pad length and width. Hwever, the minimum metal-t-metal spacing shuld be n less than 0.7mm fr 2 z. Cpper; n less than 0.mm fr z. Cpper and n less than 0.2mm fr z. Cpper. /04/08 8
PD-600 Slder Resist It is recmmended that the lead lands are Nn Slder Mask Defined (NSMD). The slder resist shuld be pulled away frm the metal lead lands by a minimum f 0.025mm t ensure NSMD pads. The land pad shuld be Slder Mask Defined (SMD), with a minimum verlap f the slder resist nt the cpper f 0.05mm t accmmdate slder resist mis-alignment. Ensure that the slder resist in between the lead lands and the pad land is 0.5mm due t the high aspect rati f the slder resist strip separating the lead lands frm the pad land. /04/08 9
Stencil Design PD-600 The Stencil apertures fr the lead lands shuld be apprximately 80% f the area f the lead lads. Reducing the amunt f slder depsited will minimize the ccurrences f lead shrts. If t much slder is depsited n the center pad the part will flat and the lead lands will be pen. The maximum length and width f the land pad stencil aperture shuld be equal t the slder resist pening minus an annular 0.2mm pull back t decrease the incidence f shrting the center land t the lead lands when the part is pushed int the slder paste. /04/08 20
PD-600 IR WORLD HEADQUARTERS: 2 Kansas St., El Segund, Califrnia 90245, USA Tel: (0) 252-705 TAC ax: (0) 252-790 This prduct has been designed and qualified fr the Cnsumer market. Visit us at www.irf.cm fr sales cntact infrmatin Data and specificatins subject t change withut ntice. 0/07 /04/08 2