MOTOROLA nc. SEMICONDUCTOR TECHNICAL DATA Order this document by /D The Wideband IC Line RF LDMOS Wideband Integrated Power Amplifier The wideband integrated circuit is designed for base station applications. It uses Motorola s newest High Voltage (26 to 28 Volts) LDMOS IC technology and integrates a multi-stage structure. Its wideband On-Chip matching design makes it usable from 600 to 2600 MHz. The linearity performances cover W- CDMA modulation formats. Final Application Typical W-CDMA Performance: -45 dbc ACPR, 20-270 MHz, V DD = 27 Volts, I DQ = 56 ma, I DQ2 = 6 ma, I DQ3 = 7 ma, P out = 34 dbm, 3GPP Test Model, Measured in a.0 MHz BW @ 4 MHz offset, 64 DTCH Power Gain 30 db PAE = 6% Driver Application Typical W-CDMA Performance: -53 dbc ACPR, 20-270 MHz, V DD = 26 Volts,, P out = 23 dbm, 3GPP Test Model, Measured in a 3.84 MHz BW @ 5 MHz offset, 64 DTCH Power Gain 34 db Gain Flatness = 0.3 db from 20-270 MHz PdB = 5 Watts, Gain Flatness = 0.2 db from 20-270 MHz Capable of Handling 3: VSWR, @ 26 Vdc, 240 MHz, 5 Watts CW Output Power Characterized with Series Equivalent Large- Signal Impedance Parameters On-Chip Matching (50 Ohm Input, DC Blocked, >5 Ohm Output) Integrated Temperature Compensation with Enable/Disable Function Integrated ESD Protection In Tape and Reel. R2 Suffix =,500 Units per 6 mm, 3 inch Reel. MAXIMUM RATINGS 270 MHz, 26 V, 23/34 dbm W- CDMA RF LDMOS WIDEBAND INTEGRATED POWER AMPLIFIER CASE 978-03 PFP -6 Rating Symbol Value Unit Drain-Source Voltage V DSS 65 Vdc Gate-Source Voltage V GS -0.5, 5 Vdc Storage Temperature Range T stg - 65 to 50 C Operating Junction Temperature T J 50 C V GS3 V GS2 V GS RF in I C V DS V DS2 Quiescent Current Temperature Compensation 3 Stages I C N.C. V GS3 V GS2 V GS RF in RF in V DS V DS2 PIN CONNECTIONS 2 3 4 5 6 7 8 6 5 4 3 2 0 9 N.C. N.C. (Top View) NOTE: Exposed backside flag is source terminal for transistors. () Refer to AN987/D, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.motorola.com/semiconductors/rf. Select Documentation/Application Notes - AN987. Rev. Motorola, MOTOROLA Inc. 2004 RF DEVICE DATA
nc. THERMAL CHARACTERISTICS Characteristic Symbol Value Unit Thermal Resistance, Junction to Case R θjc C/W Driver Application Stage, 26 Vdc, I DQ = 96 ma (P out = 0.2 W CW) Stage 2, 26 Vdc, I DQ = 204 ma Stage 3, 26 Vdc, I DQ = ma 3.5 Output Application Stage, 27 Vdc, I DQ = 56 ma (P out = 2.5 W CW) Stage 2, 27 Vdc, I DQ = 6 ma Stage 3, 27 Vdc, I DQ = 7 ma ESD PROTECTION CHARACTERISTICS Human Body Model Machine Model Charge Device Model MOISTURE SENSITIVITY LEVEL Test Conditions Test Methodology 2.7 Class (Minimum) M (Minimum) C2 (Minimum) Per JESD 22-A3 3 Rating ELECTRICAL CHARACTERISTICS (T C = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit W-CDMA CHARACTERISTICS (In Motorola Test Fixture, 50 ohm system) V DD = 26 Vdc,, P out = 23 dbm, 20-270 MHz Power Gain G ps 3 34 db Gain Flatness G F 0.3 0.5 db Input Return Loss IRL -2-0 db Group Delay.7 ns Phase Linearity 0.2 -Carrier W-CDMA Conditions: Adjacent Channel Power Ratio @ P out = 23 dbm, 5 MHz Offset -Carrier W-CDMA Conditions: Adjacent Channel Power Ratio @ P out = 28 dbm, 5 MHz Offset ACPR -53-50 dbc ACPR -50 dbc W-CDMA CHARACTERISTICS (In Motorola Test Fixture, 50 ohm system) V DD = 27 Vdc, I DQ = 56 ma, I DQ2 = 6 ma, I DQ3 = 7 ma, P out = 34 dbm, 20-270 MHz Power Gain G ps 30 db Gain Flatness G F 0.2 db Input Return Loss IRL -2 db Power Added Efficiency PAE 6 % -Carrier W-CDMA Conditions: Adjacent Channel Power Ratio @ P out = 34 dbm, 4 MHz Offset ACPR -45 dbc 2
nc. 6 V bias3 V bias2 V bias RF INPUT R3 R2 R C C5 C4 C2 C3 C4 2 3 4 5 5 4 3 2 C5 C6 C9 RF OUTPUT V D V D2 6 V D3 7 0 C2 C3 C8 C2 C7 C C6 C0 8 Quiescent Current Temperature Compensation 9 C7 C8 C9 C20 C, C5, C8, C2, C4, C9 µf SMT Tantalum Chip Capacitors C2, C3, C4, C7, C, C8 0.0 µf Chip Capacitors (0805C03K5RACTR) C6, C0, C7 6.8 pf Chip Capacitors, ACCU P (AVX 0805J6R8BBT) C9, C5, C6.8 pf Chip Capacitors, ACCU P (AVX 0805JR8BBT) C4 C4 V G C6 Figure. Demo Board Schematic V bias V bias2 V bias3 R R2 R3 C5 V G2 V G3 C3 C2 C5 C6 C9 C C3, C20, C2 330 µf Electrolytic Capacitors (MCR35V337M0X6) R, R2, R3 kω Chip Resistors (0805) PCB Arlon, 0.020, ε r = 2.55 V GS Rev C0 C7 C7 C8 C8 C C2 C9 C2 V DD C3 V DD2 C20 V DD3 Figure 2. Demo Board Component Layout 3
nc. TYPICAL CHARACTERISTICS 50 0.8 S2 (db) 40 S2 5 30 0 20 S 5 0 20 0 25 0 V DD = 27 Vdc, P out = 23 dbm CW 30 20 35 000 200 400 600 800 2000 2200 2400 2600 2800 3000 f, FEQUENCY (MHz) Figure 3. Broadband Frequency Response S (db) DELAY, (nsec).6.4.2 0.8 0.6 0.4 0.2 0 200 T C = 85 C 25 C 30 C V DD = 27 Vdc, P out = 23 dbm CW 20 220 230 240 250 260 270 280 f, FREQUENCY (MHz) Figure 4. Delay versus Frequency G ps, POWER GAIN (db) G ps, POWER GAIN (db) 40 39 38 T C = 30 C 37 36 25 C 35 34 85 C 33 32 V DD = 27 Vdc, P out = 23 dbm CW 3 30 200 20 220 230 240 250 260 270 280 f, FREQUENCY (MHz) Figure 5. Power Gain versus Frequency 40 39 38 T C = 30 C 37 36 25 C 35 34 85 C 33 32 V DD = 27 Vdc, f = 240 MHz 3 30 20 25 30 35 40 45 P out, OUTPUT POWER (dbm) INPUT RETURN LOSS (db) IRL, S2 PHASE( ) 20 5 0 5 T C = 85 C 25 C 30 C V DD = 27 Vdc, P out = 23 dbm CW 0 200 20 220 230 240 250 260 270 70 65 60 55 50 f, FREQUENCY, (MHz) Figure 6. Input Return Loss versus Frequency T C = 25 C 30 C 280 85 C 45 V DD = 27 Vdc, f = 240 MHz 40 20 25 30 35 40 45 P out, OUTPUT POWER (dbm) Figure 7. Power Gain versus Output Power Figure 8. S2 Phase versus Output Power 4
nc. TYPICAL CHARACTERISTICS ACPR, ADJACENT CHANNEL POWER RATIO (dbc) 40 42 44 46 48 50 52 54 56 58 60 5 V DD = 27 Vdc 3GPP Test Model 64 DPCH 270 MHz 20 MHz P out, OUTPUT POWER (dbm) 240 MHz 7 9 2 23 25 27 29 3 33 35 IMR (dbc) 40 45 50 55 60 65 70 2000 V DD = 27 Vdc P out = 23 dbm Two Tone Avg. Tone Spacing = 00 khz 3rd Order 5th Order 2050 200 ma 250 22 ma f, FREQUENCY (MHz) 2200 I DQ3 = 00 ma 2250 22 ma 00 ma 2300 Figure 9. W-CDMA ACPR versus Output Power Figure 0. Two- Tone IMR versus Frequency INTERMODULATION DISTORTION (dbc) IMD, 50 6.00 52 5.75 V BIAS 5.50 54 3rd Order 5.25 V BIAS2 56 5.00 58 V DD = 27 Vdc 4.75 V DD = 27 Vdc, f = 240 R = R2 = R3 = 000 Ohms 60 4.50 P out = 23 dbm, Two Tone Avg. V BIAS3 62 4.25 64 5th Order 4.00 66 3.75 3.50 68 3.25 70 3.00 0 5 0 5 20 25 40 30 20 0 0 0 20 30 40 50 60 70 80 90 00 TONE SPACING (MHz) Figure. Two- Tone Broadband Performance T, TEMPERATURE (C) Figure 2. Fixture Bias versus Temperature V gs, IC GATE BIAS VOLTAGE (V) 4.20 4.0.80 4.00.60 3.90 V gs & V gs2 I gs & I gs2.40 3.80.20 V DD = 27 Vdc 3.70 R = R2 = R3 = 000 Ohms.00 V 3.60 gs3 0.80 3.50 0.60 3.40 0.40 3.30 I gs3 0.20 3.20 0.00 40 30 20 0 0 0 20 30 40 50 60 70 80 90 00 T, TEMPERATURE (C) Figure 3. Gate Bias versus Temperature V bias, FIXTURE BIAS VOLTAGE (V) 2.00 I gs, GATE BIAS CURRENT (ma) 5
nc. f = 270 MHz Z load f = 20 MHz f MHz 20 240 270 Z o = 50 Ω V DD = 27 Vdc, I DQ = 4 ma, P out = 5 W Avg. Z in Ω 72.55 j2.8 7.40 j9.9 70.20 j7. Z load Ω 4.25 j.00 4.3 j.37 4.2 j.46 Z in = Device input impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. Z in f = 20 MHz f = 270 MHz Device Under Test Output Matching Network Z in Z load Figure 4. Series Equivalent Input and Load Impedance 6
nc. NOTES 7
nc. PACKAGE DIMENSIONS h X 45 A E2 4 x e A e/2 A2 Y 8 E 8X E bbb M ccc C C B S 6 9 L B C D DATUM H PLANE SEATING PLANE L.000 0.039 W W DETAIL Y A BOTTOM VIEW GAUGE PLANE c b ÇÇ ÇÇ b aaa M C SECT W-W CASE 978-03 ISSUE B PFP- 6 A c S D NOTES:. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y4.5M, 994. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS D AND E DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION IS 0.27 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. MILLIMETERS DIM MIN MAX A 2.000 2.300 A 0.025 0.00 A2.950 2.00 D 6.950 7.00 D 4.372 5.80 E 8.850 9.50 E 6.950 7.00 E2 4.372 5.80 L 0.466 0.720 L 0.250 BSC b 0.300 0.432 b 0.300 0.375 c 0.80 0.279 c 0.80 0.230 e 0.800 BSC h 0.600 0 7 aaa 0.200 bbb 0.200 ccc 0.00 Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, Motorola Literature Distribution 3-20-, Minami-Azabu, Minato-ku, Tokyo 06-8573, Japan P.O. Box 5405, Denver, Colorado 8027 8-3-3440-3569 -800-52-6274 or 480-768-230 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors 8 /D