ELECTRICAL CHARACTERISTICS ( unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Cpk 2.) (Note ) (V GS =, I D =.2 madc) Temperature Coefficient (Positive) (BR)DSS 8 mv/ C Zero Gate Voltage Drain Current (V DS =, V GS = ) (V DS =, V GS =, T J = C) GateBody Leakage Current (V GS = ±, V DS = ) I GSS nadc ON CHARACTERISTICS (Note ) Gate Threshold Voltage (Cpk 2.) (Note ) (V DS = V GS, I D = 2 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Cpk.) (Note ) (V GS =, I D =. Adc) DraintoSource OnVoltage (V GS =, I D = 2 Adc) (V GS =, I D =. Adc, T J = C) I DSS V GS(th) 2. 2.8.. R DS(on).8.2 V DS(on) Forward Transconductance (V DS =, I D =. Adc) g FS.. mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (V DS = 2, V GS =, f =. MHz) C oss 2 28 Reverse Transfer Capacitance C rss SWITCHING CHARACTERISTICS (Note 2) TurnOn Delay Time t d(on) ns 2. 2. Adc mv/ C C iss 7 pf Rise Time (V DD =, I D = 2 Adc, t r TurnOff Delay Time V GS =, R G =. ) t d(off) 2 Fall Time t f 8 Gate Charge (V DS = 8, I D = 2 Adc, V GS = ) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note ) (I S = 2 Adc, V GS = ) (I S = 2 Adc, V GS =, T J = C) Reverse Recovery Time (I S = 2 Adc, V GS =, di S /dt = A/ s) Q T nc Q. Q 2. Q 7. V SD.8.. t rr ns t a t b 2 Reverse Recovery Stored Charge Q RR. C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead.2 from package to center of die) L D. nh Internal Source Inductance (Measured from the source lead.2 from package to source bond pad). Pulse Test: Pulse Width s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature.. Reflects typical values. Max limit Typ Cpk = x SIGMA L S 7. nh 2
TYPICAL ELECTRICAL CHARACTERISTICS 2 2 2 V V DS V GS = V T J = C V 8 V 2 7 V V V 2 C 8 2 C 2 7 8 V DS, DRAINTOSOURCE VOLTAGE (VOLTS) Figure. OnRegion Characteristics 2 7 8 V GS, GATETOSOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics R DS(on), DRAINTOSOURCE RESISTANCE (OHMS). V GS = V.. T J = C.2 2 C.2. C.. R DS(on), DRAINTOSOURCE RESISTANCE (OHMS).2.22 V GS = V.2.7. V.2..7. 2 8 2 2 2 8 2 2 Figure. OnResistance versus Drain Current and Temperature Figure. OnResistance versus Drain Current and Gate Voltage R DS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 2..8..2..8. V GS = V I D = A 2 2 7 2 T J, JUNCTION TEMPERATURE ( C) IDSS, LEAKAGE (na) V GS = V. T J = 2 C..2 7 C 2 V DS, DRAINTOSOURCE VOLTAGE (VOLTS) Figure. OnResistance Variation with Temperature Figure. DrainToSource Leakage Current versus Voltage
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I G(AV) ) can be made from a rudimentary analysis of the drive circuit so that t = Q/I G(AV) During the rise and fall time interval when switching a resistive load, V GS remains virtually constant at a level known as the plateau voltage, V SGP. Therefore, rise and fall times may be approximated by the following: t r = Q 2 x R G /(V GG V GSP ) t f = Q 2 x R G /V GSP where V GG = the gate drive voltage, which varies from zero to V GG R G = the gate drive resistance and Q 2 and V GSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: t d(on) = R G C iss In [V GG /(V GG V GSP )] t d(off) = R G C iss In (V GG /V GSP ) The capacitance (C iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure ) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. C, CAPACITANCE (pf) 8 V DS = V V GS = V C iss 2 C rss 8 C iss C oss 2 C rss 2 2 V GS V DS GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation
V GS, GATETOSOURCE VOLTAGE (VOLTS) 8 7 2 Q Q2 QT V GS I D = 2 A Q DS 2 8 2 8 2 Q T, TOTAL CHARGE (nc) 27 2 2 8 2 V DS, DRAINTOSOURCE VOLTAGE (VOLTS) t, TIME (ns) V DD = V I D = 2 A V GS = V t r t f t d(off) t d(on) R G, GATE RESISTANCE (OHMS) Figure 8. GateToSource and DrainToSource Voltage versus Total Charge Figure. Resistive Switching Time Variation versus Gate Resistance DRAINTOSOURCE DIODE CHARACTERISTICS, SOURCE CURRENT (AMPS) IS 2 8 7 2 V GS = V..7.....7. V SD, SOURCETODRAIN VOLTAGE (VOLTS) Figure. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 2 C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded and the transition time (t r,t f ) do not exceed s. In addition the total power averaged over a complete switching cycle must not exceed (T J(MAX) T C )/(R JC ). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (I DM ), the energy rating is specified at rated continuous current (I D ), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure ). Maximum energy at currents below rated continuous I D can safely be assumed to equal the values indicated.
SAFE OPERATING AREA I D, DRAIN CURRENT (AMPS). V GS = V SINGLE PULSE T C = 2 C s ms ms dc R DS(on) LIMIT THERMAL LIMIT 2 PACKAGE LIMIT... 2 7 2 V DS, DRAINTOSOURCE VOLTAGE (VOLTS) T J, STARTING JUNCTION TEMPERATURE ( C) E AS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mj) 22 2 7 2 7 I D = 2 A 7 Figure. Maximum Rated Forward Biased Safe Operating Area Figure 2. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. D =..2...2. SINGLE PULSE P (pk) R JC (t) = r(t) R JC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T J(pk) T C = P (pk) R JC (t) t 2 DUTY CYCLE, D = t /t 2..E.E.E.E2.E.E+.E+ t, TIME (s) Figure. Thermal Response di/dt I S t rr t a t b TIME t p.2 I S I S Figure. Diode Reverse Recovery Waveform
PACKAGE DIMENSIONS TO22 CASE 22A ISSUE AB H Q Z L V G B 2 N D A K F T U S R J C T SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 82. 2. CONTROLLING DIMENSION: INCH.. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. INCHES MILLIMETERS DIM MIN MAX MIN MAX A.7.2.8.7 B.8...28 C...7.82 D.2...88 F.2.7..7 G.. 2.2 2. H.. 2.8. J.8.2.. K..2 2.7.27 L....2 N..2.8. Q..2 2.. R.8. 2. 2.7 S.2..8. T.2.2.7.7 U....27 V.. Z.8 2. STYLE : PIN. GATE 2. DRAIN. SOURCE. DRAIN EFET is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 827 USA Phone: 727 or 88 Toll Free USA/Canada Fax: 727 or 887 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 82828 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 2 7 2 Japan Customer Focus Center Phone: 8778 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MTP2V/D