Introduction to igital Prof Nizamettin IN naydin@yildizedutr naydin@ieeeorg ourse Outline igital omputers, Number Systems, rithmetic Operations, ecimal, lphanumeric, and Gray odes 2 inary, Gates, oolean lgebra, Standard orms 3 ircuit Optimization, Two-Level Optimization, Map Manipulation, Multi-Level ircuit Optimization 4 dditional Gates and ircuits, Other Gate Types, xclusive-or Operator and Gates, igh-impedance Outputs 5 Implementation Technology and esign, esign oncepts and utomation, The esign Space, esign Procedure, The major design steps 6 Programmable Implementation Technologies: Read-Only Memories, Programmable rrays, Programmable rray,technology mapping to programmable logic devices 7 ombinational unctions and ircuits 8 rithmetic unctions and ircuits 9 Sequential ircuits Storage lements and Sequential ircuit nalysis 0 Sequential ircuits, Sequential ircuit esign State iagrams, State Tables ounters, register cells, buses, & serial operations 2 Sequencing and ontrol, atapath and ontrol, lgorithmic State Machines (SM) 3 Memory asics 2 Introduction to igital Lecture 5 Implementation Technology and esign esign oncepts and utomation undamental concepts of design and computer-aided design techniques The esign Space Technology parameters for gates, positive and negative logic and design tradeoffs esign Procedure The major design steps: specification, formulation, optimization, technology mapping, and verification Technology Mapping rom N, OR, and NOT to other gate types Verification oes the designed circuit meet the specifications? ombinational ircuits combinational logic circuit has: set of m oolean inputs, set of n oolean outputs, and n switching s, each mapping the 2 m input combinations to an output such that the current output depends only on the current input values block diagram: m oolean Inputs ombinatorial ircuit n oolean Outputs 3 4 ierarchical esign ierarchy for Parity Tree xample 0 To control the complexity of the mapping inputs to outputs: ecompose the into smaller pieces called blocks ecompose each block s into smaller blocks, repeating as necessary until all blocks are small enough ny block not decomposed is called a primitive block The collection of all blocks including the decomposed ones is a hierarchy xample: 9-input parity tree (see next slide) Top Level: 9 inputs, one output 2nd Level: our 3-bit odd parity trees in two levels 3rd Level: Two 2-bit exclusive-or s Primitives: our 2-input NN gates esign requires 4 2 4 = 32 2-input NN gates 0 2 2 3 4 5 6 7 8 9-Input odd O (a) Symbol for circuit 0 2 3 4 5 6 7 8 (c) 3-input odd circuit as interconnected exclusive-or blocks 0 3-Input odd O 2 0 3-Input 0 3-Input odd O odd O 2 2 0 3-Input odd O 2 (b) ircuit as interconnected 3-input odd blocks O O (d) xclusive-or block as interconnected NNs 5 6 opyright 2000 N IN ll rights reserved
Reusable unctions and Top-own versus ottom-up henever possible, we try to decompose a complex design into common, reusable blocks These blocks are verified and well-documented placed in libraries for future use Representative omputer-ided esign Tools: Schematic apture Simulators Timing Verifiers ardware escription Languages Verilog and VL Synthesizers Integrated ircuit Layout top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement bottom-up design starts with detailed primitive blocks and combines them into larger and more complex al blocks esigns usually proceed from both directions simultaneously Top-down design answers: hat are we building? ottom-up design answers: ow do we build it? Top-down controls complexity while bottom-up focuses on the details 7 8 Integrated ircuits Integrated circuit (informally, a chip ) is a semiconductor crystal (most often silicon) containing the electronic components for the digital gates and storage elements which are interconnected on the chip Terminology - Levels of chip integration SSI (small-scale integrated) - fewer than 0 gates MSI (medium-scale integrated) - 0 to 00 gates LSI (large-scale integrated) - 00 to thousands of gates VLSI (very large-scale integrated) - thousands to 00s of millions of gates Technology Parameters Specific gate implementation technologies are characterized by the following parameters: an-in the number of inputs available on a gate an-out the number of standard loads driven by a gate output Levels the signal value ranges for and 0 on the inputs and and 0 on the outputs (see igure -) Noise Margin the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output ost for a gate - a measure of the contribution by the gate to the cost of the integrated circuit Propagation elay The time required for a change in the value of a signal to propagate from an input to an output Power issipation the amount of power drawn from the power supply and consumed by the gate 9 0 Propagation elay Propagation delay is the time for a change on an input of a gate to propagate to the output elay is usually measured at the 50% point with respect to the and L output voltage levels igh-to-low (t PL ) and low-to-high (t PL ) output signal changes may have different propagation delays igh-to-low (L) and low-to-high (L) transitions are defined with respect to the output, not the input n L input transition causes: an L output transition if the gate inverts and an L output transition if the gate does not invert IN Propagation elay (continued) OUT IN OUT t PL t PL t pd 5 max (t PL, t PL) Propagation delays measured at the midpoint between the L and values hat is the expression for the t PL delay for: a string of n identical buffers? a string of n identical inverters? 2 opyright 2000 N IN ll rights reserved 2
Propagation elay xample ind t PL, t PL and t pd for the signals given OUT (volts) IN (volts) 0 ns per division t (ns) elay Models Transport delay - a change in the output in response to a change on the inputs occurs after a fixed specified delay Inertial delay - similar to transport delay, except that if the input changes such that the output is to change twice in a time interval less than the rejection time, the output changes do not occur Models typical electronic circuit behavior, namely, rejects narrow pulses on the outputs 3 4 : No elay (N) Transport elay (T) Inertial elay (I) elay Model xample a b c d e 0 2 4 6 8 0 2 4 6 Time (ns) Propagation elay = 20 ns Rejection Time = 0 ns an-out an-out can be defined in terms of a standard load xample: standard load equals the load contributed by the input of inverter Transition time -the time required for the gate output to change from to L, t L, or from L to, t L The maximum fan-out that can be driven by a gate is the number of standard loads the gate can drive without exceeding its specified maximum transition time 5 6 an-out and elay The fan-out loading a gate s output affects the gate s propagation delay xample: One realistic equation for t pd for a NN gate with 4 inputs is: t pd = 007 + 002 SL ns SL is the number of standard loads the gate is driving, i e, its fan-out in standard loads or SL = 45, t pd = 065 ns ost In an integrated circuit: The cost of a gate is proportional to the chip area occupied by the gate The gate area is roughly proportional to the number and size of the transistors and the amount of wiring connecting them Ignoring the wiring area, the gate area is roughly proportional to the gate input count So gate input count is a rough measure of gate cost If the actual chip layout area occupied by the gate is known, it is a far more accurate measure 7 8 opyright 2000 N IN ll rights reserved 3
Positive and Negative The same physical gate has different logical meanings depending on interpretation of the signal levels Positive IG (more positive) signal levels represent LO (less positive) signal levels represent 0 Negative LO (more negative) signal levels represent IG (less negative) signal levels represent 0 gate that implements a Positive N will implement a Negative OR, and vice-versa Positive and Negative (continued) Given this signal level table: Input L L L L hat logic is implemented? Positive ( = ) (L = 0) Negative Output L ( = 0) (L = ) 0 0 0 0 0 0 0 0 0 0 0 0 9 20 Positive and Negative (continued) Rearranging the negative logic terms to the standard table order: Positive ( = ) (L = 0) Negative ( = 0) (L = ) 0 0 0 0 0 0 0 0 0 0 0 0 Symbol onventions Use of polarity indicator to represent use of negative logic convention on gate inputs or outputs KT ircuit L L L L L Positive Negative 2 22 esign Trade-Offs ost - performance tradeoffs Gate-Level xample: NN gate G with 20 standard loads on its output has a delay of 045 ns and has a normalized cost of 20 buffer has a normalized cost of 5 The NN gate driving the buffer with 20 standard loads gives a total delay of 033 ns In which if the following cases should the buffer be added? The cost of this portion of the circuit cannot be more than 25 2 The delay of this portion of the circuit cannot be more than 040 ns 3 The delay of this portion of the circuit must be less than 030 ns and the cost less than 30 Tradeoffs can also be accomplished much higher in the design hierarchy onstraints on cost and performance have a major role in making tradeoffs esign Procedure Specification rite a specification for the circuit if one is not already available 2 ormulation erive a truth table or initial oolean equations that define the required relationships between the inputs and outputs, if not in the specification 3 Optimization pply 2-level and multiple-level optimization raw a logic diagram or provide a netlist for the resulting circuit using Ns, ORs, and inverters 23 24 opyright 2000 N IN ll rights reserved 4
esign Procedure esign xample 4 Technology Mapping Map the logic diagram or netlist to the implementation technology selected 5 Verification Verify the correctness of the final design 25 Specification to xcess-3 code converter Transforms code for the decimal digits to xcess-3 code for the decimal digits code words for digits 0 through 9: 4-bit patterns 0000 to 00, respectively xcess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 00) added to each code word Implementation: multiple-level circuit NN gates (including inverters) 26 esign xample (continued) 2 ormulation onversion of 4-bit codes can be most easily formulated by a truth table Variables - :,,, Variables - xcess-3,,, on t ares - 00 to Input 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output xcess 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 esign xample (continued) 3 Optimization a 2-level using K-maps = + + = + + = + = 0 3 2 4 5 7 6 2 3 5 4 8 9 0 0 3 2 4 5 7 6 2 3 5 4 8 9 0 0 3 2 4 5 7 6 2 3 5 4 8 9 0 0 3 2 4 5 7 6 2 3 5 4 8 9 0 28 esign xample (continued) esign xample (continued) 3 Optimization (continued) b Multiple-level using transformations = + + = + + = + = G = 7 + 0 + 6 + 0 = 23 Perform extraction, finding factor: T = + = + T = T + = + = G = 2 + + 4 + 7 + 6 + 0 = 20 29 3 Optimization (continued) b Multiple-level using transformations T = + = + T = T + = + = G = 20 n additional extraction not shown in the text since it uses a oolean transformation: ( = + = T ): = + T = T + T = + T = G = 2 + + 4 + 6 + 4 + 0 = 7 30 opyright 2000 N IN ll rights reserved 5
esign xample (continued) 4 Technology Mapping Mapping with a library containing inverters and 2-input NN, 2-input NOR, and 2-2 OI gates Technology Mapping hip design styles ells and cell libraries Mapping Techniques NN gates NOR gates Multiple gate types Programmable logic devices 3 32 hip esign Styles ull custom - the entire design of the chip down to the smallest detail of the layout is performed xpensive Justifiable only for dense, fast chips with high sales volume Standard cell - blocks have been design ahead of time or as part of previous designs Intermediate cost Less density and speed compared to full custom Gate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections between gates are specific to a design Lowest cost Less density compared to full custom and standard cell ell Libraries ell - a pre-designed primitive block ell library - a collection of cells available for design using a particular implementation technology ell characterization - a detailed specification of a cell for use by a designer - often based on actual cell design and fabrication and measured values ells are used for gate array, standard cell, and in some cases, full custom chip design 33 34 Typical ell haracterization omponents xample ell Library Schematic or logic diagram rea of cell Often normalized to the area of a common, small cell such as an inverter Input loading (in standard loads) presented to outputs driving each of the inputs elays from each input to each output One or more cell templates for technology mapping One or more hardware description language models If automatic layout is to be used: Physical layout of the cell circuit floorplan layout providing the location of inputs, outputs, power and ground connections on the cell Typical Typical Input-to- ell ell Normalized Input Output Name Schematic rea Load elay 004 Inverter 00 00 002 3 SL 005 2NN 25 00 004 3 SL 006 2NOR 25 00 008 3 SL 007 2-2 OI 225 095 009 3 SL asic unction Templates 35 36 opyright 2000 N IN ll rights reserved 6
Mapping to NN gates ssumptions: Gate loading and delay are ignored ell library contains an inverter and n-input NN gates, n = 2, 3, n N, OR, inverter schematic for the circuit is available The mapping is accomplished by: Replacing N and OR symbols, Pushing inverters through circuit fan-out points, and anceling inverter pairs NN Mapping lgorithm Replace Ns and ORs: 2 Repeat the following pair of actions until there is at most one inverter between : a circuit input or driving NN gate output, and b The attached NN gate inputs 37 38 NN Mapping xample Mapping to NOR gates 5 7 (a) 5 6 7 8 5 6 OI 2 4 3 9 (b) ssumptions: Gate loading and delay are ignored ell library contains an inverter and n-input NOR gates, n = 2, 3, n N, OR, inverter schematic for the circuit is available The mapping is accomplished by: Replacing N and OR symbols, Pushing inverters through circuit fan-out points, and anceling inverter pairs (c) (d) 39 40 NOR Mapping lgorithm NOR Mapping xample Replace Ns and ORs: 2 Repeat the following pair of actions until there is at most one inverter between : a circuit input or driving NN gate output, and b The attached NN gate inputs (a) (c) (b) 3 2 4 42 opyright 2000 N IN ll rights reserved 7
Mapping Multiple Gate Types Mapping Multiple Gate Types lgorithm is available in the dvanced Technology Mapping reading supplement ell library contains gates of more than one type oncept Set Steps Replace all N and OR gates with optimum equivalent circuits consisting only of 2-input NN gates and inverters Place two inverters in series in each line in the circuit containing NO inverters Justification reaks up the circuit into small standardize pieces to permit maximum flexibility in the mapping process or the equivalent circuits, could use any simple gate set that can implement N, OR and NOT and all of the cells in the cell library oncept Set 2 an-out free subcircuit - a circuit in which a single output cell drives only one other cell Steps Use an algorithm that guarantees an optimum solution for fan-out free subcircuits by replacing interconnected inverters and 2-input NN gates with cells from the library Perform inverter canceling and pushing as for the NN and NOR Justification Steps given optimize the total cost of the cells used within fanout free subcircuits of the circuit nd result: n optimum mapping solution within the fan-out free subcircuits 43 44 xample: Mapping Multiple ell Types xample: Mapping Multiple Gate Types Uses same example circuit as NN mapping and NOR mapping ell library: 2-input and 3-input NN gates, 2-input NOR gate, and inverter ircuits on next slide (a) Optimized multiple-level circuit (b) ircuit with N and OR gates replaced with circuits of 2- input NN gates and inverters (Outlines show 2-input NNs and inverter sets mapped to library cells in next step) (c) Mapped circuit with inverter pairs cancelled (d) ircuit with remaining inverters minimized (a) (b) (c) (d) 45 46 Verification Verification - show that the final circuit designed implements the original specification Simple specifications are: truth tables oolean equations L code If the above result from formulation and are not the original specification, it is critical that the formulation process be flawless for the verification to be valid! asic Verification Methods Manual nalysis ind the truth table or oolean equations for the final circuit ompare the final circuit truth table with the specified truth table, or Show that the oolean equations for the final circuit are equal to the specified oolean equations Simulation Simulate the final circuit (or its netlist, possibly written as an L) and the specified truth table, equations, or L description using test input values that fully validate correctness The obvious test for a combinational circuit is application of all possible care input combinations from the specification 47 48 opyright 2000 N IN ll rights reserved 8
Verification xample: Manual nalysis -to-xcess 3 ode onverter ind the SOP oolean equations from the final circuit ind the truth table from these equations ompare to the formulation truth table inding the oolean quations: T = + = + = (T ) = + T = (T ) ( ) = T + = + = + Verification xample: Manual nalysis ind the circuit truth table from the equations and compare to specification truth table: Input Output xcess-3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The tables match! 49 50 Verification xample: Simulation Simulation procedure: Use a schematic editor or text editor to enter a gate level representation of the final circuit Use a waveform editor or text editor to enter a test consisting of a sequence of input combinations to be applied to the circuit This test should guarantee the correctness of the circuit if the simulated responses to it are correct Short of applying all possible care input combinations, generation of such a test can be difficult Verification xample: Simulation nter -to-xcess-3 ode onverter ircuit Schematic NN2 NOR2 NN2 NN3 N2 NOR2 NN2 NN2 OI symbol not available N2 OI 5 52 INPUTS Verification xample: Simulation nter waveform that applies all possible input combinations: 0 50 ns 00 ns re all input combinations present? (Low is a 0 and high is a one) Verification xample: Simulation Run the simulation of the circuit for 20 ns INPUTS OUTPUTS 0 50 ns 00 ns o the simulation output combinations match the original truth table? 53 54 opyright 2000 N IN ll rights reserved 9