Technology Development & Integration Challenges for Lead Free Implementation Vijay Wakharkar Assembly Technology Development Intel Corporation
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Environment Agenda Package Technology Challenges Intel Lead Free Symposium Synopsis 3
Environment
Computing + Communications Vision: Data Anytime, Anywhere Cellular: Voice + Data @ the Office Everywhere Else @ Hotspots 802.11 @ Home Broadband 10/100 10/100/GbE 802.11 802.11 Cellular 5
Convergence Driving New Innovations Any Time, Anywhere, Any Device Demand COMPUTING 1985 1990 COMMUNICATIONS 1995 Innovation 2000 2005 6
Technology Complexity Millimeter to Nanometer M1 M2 M3 M4 M5 Flash 0.16µm2 Flash Cell Die Die-package interconnection Via s Low K ILD Package substrate - um scale Cu interconnects Motherboard mm scale Package to MB interconnection 7
Packaging Complexity Die stacking, package stacking, and device integration all in one package. Complex packaging solutions require innovation. 8
Cost Challenges Packaging costs are becoming a bigger part of the total equation Silicon shrinks, 300 mm Technology.. Accelerated Time-to to-cost (faster HVM ramps) Significant Capital Investments in HVM Silicon Costs Yesterday Today Tomorrow Assembly Cost Silicon Costs Assembly Cost Aggressive Packaging Cost Reduction 9
Product Stewardship Environmental requirements driving technology shifts Legislation/ Recycling Laws Customer pull - green marketing Growing Safety Awareness Worldwide Key Issues Lead Free Halogen Free Impact to Materials / Supply chain Environmental Product Content Specification Effective Communication Environmental, Health & Safety screening guidelines 10
Lead Free First Level Interconnect Materials
First Level Interconnect Materials Low K Silicon Flip-Chip Bump SnPb Cu Other Silicon Stack - BLM Flux Materials Die Substrate UnderFill Materials Lead Free Assembly Materials, Process, Package Integration Substrate Surface Finish ENIG / EG / NG Surface Finish Substrate Bump SnPb SnAg Other
Solder Transition Die Die Substrate Leaded Substrate Lead Free Attribute Leaded Lead Free Next Gen Lead Free Die bump metallurgy 97Pb/3Sn Cu Advanced Bumps Substrate Solder 63Sn/37Pb LF Alloy Next Generation LF Alloy 13
Interconnect Solders Die Low k ILD failure Underfill Substrate Cu Bump Solder Paste during chip attach Significant reduction in Stress needed to integrate Low K Si and Lead-Free interconnect Solder electromigration during operation Robust electromigration resistance for Imax Lead Free poses significant new challenges. 14
Thermal Materials
Power Management Non Uniform Power dissipation is the challenge! Average power density is much lower than the peak power Challenges will continue with multi-core Power 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 4 Power Density S9 S17 7 10 13 16 19 S1 16
Improved Heat Spreading Silicon Temperature Package Temperature Ambient Temperature Packaging smoothes out Hot Spots Temperature Gradient Example : Intel Itanium Processor Example : Intel Pentium 4 Processor Integrated Integrated Heat Spreader 17
250 Solder Thermal Interface Material Cooling Capability [W] 200 150 100 50 0 Bare die PTIM STIM 2000 2002 2004 2008 2012 Heat Spreader Lid Pb-Free Solder TIM Lid Plating Back-Side Metal Thermal Interface Material (TIM) IHS (or Lid) Die Die Package Industry s First High Volume Solder Thermal Interface Material (STIM) Technology on Organic Packaging 18
Lead Free Second Level Interconnect Materials
Lead Free 2 nd LI Solder Joint Reliability Lead Free SJR (DROP( DROP) ) failure Typical SAC Alloy Failure Mode Interfacial fracture Typical Lead Free Alloy Leaded Typical Lead Free solder alloy exhibits significantly lower DROP DROP performance than Leaded 20
2 nd LI Lead Free Challenges Shrinking FF, multiple package designs Package & Board Design SRO Ball Pitch Ball Size Package/Board Stiffness induced solder joint strains BGA Solder Ball SAC 405/305 SAC 105 Advanced Ball Attach Flux Water Soluble No Clean Other Package Surface Finish ENIG EG OSP Advanced Package & Board Lead Free Assembly & Integration Board Attach Flux/Paste Water Soluble No Clean SAC 405/305 Paste Board Surface Finish OSP ImAg Advanced
Lead Free Drop Improvements Optimize Solder Alloys for Drop Increasing SAC Bulk compliance Lowering Ag content in SAC High Ag SAC Low Ag SAC SAC Solder Doping Cu content optimization in SAC High Ag SAC High Ag SAC Low Ag SAC Low Ag SAC 22
Process Challenges Liquidus Temp of solders (oc) 255 245 235 225 215 Assembly Process Window Shrinkage POR SMT Reflow window SAC405 SAC2510 SAC205 SAC1505 SAC110 SAC105 Alternative Lead Free Solder Alloys are typically offeutectic higher liquidus temperature larger spread in melting range 23
Platform Compatibility Challenges Leaded Components & Materials Lead Free Components & Materials Next Gen Lead Free Components & Materials 24
Intel Lead Free Symposium Synopsis
Intel Lead Free Symposium What: Two-Day Industry Forum, that began an open dialog on the challenges facing the electronic industry with respect to the conversion of Lead-Free Manufacturing Where: Scottsdale, AZ March 15 & 16 th, 2006 Who: Initially, industry leaders by invitation Open to anyone through sponsorship by IPC Over 170 attendees representing 76 different companies Why: To share learnings from our industry and to initiate Calls-for for-action on challenges that still remain as we have just BEGUN the transition to Pb-Free manufacturing 26
Intel Lead Free Symposium More on the why We are in this together no one company is solely responsible for the product that is delivered to the end- user. This is true for the OEM, ODM, EMS, Component Supplier and Materials Suppler. There is an entire supply chain. Thus, any one component, one unreliable solder joint, one lead- free traceability issue can prevent each of us from shipping product. We have just begun a significant transition to the electronics industry. We have been using eutectic solder for 50 years. Even at a 5:1 learning curve, it will take us a decade to achieve parity. The rate of learning is high, and we need to share across the entire supply line for both our individual company and industry success. 27
Intel Lead Free Symposium Lead-Free Current Situation Industry is converting products to Pb-free technology in a phased manner The convergence around SnAgCu family of solder alloys has enabled the initial Pb-free transition 12/04: EU approved exemption for Pb in flip-chip first level interconnect Challenges: Pb-free transition has created dual line items for each producer Impacts supply line and factory planning and traceability Multiple process recipes increase manufacturing complexity 28
Intel Lead Free Symposium Call to Action: Gain clarity of global legislation initiatives (EU / China / Japan / USA) Agreement on standards Alignment on interpretation of regulations Industry alignment on reliability assessment testing 80-90% of the testing is common, yet we are all driving to our own company requirements Industry collaboration to strengthen the alloy/ materials/process knowledge base to: Identify the overall best solution to meet performance targets Increase process & reliability margin Minimize impact to supply chain & customers 29
Intel Lead Free Symposium Pb-free implementation drives a number of technology challenges.. BGA Pb-Free alloy composition Ball attach flux optimization Pb-free surface finish and board assembly integration PCB Laminate crack/pad cratering Solder joint planar microvoids SLI solder joint reliability 30
inemi Role Gain industry knowledge in key areas such that an efficient working group can be spawned in a standards body in order to deliver a timely specification. Working Groups Kicking Off inemi to play a significant role in developing this industry knowledge! Please join / participate in this effort. 31