Development of a LFLE Double Pattern Process for TE Mode Photonic Devices Mycahya Eggleston Advisor: Dr. Stephen Preble
2 Introduction and Motivation Silicon Photonics Geometry, TE vs TM, Double Pattern vs Single Pattern
Silicon Photonics Geometry Effective index 3.4 Silicon 3.2 waveguide thickness TE0 TE1 3 TM0 TM1 2.8 that only a single TE and TM 2.6 mode are confined. 2.4 2.2 Waveguide Thickness vs. Effective Index and width are chosen such At 1550 nm wavelength: 2 1.8 Thickness 220 nm 1.6 Width 500 nm 1.4 0 50 100 150 200 250 300 350 400 450 500 Thickness [nm] EFFECTIVE INDEX 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 Waveguide Width vs. Effective Index TE0 TM0 TE1 TM1 Silicon Glass SiO2 Silicon Handle Wafer 1 150.00 350.00 550.00 750.00 950.00 WAVEGUIDE WIDTH [NM] 3 [1] S.Preble, Waveguides: Silicon Waveguides, MCEE-789/EEEE-789, Powerpoint, Spring 2165
TE Mode vs TM Mode 1 0.5 polarized mode(s) TE Mode E-Field (Log Scale) Energy Confined in Waveguide 4 Photonic devices take advantage of optical tunneling of the evanescent field to couple energy from one waveguide to another. E-Field Amplitude 0-0.5-1 1-600 -400-200 0 200 400 600 Position - perpendicular to wafer [nm] TM polarized Mode mode(s) E-Field (Log Scale) Evanescent Field Region TM Mode contains a larger amplitude evanescent field allowing coupling over larger distances E-Field Amplitude 0.5-0.5 0 Energy Confined in Waveguide Evanescent Field Region [1] S.Preble, Waveguides: Silicon Waveguides, MCEE-789/EEEE-789, Powerpoint, Spring 2165-1 -600-400 -200 0 200 400 600 Position - perpendicular to wafer [nm]
5 Double Pattern vs Single Pattern (Using i-line Lithography) TE Double ModePattern Minimum needed feature size feature possible: size: ~250 nm Minimum needed feature separation feature separation: possible: ~100 nm TM Single Mode Pattern Minimum needed feature size feature possible: size: ~400 ~300 nm Minimum needed feature separation feature separation: possible: ~300 nm
6 Process Development Proposed Litho-Freeze-Litho-Etch Process
Wafer Pre-processing Cleaning, BARC Application 7 Obtain SOI Wafer (2000 nm SiO 2 ) (220 nm a-si) RCA Clean Apply BARC (65 nm) BARC a-si a-si SiO2 Silicon RCA Clean SiO2 Silicon
8 Coat, Pattern, and Develop OiR-620 Positive Photoresist Image Apply Positive Resist (300 nm) Expose Resist Develop Positive Resist Positive Resist a-si Exposed Resist a-si a-si SiO2 Silicon SiO2 Silicon SiO2 Silicon
9 UV Cure of OiR-620 Positive Photoresist Image UV Cure Flood Expose o 250 nm Source o 140 C o 7 min 250nm UV Light Source a-si SiO2 Silicon Hotplate
10 Coat, Pattern, and Develop NLOF-2020 Negative Photoresist Image Apply Negative Resist (600 nm) Expose Resist Develop Negative Resist Negative Resist a-si Unexposed Resist a-si a-si SiO2 Silicon` SiO2 Silicon SiO2 Silicon
RIE Etch of BARC, ICP Etch of a-si, Photoresist Strip 11 BARC Etch a-si Etch Photoresist Strip RIE Plasma ICP Plasma O 2 Plasma Ash a-si a-si a-si a-si a-si SiO2 Silicon SiO2 Silicon SiO2 Silicon
Final Device Profile TE Mode Waveguide 12 220 nm a-si ~200 nm a-si 500 nm 2000 nm SiO2 Silicon
13 Process Development UV Cure DOE Impact of Exposure Time and Temperature on UV Cure Process
Experimental Setup 14 Study the effects of exposure time, exposure temperature, room temperature, and humidity on the area of cured photoresist remaining after processing of the second layer of photoresist Apply and develop OiR-620 photoresist without exposure UV cure the first layer Apply and develop NLOF-2020 photoresist without exposure Measure area of remaining OiR-620 photoresist SVG 88 Track UV Cure Setup
15 Design Matrix and Area of Cured Photoresist Exposure Temperature Area (cm 2 ) Area (cm 2 ) Area (cm 2 ) 46.94 2876.6 3093.4 131.40 2519.4 3119.0 Exposure Time 90.38 2506.6 3139.5 1148.10 2633.7 3598.6 993.80 3026.1 3198.1
16 Method of Analysis Least Squares Regression Examined three predictor variables: 1. Exposure Temperature (Continuous) 2. Exposure Time (Continuous) 3. Humidity (Continuous) Using one response variable 1. Area of cured photoresist in cm 2 Regression Model: Area = -1832 + 0.59*Time + 15.76*Temp 901.64*Humidity
17 Process Development Engineering Design Mask
Design Mask Overview 18 Photonic Design Variations: 1. Ring Grating Width Duty Ratio (space:line) 500 0.40nm 520 0.50nm 540 0.60nm 2. Waveguide to Width Ring Gap 500 150 nm 515 175 nm 530 200 nm 225 nm 250 nm
19 Experimental Results Initial Lithography Results
20 Compound Photoresist Image Positive Resist Positive Resist Negative Resist Positive Resist Negative Resist Negative Resist
Affect of Pitch and Duty Ratio on Photoresist Image 21 Duty Ratio (space:line) 0.40 Pitch (nm) 640 675 710 0.50 0.60
Affect of Pitch and Duty Ratio on Photoresist Image 22 Duty Ratio (space:line) 0.40 Pitch (nm) 745 780 815 0.50 0.60
Ring Resonator 23
24 Experimental Results Initial Etch Results
25 Grating Coupler Post Etch SEM 1.535 nm um 753.6 1.558 nm um 759.2 201.0 nm 150.7 nm
26 Ring Resonator Post Etch SEM 349.8 394.5 201.0 305.2 nm
27 Conclusions Conclusions Drawn from Final Results
28 Conclusions Obtained successful results from experimental process: Minimum obtained feature size ~150 nm Minimum obtained feature separation - ~100 nm Developed a working UV cure process using readily obtained positive and negative tone resists Developed a working LFLE process that can be refined to fabricate working TE mode photonic devices Created a two layer engineering design mask adequate for future work
29 Future Work Outline of Possible Future Work
30 Outline of Possible Future Work Lithography optimization for SOI wafer Account for changes in stack reflectivity Separate optimization for positive and negative layers Optical Proximity Correction (OPC) mask design Corrections for bulging in ring to wave guides gap Corrections for fine pitch grating couplers Etch Recipe Optimization for compound resist image
31 References Works Referenced
Works Referenced 32 [1] S.Preble, Waveguides: Silicon Waveguides, MCEE-789/EEEE-789, Powerpoint, Spring 2165 [2] M. Maenhoudt, Alternative process schemes for double patterning that eliminate the intermediate etch step, Proc. of SPIE Vol. 6924, 2008. [3] M. Hori, et al., Sub-40nm Half-Pitch Double Patterning with Resist Freezing Process, Proc. of SPIE Vol. 6923, 2008. [4] C. Shay, CD Reduction through Annular Illumination and Sidewall Spacer Etch, Senior Design, Rochester Institute of Technology, 2016. [5] P. Cadareanu, "Silicon Photonic Devices Manufactured Using Double- Patterned iline Lithography, Rochester Institute of Technology, 2016.