Avalanche Ruggedness of 800V Lateral IGBTs in Bulk Si

Avalanche Ruggedness of 800V Lateral IGBTs in Bulk Si Gianluca Camuso 1, Nishad Udugampola 2, Vasantha Pathirana 2, Tanya Trajkovic 2, Florin Udrea 1,2 1 University of Cambridge, Engineering Department Trumpington Street, CB2 1PZ Cambridge, United Kingdom +44 1223 748311 gc409@cam.ac.uk 2 Cambridge Microelectronics Ltd, 30 Brooke House, Kingsley Walk, Cambridge, CB5 8TJ Acknowledgements The authors would like to acknowledge the support from the UK Power Electronics Centre grant reference EP/L007010/1. Keywords «Power semiconductor device», «High voltage ICs», «IGBT», «Robustness», «Device simulation», «Measurement». Abstract Avalanche capability of 800V rated Lateral IGBTs (LIGBTs) fabricated using bulk CMOS technology has been investigated for the first time for both turn-on and turn-off. The LIGBTs have been designed for 65kHz operation in energy-efficient, compact off-line power supplies. Measurements of the device during turn-on revealed failures under high line voltages. The device was analysed using a combination of measurements and simulations which revealed that the dynamic avalanche was the cause of failure. An optimised LIGBT has been designed, simulated, fabricated and tested. The optimised device exhibits higher breakdown voltage and improved turn-on avalanche capability. Moreover, the optimised device showed improved avalanche capability during turn-off and reduced likelihood of latch-up. Introduction Due to their high current density, low power losses and reduced device area, high voltage LIGBTs have recently attracted lot of attention in high voltage, low power applications [1-2]. Off-line flyback converter is one of the most common Switch Mode Power Supply (SMPS) topologies for these kinds of applications (e.g. LED lighting, mobile phone and tablet chargers) because of the reduced cost achieved by minimising the number of circuit components [3]. A typical flyback converter has been analysed to gain better understanding of the requirements for the LIGBTs used in such low-power off-line SMPS applications. Figure 1 shows a schematic of the flyback circuit. When the switch S is closed (LIGBT turned-on), the rectified dc voltage is applied to the primary side of the transformer (V 1). Depending on the grid supply conditions, V 1 typically varies from 80 to 265V DC and in some cases (such as India or Brazil) it can be even higher. The Diode D 5 at the secondary side of the transformer is reverse biased, therefore the load is fed with the energy stored in the capacitor C. When S is opened (LIGBT turned-off), most of the energy stored in the primary side inductor will be transferred to the secondary side to charge the capacitor C and

feed the load. The part of the energy stored in the leakage inductance of the transformer which is not coupled to the secondary, has to be dissipated through the switch. Figure 1 Schematic of a flyback converter configuration. Figure 2 shows the collector voltage waveform of the LIGBT during normal operation in a flyback converter obtained using mixed-mode TCAD simulations. When the device starts conducting at turn-on, the collector voltage will drop from V 1 to the LIGBT on-state voltage. When the device is turned-off, the collector voltage starts rising beyond V 1 because of the energy stored in the leakage inductances (i.e. noncoupled inductance of the transformer, package leads). The peak of the collector voltage (V peak) will depend on the amount of stored energy in the transformer. Once the stored energy has been dissipated, the voltage will then stabilise to a level given by the sum of the primary side voltage V 1 and the reflected voltage from the secondary side (V R), which depends on the regulated output voltage and the turns ratio of the transformer. From the description above, it is clear that there are different requirements for the turn-on and turn-off of the LIGBT used in the flyback topology: i) the device has to be able to turn-on while a voltage V 1 is applied to the collector and ii) it has to be able to block the peak voltage V peak during turn-off without breaking down. Figure 2 Simulated collector voltage waveform for the LIGBT during one cycle of operation in the flyback circuit. Sudden increase of voltage V 1 can be caused by a surge in the line voltage or induced by lightning or an electrostatic discharge (ESD) event. To avoid failure of the LIGBT under these extreme conditions, it is

necessary to use protection circuits with several additional components which leads to undesirable increase in cost and size of the final product [4]. However, using an avalanche-capable high voltage device, the need for additional components can be eliminated without compromising safe operation of the product. Avalanche ruggedness has been investigated previously, but only for turn-off of vertical IGBTs [5]. To the authors knowledge, there are no studies reporting avalanche capability of Lateral IGBTs, either for turnon or turn-off. In this work we investigate the avalanche capability of a fabricated 800V rated LIGBT in bulk Si, explain the main mechanisms that lead to failure and propose an improved device design which will ensure better avalanche ruggedness. Measurements and Device Analysis The cross section and a photograph of a fabricated LIGBT are given in Figure 3 a) Cross-section of the 800V rated LIGBT.. The LIGBT was manufactured using a standard bulk CMOS technology with one additional lowly doped n-drift layer. The drift region design is based on a double-resurf approach [6] using the PTOP and the n-drift layers implanted into the p-substrate. The n-buffer layer is used to control the carrier injection during on-state and adjust the conduction vs switching losses trade-off. The device can support >800V in blocking mode and it can deliver in excess of 500mA when operated with a standard gate voltage Vg=5V (Fig. 4). Operating current density in the SMPS application is more than 100A/cm 2 and the LIGBT turns off in ~250ns at Tj=125C (Fig 5). a) b) Figure 3 a) Cross-section of the 800V rated LIGBT. b) Photograph of the fabricated 800V rated LIGBT device in bulk Si technology. Figure 4 LIGBT on-state Collector current at T j=125c for different gate voltages.

Figure 5 LIGBT turn-off waveforms measured under clamped inductive switching conditions. Figure 6 Schematic of the circuit used for measurements and mixed-mode TCAD simulations. Extensive analysis has been carried out using both simulations and the measurements in order to optimise the simulation models to ensure very good match between measured and simulated LIGBT performance. This approach ensured we could rely on simulations to both understand better the physics of failure under different conditions as well as to design an optimised device with improved performance. The schematic of the unclamped inductive switching (UIS) circuit used for analysis of the LIGBT performance in a flyback converter in measurements and mixed-mode simulations is shown in Fig.6. It is important to note that the capacitor C 1 represents the parasitic capacitance associated with the inductor L 1 and C 2 is associated with the stray capacitances of the test board. Their values have been extracted through measurements and they have been added to the circuit used for mixed-mode simulations. Turn-on At the beginning of the turn-on measurements and simulations the device is in the off-state with a constant voltage applied to the node Vdc. The device is then turned on by increasing the gate voltage of the LIGBT from 0V to 5V. When the gate is turned on, the current starts to flow through the device which reduces the collector voltage. This in turn builds current in the inductance L 1. Measurements have been done for a range of Vdc levels showing similar voltage and current waveforms up to the Vdc=560V when the device failed. The measured voltage and current waveforms during LIGBT turn-on obtained for Vdc=450V and Vdc=550V are given in Figs. 7 and 8 respectively. High electric field and high carrier concentration at turn-on induce dynamic avalanche resulting in the first peak in the current waveform. As the collector voltage decreases, the avalanche subsides and the parasitic capacitor C 1 is discharged by dv/dt. This leads to the second peak of current. When Vdc exceeds 550V a sudden increase in device current, which is not seen at lower voltages, is observed just before the failure occurs (Fig. 9).

Figure 7 LIGBT turn-on waveforms measured for Drift- 1 design at Vdc =450V. The device safely survives this test. Figure 8 LIGBT turn-on waveforms measured for Drift- 1 design at Vdc =550V, just before device failure. Figure 9 Failure of the LIGBT measured at turn-on for Drift-1 design at 560V. To understand the phenomenon behind the failure, mixed mode simulations have been carried out for different values of Vdc. Figure 10 shows initial simulations (red curves) which matched behaviour seen in measurements, confirming high accuracy of the TCAD model. When simulations were repeated without the avalanche model (black curves), the initial peak of current which is seen in measurements disappeared from simulated current waveform confirming that the onset of avalanche is responsible for the failure.

Figure 10 Comparison of the collector currents and voltages simulated with and without Avalanche model. It can be seen that the peak in the collector current which is seen in measurements is present only in the simulation which uses avalanche model (red curve) confirming that the avalanche precedes device failure. When the LIGBT is turned on, the carriers are injected into the depletion region with the high voltage still supported across the device. If the electric field is sufficiently high, avalanche multiplication can happen, resulting in localised increase in current which leads to failure (Fig 9). To improve device robustness at turn-on, the drift region must be optimised to allow more uniform electric field distribution. This has been achieved by optimising the metal field plate design and the Double Resurf PTOP layer length. The optimised device (Drift-2) has been compared to the original design (Drift-1) confirming that the avalanche peak current has been reduced (black curve) for the same Vdc voltage for which the original design was failing (Fig. 11). Figure 11 Comparison of the collector currents and voltages at turn-on for LIGBTs with Drift-1 and Drift-2 designs. Comparing Fig. 12 and Fig. 13 it is clear that the improved LIGBT design (Drift-2) has a reduced peak of the electric field at the collector side which limited the avalanche current.

Figure 12 Electric field distribution and electrostatic potential contours for the Drift-1 design at turn-on peak current (I peak1) shown in Fig. 9. Figure 13 Electric field distribution and electrostatic potential contours for the Drift-2 design at turn-on peak current (I peak2) from Fig 9. Similarly to the Drift-1 design, the highest electric field is located at the collector side, but in this case it is confined within a smaller region which results in weaker avalanche and more robust device performance. The optimised device (Drift-2) has been manufactured and compared to the original design (Drift-1), confirming simulation predictions and proving it can survive turn-on avalanche with Vdc=560V (Fig. 14). Figure 14 Measured turn-on waveforms for the LIGBT with the Drift-2 design at Vdc =560V. It is clear that the optimised device is more robust than the original design (Drift-1) as there is no first current peak which is the sign of dynamic avalanche. Turn-off During the device turn-off under UIS, the collector voltage will keep rising until the device goes into avalanche. The avalanche multiplication will continue until all the energy stored in the inductor is dissipated. Figure 15 compares the measured waveforms at turn-off for Drift-1 and Drift-2 designs which have been perfectly reproduced with simulations (Fig. 16).

Figure 15 LIGBT turn-off waveforms in UIS test measured for Drift-1 and Drift-2 designs for a maximum collector current of 150mA. Figure 16 Simulated LIGBT turn-off waveforms under UIS condition for Drift-1 and Drift-2 designs. The optimisation of the electric field in the drift region of the LIGBT has resulted in a device with ~50V higher breakdown (Drift-2 design). Comparing the performance of the original (Drift-1) and the optimised (Drift-2) LIGBTs under the UIS test, it is clear why the improved drift design has led to a more robust structure: for the same energy stored in the inductance L1, Drift-1 design will avalanche at a lower collector voltage and a higher avalanche current while the optimised LIGBT will avalanche at a higher voltage and a lower peak collector current. This is particularly important for repetitive avalanche events which can weaken the high voltage power device because of localized increase in temperature which eventually leads to latch-up and device failure [7]. Conclusions Avalanche capability for both turn-on and turn-off of fabricated LIGBTs has been investigated for the first time. Extensive analysis based on measurements and simulations highlighted that dynamic avalanche is causing a failure of the device during turn-on. A new device with improved electric field distribution has been designed using simulations, fabricated and tested. The results reveal that the optimised LIGBT has better breakdown voltage and avalanche capability which prevent failure during the turn-on. Moreover, the improved design exhibits lower avalanche current during turn-off under unclamped inductive switching conditions. This characteristic makes the device more immune to failure caused by repetitive avalanche events. References [1] T. Trajkovic, V. Pathirana, N. Udugampola, G. Camuso, F. Udrea, and G. Amaratunga, 800V LIGBT in Bulk Si for Low Power Compact SMPS Applications, Proc. ISPSD, pp. 401-404, 2013. [2] T. Terashima, A Novel Driving Technology for a Passive Gate on a Lateral-IGBT, Proc. ISPSD, 2007. [3] Introduction to Avalanche considerations for CoolMos in SMPS Applications, Infineon Application Note, April 2001. [4] Willers, M.J. et al. Analysis and design of a practical discontinuous-conduction-mode BIFRED converter, Transactions on Industrial Electronics, Vol. 46, No. 4, August 1999.

[5] C.C. Shen et al., Failure Dynamics of the IGBT During Turn-Off for Unclamped Inductive Loading Conditions, Industry Applications Conference, pp. 831-839, 1998. [6] D. Diseny et al., A new 800V lateral MOSFET with dual conduction paths, Proc. ISPSD, 2001. [7] Philips Semiconductor, Power MOSFET Single-Shot and Repetitive Avalanche Ruggedness Rating, Application Note n. 10273_1, 2003.