Evaluation Board for ADP EVAL-ADP FEATURES Full-featured demo board for the ADP Standalone capability Configurable dual synchronous step-down, dc-to-dc switching regulator Dual A/ A or A/ A output or single combined A output Input voltage V IN :.75 V to 5.5 V Selectable fixed output:.8 V,. V,.5 V,.8 V,.5 V,. V or adjustable output voltage to.6 V minimum Selectable switching frequency: khz, 6 khz,. MHz or synchronized from khz to MHz Configurable SYNC input or CLOCKOUT output Two independent enable inputs Two power good outputs Size: -7/6 inch -5/8 inch APPLICATIONS Demonstrate features and configurability of ADP Emulate functionality of ADP in a user s circuit Evaluate ADP performance GENERAL DESCRIPTION The ADP evaluation (demo) board is a complete, dual, step-down, dc-to-dc converter design based on the ADP, a configurable, dual A/single A, synchronous step-down, dc-to-dc regulator. The ADP is a versatile step-down switching regulator that satisfies a wide range of user point-of-load requirements. The two PWM channels are 8 phase shifted and provide ±.5% accurate regulated output voltages. For more details, see the ADP data sheet. The ADP evaluation board comes in two versions: the ADP-EVALZ with. V at A and.8 V at A outputs, switching frequency set to 6 khz, and pulse skip enabled, and the ADP-PH-EVALZ with interleaved. V at A single output, switching frequency set to. MHz, and forced PWM mode. If needed, the ADP evaluation board output voltages and configuration can be modified by changing the values of the appropriate passive components and changing the links. The ambient temperature operation range is from C to +85 C. ADP EVALUATION BOARD Figure. ADP-EVALZ V OUT :. V @ A; V OUT :.8 V @ A; f SW = 6 khz; Pulse Skip Enabled 866- Rev. Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied as is and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 78.9.7 www.analog.com Fax: 78.6. 9 Analog Devices, Inc. All rights reserved.
EVAL-ADP TABLE OF CONTENTS Features... Applications... General Description... ADP Evaluation Board... Revision History... Using the Evaluation (Demo) Board... Powering Up... Evaluating Performance of the DC-to-DC Converter... Modifying the Board... Typical Performance Characteristics...6 Bode Plots...9 Evaluation Board Schematics and Artwork... PCB Layout... Ordering Information... 6 Bill of Materials... 6 Ordering Guide... 7 ESD Caution... 7 REVISION HISTORY 7/9 Revision : Initial Version Rev. Page of
EVAL-ADP USING THE EVALUATION (DEMO) BOARD POWERING UP The ADP evaluation board is supplied fully assembled and tested. Before applying power to the evaluation board, follow the procedures in this section. Input Power Source The power source voltage must not exceed 5.5 V, the maximum operation input voltage of the ADP. Connect the negative terminal of the power source to the J (GND) jack of the evaluation board and the positive terminal of the power source to the J () jack of the evaluation board. Output Load Before connecting a load to the output of the demo board, make sure that the output voltage does not exceed the maximum operating voltage range of the load. To connect a load to the output of Channel, connect the negative terminal of the load to Jack J (GND) on the evaluation board and connect the positive terminal of the load to Jack J (+VOUT). To connect a load to the output of Channel, connect the negative terminal of the load to Jack J5 (GND) of the evaluation board and connect the positive terminal to Jack J6 (+VOUT). For the single interleaved output configuration, the outputs of Channel and Channel are shorted together by soldering Link CB. To apply a load to the single interleaved dual-phase output, connect the negative terminal of the load to either Jack J (GND) or Jack J5 (GND) of the evaluation board and connect the positive terminal of the load to either Jack J (+VOUT) or Jack J6 (+VOUT). Enabling and Disabling the DC-to-DC Converter HEADER EN is used to control Channel. Use one of the following methods to enable or disable Channel : To enable Channel, short the middle pin of HEADER EN to by placing a shunt in the on position, or apply a dc voltage from. V to 5.5 V to the middle pin. To disable Channel, short the middle pin of HEADER EN to GND by placing a shunt in the off position or apply a positive dc voltage below.8 V to the middle pin. HEADER EN is used to control Channel. Use one of the following methods to enable or disable Channel : To enable Channel, short the middle pin of HEADER EN to by placing a shunt in the on position, or apply a dc voltage from. V to 5.5 V to the middle pin. To disable Channel, short the middle pin of HEADER EN to GND by placing a shunt in the off position, or apply a positive dc voltage below.8 V to the middle pin. For the single interleaved output configuration, the EN and EN signals are connected together at the Circuit Breaker CB, which is a solder link. Use either HEADER EN or EN to enable and disable Channel and Channel simultaneously. Rev. Page of Input and Output Voltages To measure the input voltage, V IN, connect the negative probe of the voltmeter to Terminal T (GND) on the evaluation board and connect the positive probe to Terminal T (). To measure the output voltage of Channel, V OUT, connect the negative probe of the voltmeter to Terminal T (GND) and connect the positive probe to Terminal T. To measure the output voltage of Channel, V OUT, connect the negative probe to Terminal T5 (GND) and connect the positive probe to Terminal T6. To measure the output voltage, V OUT, for the single interleaved output configuration, connect the negative probe of the voltmeter to Terminal T7 (GND) and connect the positive probe to either Terminal T or Terminal T6. External Synchronization To synchronize the dc-to-dc converter to an external clock signal,. Short the middle pin of HEADER SCFG to GND by placing a shunt in the in position. This configures the (SYNC/CLKOUT) pin of the ADP as an input.. Apply an external clock signal to Test Point TP SYNC/CLKOUT. The clock signal must have a logic high level from. V up to the voltage of the input power, V IN, and a logic low level below.8 V. Set the external clock pulse width to more than ns and the frequency, f SYNC, equal to double the target PWM switching frequency, f SW : f SYNC = f SW () For reliable synchronization, the external clock frequency, f SYNC, must be in the range from 8 khz to MHz for the ADP-EVALZ board, which has the switching frequency set to 6 khz. When using the ADP-PH-EVALZ board, which has the switching frequency set point at. MHz, the external clock frequency f SYNC must be within the range from.6 MHz to MHz. Internal Clock Out Shorting the middle pin of HEADER SCFG to, performed by placing the shunt in the out position, makes the ADP internal clock available at Test Point TP (SYNC/CLKOUT). The frequency of the internal clock, f CLKOUT, is twice that of the switching frequency, f SW, of the converter and 9 phase-shifted. PGOOD and PGOOD Signals When Channel is enabled and the output voltage, V OUT, is in regulation range, the logic signal at the Test Point PGOOD is high. When Channel is enabled and the output voltage, V OUT, is in regulation range, the logic signal at Test Point PGOOD is also high. For the single dual-phase interleaved output configuration, the PGOOD and PGOOD signals are tied together at the Circuit Breaker CB, which is a solder link. Use either
EVAL-ADP Test Point PGOOD or Test Point PGOOD to monitor whether the converter output voltage, V OUT, is within regulation. EVALUATING PERFORMANCE OF THE DC-TO-DC CONVERTER Switching Waveforms To observe the switching waveform with an oscilloscope, place the probe tip at the end of Inductor L (or L for Channel ) that is connected to the SWx pin of the ADP. The probe ground is connected to GND. Output Voltage Ripple To observe the output voltage ripple, place the oscilloscope probe tip at Terminal T (or T6 for Channel ), the converter output, and connect the probe ground lead to Terminal T7 (GND). The oscilloscope input should be set to ac-coupled. Measuring Efficiency The efficiency, η, is calculated by comparing the measured input power with the measured output power of the converter: V I OUT OUT η = () VIN I IN Measuring Line Regulation Vary the input voltage and measure the change of the output voltage. Measuring Load Regulation Measure the load regulation by increasing the load current at the output and measuring the change in output voltage. Line Transient Response Generate a step input voltage (V IN ) change and observe the behavior of the output voltage, V OUT (V OUT for Channel ), with an oscilloscope. Load Transient Response Generate a load current transient at the output, V OUT (V OUT for Channel ), and observe the output voltage response with an oscilloscope. Use a current probe attached to the wire between the output and the load to visualize the current transient. MODIFYING THE BOARD To modify the converter configuration, unsolder and/or replace/remove the appropriate passive components or links on the board. Changing the Operation Mode Settings The operating mode of the ADP dc-to-dc converter can be changed by replacing the configuration resistor, R, with a different value, as shown in Table. This configuration sets the current limit for each channel and enables or disables the transition to pulse skip mode at light loads. Table. Setting the Operating Mode Maximum DC Load Current (A) Peak Current Limit (A) R (Ω) ± 5% V OUT V OUT V OUT V OUT Pulse Skip.. Enabled.7 k.. Forced PWM 8. k.5.9 Enabled 5 k.5.9 Forced PWM Rev. Page of
EVAL-ADP Changing the Output Voltages The output voltages set points of the converter can be changed by replacing Resistor R5, Resistor R6, Resistor R7, and Resistor R8 with the resistor values shown in Table. In addition, when the adjustable output voltage version is used for the ADP, the output voltage, VOUT, is set by the resistive voltage divider R5/R6 and the output voltage, VOUT, is set by the resistive voltage divider R/R. To calculate the desired resistor values, first determine the value of the bottom divider string resistor, R6 (R for Channel ), by ensuring that the divider string current, ISTRING, is greater than μa. For Channel, R6 =.6 V/ISTRING () For Channel, R =.6 V/ISTRING () Then calculate the value of the top resistor, R5 (R for Channel ). For Channel, V.6 V R5 R6 OUT (5).6 V For Channel, V.6 V R R OUT (6).6 V Note that when the output voltage of Channel, VOUT, is changed, to ensure stable operation, the values of Inductor L, the C and C output capacitors, and the R and C compensation components must be recalculated and changed (see the ADP data sheet for details on external component selection). If the output voltage of Channel, VOUT, is changed, the values of the Inductor L, the C5 and C6 output capacitors, and the R and C compensation components must be recalculated and changed. Changing the Switching Frequency The switching frequency (fsw) set point can be changed by replacing Resistor R9 with a different value, as shown in Table. Table. Setting the Switching Frequency, fsw R9 (Ω) ± 5% Switching Frequency, fsw (khz) 8. k 6 7 k Note that when the switching frequency (fsw) is changed, to ensure stable operation, the values of the Inductor L and Inductor L, the C, C, C5, and C6 output capacitors, and the R, C, R, and C compensation components must be recalculated and changed (see the ADP data sheet for details on external component selection). Changing the Soft Start Time The soft start time of the ADP on the evaluation board is programmed to ms. To change the soft start time, tss, replace Capacitor C7 (C9 for Channel ) with a different capacitor value using the following: For Channel, C7 [nf] = tss [ms] (7) For Channel, C9 [nf] = tss [ms] (8) Combining the Two Channels into a Single Output For a single, interleaved dual-phase output, make the following modifications: Short the outputs, +VOUT and +VOUT, by soldering the bridge on CB Tie the EN and EN signals by shorting CB Tie the PGOOD and PGOOD signals by shorting CB Tie the FB and FB signals by shorting CB Tie the COMP and COMP signals by shorting CB5 Set the same output voltages of both channels by choosing R5 = R7 and R6 = R8 Choose and set the operating mode to A/ A, forced PWM configuration, by setting R to.7 kω. The evaluation board version ADP-PH-EVALZ is already configured for interleaved dual-phase single output,. V at A,. MHz switching frequency, and forced PWM mode. Table. Programming the Output Voltages R5 (Ω) ± 5% R6 (Ω) ± 5% VOUT (V) R7 (Ω) ± 5% R8 (Ω) ± 5% VOUT (V) Open.8 Open.8 Open.7 k. Open.7 k. Open 8. k.5 Open 8. k.5 Open 5 k.8 Open 5 k.8 Open 7 k.5 Open 7 k.5 Open 7 k. Open 7 k. Open 8 k Adjustable.6 to <.6 Open 8 k Adjustable.6 to <.6 Open Adjustable.6 to. Open Adjustable.6 to. Rev. Page 5 of
EVAL-ADP TYPICAL PERFORMANCE CHARACTERISTICS 95 9 9 85 8 EFFICIENCY (%) 85 8 75 EFFICIENCY (%) 75 7 65 7 V OUT =.V; PULSE SKIP V OUT =.V; FORCED PWM 65 V OUT =.8V; PULSE SKIP V OUT =.8V; FORCED PWM 6 k k LOAD CURRENT (ma) Figure. Efficiency vs. Load, VIN = 5 V, fsw = 6 khz 866-6 55 V IN = 5V V IN =.V 5 k k LOAD CURRENT (ma) Figure 5. Efficiency vs. Load: Single Output, Dual-Phase VOUT =. V, fsw =. MHz 866-5 V OUT (V)..5..95.9.85.8.75 V OUT =.V, LOAD = A.7.5.75 5. 5.5 5.5 V IN (V) Figure. Line Regulation Channel, VOUT =. V 866- V OUT (V).85.8.85.8.85.8.795.79.785.78 V OUT =.8V, LOAD = A.775..5..5 5. 5.5 V IN (V) Figure 6. Line Regulation Channel, VOUT =.8 V 866-6 V OUT (V).5..95.9.85 V OUT (V).85.8.85.8.85.8.795.79.8 V IN = 5V, V OUT =.V.75 5 5 LOAD CURRENT (ma) Figure. Load Regulation Channel, VOUT =. V; Pulse Skip Enabled 866-.785.78 V IN = 5V, V OUT =.8V.775 5 5 LOAD CURRENT (ma) Figure 7. Load Regulation Channel, VOUT =.8 V; Pulse Skip Enabled 866-7 Rev. Page 6 of
EVAL-ADP..5 V OUT V OUT (V). I OUT.95 CHANNEL SW LOAD CURRENT = A.9..5..5 5. 5.5 V IN (V) 866-8 CH 5.V B W CH 5.mV B W CH.A Ω B W Mµs 6.5GS/s A CH.V 866- Figure 8. Line Regulation, Single Dual-Phase Output Figure. Load Transient Response,. A to A, V OUT =. V..5 V OUT V OUT (V). I OUT.95 CHANNEL SW V IN = 5V.9 5 5 5 5 LOAD CURRENT (ma) Figure 9. Load Regulation, Single Dual-Phase Output 866-9 CH 5.V B W CH 5.mV B W CH.A Ω B W Mµs 5MS/s A CH.6A Figure. Load Transient Response,. A to A, V OUT =.8 V 866- V OUT V OUT PHASE SWITCH NODE I OUT PHASE SW PHASE SWITCH NODE PHASE SW CH 5.V CH 5.V CH.mV B W Mns.5GS/s A CH.V 866- CH 5.V B W CH 5.mV B W CH 5.V B W CH.A Ω B W Mµs 5.MS/s A CH.A 866- Figure. Switching Waveforms, Single Dual-Phase Output Figure. Load Transient Response,. A to A, Single Dual-Phase Output, V OUT =. V Rev. Page 7 of
EVAL-ADP EN CHANNEL SW V OUT V OUT PGOOD SS I OUT CH 5.V B CH 5.V B W W CH.V B W CH.V B W M.ms 5.MS/s A CH.7V 866- CH 5.V B W CH 5mV B W CH.V Ω B W M.ms.5MS/s A CH.V 866-7 Figure Soft Start Channel, V OUT =. V Figure 7. Current Limit Operation Channel EN CHANNEL SW V OUT V OUT PGOOD SS I OUT CH 5.V B CH 5.V B W W CH.V B W CH.V B W M.ms 5.MS/s A CH.7V 866-5 CH 5.V B W CH 5mV B W CH.A Ω B W M.ms.5MS/s A CH.V 866-8 Figure 5. Soft Start Channel, V OUT =.8 V Figure 8. Current Limit Operation Channel EN PHASE SW V OUT PGOOD PHASE SW V OUT SS I OUT CH 5.V B CH 5.V B W W CH.V B W CH.V B W M.ms 5.MS/s A CH.7V 866-6 CH 5.V B CH 5.V B W W CH 5mV B W CH 5.A Ω B W M.ms 5.5MS/s A CH.A 866-9 Figure 6. Soft Start Single Output,. V Figure 9. Current Limit Operation Single Output Rev. Page 8 of
EVAL-ADP BODE PLOTS 5 5 9 MAGNITUDE (db) MAGNITUDE PHASE 6 6 PHASE (Degrees) 9 5 k k M k M FREQUENCY (Hz) 5 FREQUENCY MAGNITUDE PHASE M 5.86kHz.dB 5.99 M.kHz 9.6dB. M M 55.8kHz 9.67dB 5.5 Figure. Channel : V IN = 5 V, V OUT =. V, Load = A, f SW = 6 khz, Crossover Frequency (f CO ) = 55 khz; Phase Margin 5 866-5 5 9 MAGNITUDE (db) MAGNITUDE PHASE 6 6 PHASE (Degrees) 9 5 k k M k M FREQUENCY (Hz) 5 FREQUENCY MAGNITUDE PHASE M 57.5kHz.dB 7.96 M 8.7kHz 6.67dB.6 M M 6.7kHz 6.66dB 8.7 Figure. Channel : V IN = 5 V, V OUT =.8 V, Load = A, f SW = 6 khz, Crossover Frequency (f CO ) = 57 khz; Phase Margin 8 866- Rev. Page 9 of
EVAL-ADP EVALUATION BOARD SCHEMATICS AND ARTWORK 866- U 5 6 7 8 R8 K FREQ ADP SCFG 9 8 7 9 5 6 PAD 9 8 7 6 5 GND SW COMP SW PGND PGND SYNC/CLKOUT PGND OPCFG PGND COMP SW VDD SW T7 FB VSET SS PGOOD EN VIN VIN5 VIN6 EPAD FB VSET SS PGOOD EN VIN VIN VIN T CB PGOOD C T R K C5 UF 6.V GND T6 VOUT C UF 6.V PGOOD J GND FB T OPCFG FREQ VOUT L.UH COMP R6 7K For single VOUT operation: choose R5 = R7, R6 = R8 T CB: solder bridge for single VOUT T5 J5 GND GND CB EN C7 nf VOUT GND C6 UF C8 PF PGOOD CB FB SS R R7 K R K Open EN: External Control Signal C9 nf C UF 6.V R SCFG R L.7UH C Short EN to GND: Disable Channel FB GND J J6 +VOUT +.8V A EN EN C PF R K GND. TPoint R PGOOD TPoint R9 K Short EN to GND: Disable Channel Open EN: External Control Signal Short EN to : Enable Channel R5 R8 5K +VOUT CB5 COMP COMP Short COMP and COMP for single VOUT operation EN VSET CB VOUT VDD C6 7UF 6.V VSET C PF R SCFG R6 COMP PGOOD TPoint Short EN to : Enable Channel EN HEADER R7 FB VSET R5 OPCFG GND TPoint EN HEADER C UF 6.V VOUT VSET +.V A SS FB C5 COMP C PF EN J +5.V DC SYNC/CLKOUT J C GND 7UF 6.V Short EN and EN for single VOUT operation Short PGOOD and PGOOD for single VOUT operation Short FB and FB for single VOUT operation TP Figure. ADP-EVALZ Schematic: Dual. V @ A and.8 V @ A Output, Switching Frequency 6 khz, Pulse Skip Enabled Rev. Page of R C7 SCFG HEADER FREQ R9 8.K
EVAL-ADP FB 866- GND C OPCFG C8 PF VOUT R6.7K T J GND GND J J6 GND CB EN CB FB FB FB Short FB and FB for single VOUT operation EN T SCFG R L.UH R K Open EN: External Control Signal J5 EN PGOOD C7 nf R.7K R L.UH Short EN to GND: Disable Channel For single VOUT operation: choose R5 = R7, R6 = R8 +VOUT EN R K Short EN to : Enable Channel CB: solder bridge for single VOUT SS GND. TPoint C6 UF CB VOUT J C UF 6.V COMP VDD R7 K PGOOD TPoint R9 K R5 +VOUT T5 COMP COMP Short COMP and COMP for single VOUT operation C9 nf C 68PF PGOOD TPoint C VSET VSET R6 SCFG Short EN to : Enable Channel C UF 6.V EN HEADER R7 CB5 COMP VSET SS T C 68PF C5 OPCFG FREQ R GND TPoint R8 K Short EN to GND: Disable Channel Open EN: External Control Signal EN HEADER VOUT VSET R8.7K T C6 7UF 6.V PGOOD FB R K U 5 6 7 COMP 8 FREQ ADP SCFG 9 8 7 EN CB PGOOD 9 5 6 PAD 9 8 7 6 5 GND COMP SYNC/CLKOUT OPCFG COMP VDD FB VSET SS PGOOD EN VIN VIN5 VIN6 EPAD FB VSET SS SW PGOOD EN VIN VIN VIN R SW PGND PGND PGND PGND SW SW C5 T7 R5 +.V A Single VOUT T6 VOUT VOUT C UF 6.V +5.V DC C PF C J GND SYNC/CLKOUT TP 7UF 6.V GND R GND Short EN and EN for single VOUT operation C7 Short PGOOD and PGOOD for single VOUT operation Figure. ADP-PH-EVALZ Schematic: Single Dual-Phase Interleaved. V @ A Output, Switching Frequency. MHz, Forced PWM Rev. Page of SCFG HEADER FREQ R9 7K
EVAL-ADP PCB LAYOUT Figure. Layer Component Side 866- Rev. Page of
EVAL-ADP Figure 5. Layer Ground Plane 866-5 Rev. Page of
EVAL-ADP Figure 6. Layer Power Plane 866-6 Rev. Page of
EVAL-ADP Figure 7. Layer Bottom Side 866-7 Rev. Page 5 of
EVAL-ADP ORDERING INFORMATION BILL OF MATERIALS Table. ADP-EVALZ Bill of Materials Qty Reference Designator Description Manufacturer Part Number CB, CB, CB, CB5 Circuit breaker, 6, open CB Circuit breaker, open C Capacitor, MLCC, µf, 6. V, X5R, Murata GRMER6J7MEL C, C Capacitor, MLCC, pf, 5 V, CG, 6 TDK C68CGHJ C, C5, C7 Not populated C6 Capacitor, MLCC,. µf, V, X7R, 6 TDK C68X7RC5K C7, C9 Capacitor, MLCC, pf, 5 V, X7R, 6 Panasonic ECJ-VBHK C8, C Capacitor, MLCC, pf, 5 V, CG, 6 TDK C68CGHJ C, C, C5 Capacitor, MLCC, µf, 6. V, X5R, 85 TDK CX5RJ6M C Not populated C, C6 Capacitor, MLCC, 7 µf, 6. V, X5R, Panasonic ECJ-YBJ76M EN, EN, SCFG HEADER. inch Sullins PBCSAAN 5 TP, PGOOD, PGOOD, GND., GND Test point Sullins PBCSAAN 6 J, J, J, J, J5, J6 Jack, noninsulated, staking.8 inch Keystone Electronics 575- L Inductor, fixed,.7 µh, SMD TOKO FDV6-R7M L Inductor, fixed,. µh, SMD TOKO FDV6-RM R Resistor, Ω, / W, 5%, SMD, 6 R, R Resistor, kω, /W, 5%, SMD, 6 R, R5, R,R Resistor, Ω, / W, 5%, SMD, 6 5 R6, R, R, R5, R7 Not populated R7, R9 Resistor, kω, / W, 5%, SMD, 6 R8, R Resistor, kω, / W, 5%, SMD, 6 R6 Resistor, 7 kω, / W, 5%, SMD, 6 R8 Resistor, 5 kω, / W, 5%, SMD, 6 R9 Resistor, 8. kω, / W, 5%, SMD, 6 7 T, T, T, T, T5, T6, T7 Terminal, double turret, brass,.78 Keystone Electronics 5- U Configurable, dual A/single A, Analog Devices ADPACPZ-R7 synchronous step-down, dc-to-dc regulator Connector, shunt dual beam AU PCB Tyco Electronics 988- Standoff,.5 inch, #-, nylon 6/6, hex Keystone Electronics 9C Screw, nylon, slot pan head, - thread, ¼ inch length Richco Plastic Co. NSS--- Rev. Page 6 of
EVAL-ADP Table 5. ADP-PH-EVALZ Bill of Materials Qty Reference Designator Description Manufacturer Part Number CB, CB, CB, CB5 Circuit breaker 6, short CB Circuit breaker, short C Capacitor, MLCC, µf, 6. V, X5R, Murata GRMER6J7MEL C, C Capacitor, MLCC, 68 pf, 5 V, CG, 6 TDK C68CGH68J C, C5, C7 Not populated C6 Capacitor, MLCC,. µf, V, X7R, 6 TDK C68X7RC5K C7, C9 Capacitor, MLCC, nf, 5 V, X7R, 6 Panasonic ECJ-VBHK C8, C Capacitor, MLCC, pf, 5 V, CG, 6 TDK C68CGHJ C, C Capacitor, MLCC, µf, 6. V, X5R, 85 TDK CX5RJ6M C, C5 Not populated C, C6 Capacitor, MLCC, 7 µf, 6. V, X5R, 6 TDK C6X5RJ76M EN, EN, SCFG HEADER. inch Sullins PBCSAAN 5 TP, PGOOD, PGOOD, GND., GND Test point Sullins PBCSAAN 6 J, J, J, J, J5, J6 Jack noninsulated staking.8 inch Keystone Electronics 575- L, L Inductor, fixed,. µh, SMD TOKO FDV6-RM R Resistor, Ω, / W, 5%, SMD, 6 R, R Resistor, kω, / W, 5%, SMD, 6 R, R5, R Resistor, Ω, / W, 5%, SMD, 6 5 R6, R, R, R5, R7 Not populated R7, R9 Resistor, kω, / W, 5%, SMD, 6 R8, R Resistor, kω, / W, 5%, SMD, 6 R, R6, R8 Resistor,.7 kω, / W, 5%, SMD, 6 R9 Resistor, 7 kω, / W, 5%, SMD, 6 7 T, T, T, T, T5, T6, T7 Terminal, double turret brass.78 inch Keystone Electronics 5- U Configurable, dual A/single A, Analog Devices ADPACPZ-R7 synchronous step-down dc-to-dc regulator Connector shunt dual beam AU PCB Tyco Electronics 988- Standoff,.5 inch, #-, nylon 6/6, hex Keystone Electronics 9C Screw, nylon, slot pan head, - thread, ¼ inch length Richco Plastic Co. NSS--- ORDERING GUIDE Model ADP-EVALZ ADP-PH-EVALZ Z = RoHS Compliant Part. Description Dual output,. V at A and.8 V at A, 6 khz switching frequency, pulse skip enabled Single output, dual-phase interleaved,. V at A,. MHz switching frequency, forced PWM ESD CAUTION Rev. Page 7 of
EVAL-ADP NOTES Rev. Page 8 of
EVAL-ADP NOTES Rev. Page 9 of
EVAL-ADP NOTES 9 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB866--7/9() Rev. Page of