Load Adaptive Control for Mixed-Signal PFC Control IC

PEDS9 Load Adaptive Control for Mixed-Signal PFC Control C Ming-Hau Chan, Yu-Tzung Lin, Student Member, EEE and Ying-Yu Tzou, Member, EEE Power Electronic Systems & Chips Lab. Department of Electrical and Control Engineering, National Chiao Tung Univ., Hsinchu, Taiwan. Abstract This paper presents a mixed-signal power-factorcorrection (PFC) control C for the single-phase criticalconduction-mode (CRM) boost AC/DC converters. The peak current mode control is applied and analyzed by using the analog circuit. The voltage control loop is implemented in digital approach. This paper analyzes effect of the hysteresis band effect of the analog current arator in current loop. n digital voltage loop, the proper quantization resolutions both ADC and DAC are determined. The digital voltage controller uses a digital notch filter to achieve fast dynamic response and a low total-harmonic-distortion (THD) with high power factor (PF). A load adaptive control scheme to maintain same dynamic response of the put voltage at different load conditions change. The proposed mixed-signal PFC control scheme has been verified by using uter simulation with experimental results to validate feasibility. ndex Terms Power-factor-correction (PFC), criticalconduction-mode (CRM), mixed-signal control, analog current arator, quantization effect, digital notch filter, load adaptive control.. NTRODUCTON Power-factor-correction (PFC) control schemes have been developed to ly with the EN6-3- standard in input line current harmonic onents []. Active PFC techniques for single-phase boost converters have been widely discussed by academic and industrial researches over the past ten years []. Recently, due to science and technologies develop rapidly, low power electronic products (< W) such as note book adaptor, lighting and LCD monitor etc., need adding PFC techniques to maintain low harmonics distortion of the input line current. Continuousconduction-mode (CCM) is improper used in low power electronics products because needs large inductor to maintain operating in CCM. The critical-conduction-mode (CRM) have several advantages, such as small size inductor can reduce PCB area, inductor current decrease to zero in turn-off time can result zero-current-switching (ZCS) to increase efficiency etc. Thus, CRM has been widely applied for low power electronic products better than CCM. Analog PFC control techniques can provide robust voltage regulation with low total-harmonic-distortion (THD) on input line current under large input line voltage range, and the feasible control schemes are also realized with This work was supported by the National Science Council, Taipei, Taiwan, R. O. C. Project no. NSC 96-6-E-9-3. V g - EM Filter A/D MULT V ZOH ZCD D/A Digital Voltage Controller L,ref S R CS SR Flip-Flop Current Comparator Analog Current Controller Digital Voltage Loop Regulator V dc 4V DC commercial PFC Cs to meet the demanding requirements both on performance and cost. Because of the temperature sensitivity and a large amount of extra onents required for more licated control schemes in analog approach, digital control techniques are merging to simply the external control circuits and ease to implement lex control algorithm though digital circuit design better than with analog circuit control for various applications [3]. However, a pure digital realization for the current loop of the CRM PFC control scheme requires extremely large value of sampling frequency which will induce significant power losses. Mixed-signal technique to realization the CRM PFC control scheme can combine advantages both analog and digital circuit. For current loop, using analog circuit to achieve fast response under peak current mode control, flexible digital circuit for voltage loop can realize advance control algorithms [4]. This paper presents a mixed-signal PFC control C which combines the benefits of analog circuit and digital circuit implementation techniques to achieve perfect dynamic response for put voltage with the low THD and high power factor (PF) for a CRM boost AC/DC converter. Fig. shows overall system block diagram of the mixed-signal control for the CRM boost AC/DC converters, include the analog current control with the digital voltage control. The current loop is used peak current mode control to make inductor current can accurately track with current command. The voltage loop, except uses proportional-integral (P) controller to regulate put voltage at setting level, this paper proposes a notch filter to eliminate double line C A/D OF Digital Notch Filter H NV A/D V ref Adaptive Control Law Fig.. Overall system block diagram of the mixed-signal control for the boost AC/DC converters. GND

PEDS9 i g i g i L i L,ref Fig.. The relationship between hysteresis band with input line current fundamental waveform. Line Current THD (%) 8 7 6 4 3 Line Voltage: 8 Vrms Line Voltage: Vrms Line Voltage: 6 Vrms Line Voltage: Vrms Line Voltage: 6 Vrms frequency to achieve a fast dynamic response and to make the input line current maintain low THD distortion and high PF. Beside, due to the dynamic characteristics of the boost AC/DC converters are different at different load conditions, this paper also presents the load adaptive control scheme in digital voltage loop to obtain same dynamic responses at different load conditions change.. ANALYSS OF ANALOG CURRENT CONTROL LOOP For the current loop arator of analog peak current mode control, hysteresis band is necessary to eliminate the disturbance of noise to obtain a correct switching signal. Unfortunately, over-wide hysteresis band can also cause input current distortion. Therefore, the hysteresis band should be properly determined. Fig. shows the relationship between hysteresis band with input line current fundamental waveform. The hysteresis band is resulting a dc onent (Δ H ) in the reference signal of inductor current, i L,ref, i g is the input line current fundamental waveform, and i g is the line current waveform [], [6]. n Fig., assuming that the switching frequency is much higher than the line frequency, L,rms and can be the expressed as follow π g,rms = il,ref sinθdθ π () π = ( H sinθ)sinθdθ π Δ 4ΔH P = =. π ηv g,rms where is amplitude of input line current sinusoidal waveform, P is the put power, η is the factor of efficiency, and V g,rms is rms value of line voltage. And then, we can derive the root-mean-square (RMS) value of the input line current is as π g,rms = sin θ ΔH dθ π () 4 = ΔH ΔH. 4 π The THD and PF can be obtained as THD,dis,rms g,rms g g,rms = = (3) g,rms g,rms..3.4..6.7.8.9. Hysteresis Band (V) Fig. 3. The relationship between hysteresis band and THD at different input line voltages. Line Current (A). -. - Fig. 4. Hysteresis Band: mv Hysteresis Band: mv Hysteresis Band: mv...4.6.8...4.6.8.3 nput line current waveforms at three different hysteresis band. g,rms PF = =. (4) g,rms THD According to ()-(3), the relationship between influence of hysteresis band with the THD can be obtained as shown in Fig. 3, since the THD can be determined by designers through selecting the proper hysteresis band. n this paper, the hysteresis band is selected at least under 6 mv to make THD lower than % at universal input line voltage range. Fig. 4 shows input line current waveforms at three different hysteresis band conditions. When the hysteresis band is mv, the input line current is no distortion. At mv hysteresis band, the input line current is almost equal to the line current with mv hysteresis band. f the hysteresis band increases to mv, the input line current will distort at the zero crossing region. Fig. 4 sufficient reveals overwide hysteresis band can cause input line current distortion.. ANALYSS OF DGTAL QUANTZATON EFFECT n digital voltage control implementation, the rectified input line voltage is applied to result the current command. Therefore, due to wide range variation of the rectified input line voltage, the issues of the quantization resolution of the ADC with DAC must be concerned. Notice that the ADC and DAC are added as the interfaces between analog 3

PEDS9 Amplitude Amplitude Original Signal time Quantizer Quantized Signal time Fig.. Quantization effect on rectified input line voltage feedback. e(s) V V in V inf V MULTOUT g R Fig. 6. Equivalent block diagram of ADC quantization effect on rectified input line voltage feedback. Line Current THD (%) 9 8 7 6 4 3 4 6 7 8 9 Bit of Resolution (Bit) Fig. 7. The relationship between ADC resolutions and input line current THD. approach and digital approach. ADC converts the rectified line voltage and DAC transfers the current command signal, the signal resolution is determined by their least-significantbit (LSB). The quantization behavior can be modeled as added a noise into the control loop, this noise can cause undesired harmonic distortion at the current command, to make input PF decrease. The quantization behavior of the rectified input line voltage is shown in Fig.. The difference between the original signal and quantized signal can be modeled by an error onent introduced into the system. n order to determine the level of introduced harmonic onents of the current command, the regular shape of square waveform is used to represent the error signal. Then the worst case of the harmonic onent will be as follows 4 Δ e ADC( jω) = () max π 4 Δ e DAC( jω) = (6) max π where Δ is the resolution. From above error estimation equations, the adequate resolution for this mixed-signal CRM PFC system can be calculated. A. ADC Resolution for Rectified Line Voltage The rectified line voltage is sampled for giving the shape of the current reference. For reducing the harmonic distortions in input line current, the ADC resolution of the rectified input line voltage feedback should be high enough to eliminate the noise from quantization error as shown in Fig. 6. Assuming the current loop bandwidth is much higher than line frequency, the relationship between quantization noise of rectified input line voltage feedback and input line current waveform can be derived ~ i g = eadc( jω ) V. (7) max R From the EN 6-3- Class C requirement, the lowest limit of line current harmonic RMS value varies by different input line current RMS value and the minimum value is 3 % of line current RMS value π 3 Δ Vin,. (8) V V in inf The worst case occurs at minimum RMS value of input line voltage. f is., the minimum resolution should be lower than.. This is equivalent to 8-bit resolution. Moreover, the input line current THD which is controlled by the analog CRM PFC C, L66, is ab. %. From Fig. 7, the input line current THD which uses 8-bit resolution ADC in digital controller is also ab.6 %. B. DAC Resolution for Current Command The DAC converts the digital current command back into analog signal. Fig. 8 shows the equivalent block diagram of DAC quantization effect on current command. Assume the current loop bandwidth is much higher than line frequency, the inductor current will track the current command, V mult, immediately. Then the relationship between quantization noise of rectified input line voltage feedback and input line current waveform can be derived as follow ~ i g = edac( jω ). (9) max R The lowest limit of input line current harmonic RMS value varies by different input line current RMS value and the minimum value is 3 % of input line current RMS value P 3 Δ π R. () ηvin,rms The worst case occurs at minimum operating power and maximum input line voltage. Then the minimum resolution should be lower than.4 %. This is equivalent to -bit resolution. V. V V MULTOUT e DAC g R Fig. 8. Equivalent block diagram of DAC quantization effect on current command. DESGN OF DGTAL VOLTAGE CONTROLLER A. Small-Signal Modeling For the aim of finding a voltage loop controller to achieve 4

PEDS9 ˆv g, rms V ref r M V R g, rms M r g, rms Vg, rms R M Fig. 8. Small-signal circuit model of the boost AC/DC converter. - Notch Filter N(z) Voltage Compensator C(z) z - K DAC î Control-to-Output G COD (z) V Magnitude, (db) 4. db PSM Simulation 4 Transfer function 3 4.7 db - Due to line voltage - - K ADC Fig. 9. Block diagram of the digital voltage control loop. H Phase, (Degree) -.66 Hz - -3-4 - Frequency, (Hz) Hz low harmonic distortion in input line current and have enough phase margin for making sure the system is stable over a large range load operating conditions, it is necessary to get an insight into the voltage control loop of the boost AC/DC converter [8], [9]. Analysis of the small-signal model is performed on an average basis over a lete half-cycle of the input line frequency, assuming that the input line current is perfectly controlled to track the scaled input line voltage and the put voltage is constant over a switching period, and the efficiency of the converter is unity, the small-signal model transfer function of the voltage loop of boost AC/DC converter can be easily derived. According to power balance can be obtained as KM KPV vin,rmsiin,rms = v in,rms = vi () R where the input quantities v in,rms and i in,rms are rms values, v is the voltage controller put, v is the put voltage, i is the put current, K M is the gain of multiplier, K p is the factor of rectified input line voltage feedback, and R is the current sensing resistor. And then, adding perturbation in () and eliminating small-signal high order terms with dc onents, () can be re-written respectively as follows ˆ M Vin,rmsKM K P i = in,rms () r R M r V K K M ˆ in,rms M P iin, rms = (3) in,rms R r Fig.. Frequency responses of the control-to-put of the boost AC/DC converter, the circuit sweeping as blue line and the transfer function calculation as red line. where r is the small-signal equivalent put resistance and the hats express the perturbations in each quantities. n () and (3), r can be expressed as V r =. (4) The M in (8) and (9) represents the steady-state voltage conversion ratio in steady-state and can then be expressed as v VrK M KP M = =. () vin,rms R Therefore, according to (8) and (9) can construct the smallsignal equivalent circuit model as shown in Fig. 8. Note that the small-signal equivalent put resistance r is equal to the load resistance R. Thus, the control-to-put transfer function can be derived as ˆ i GCO( s) = = ˆ ˆ v i (6) KM KP R = Vin,rms. RVr src Then the sample-and-hold is applied for transferring G CO (s) to z-domain is as follow a Tsample Vin,rms KM KP R ( e ) GCOD( z) = a Tsample RVR z e (7) a = RC where T sample is digital sampling period, K M =.6, K P =.4, R =.3 Ω, and C = 3 μf. Fig. 9 shows block diagram of the digital voltage control loop. n Fig. 9, voltage loop controller includes two parts: one is the proportional-integral (P) controller, it can eliminate steadystate error and regulate closed loop bandwidth (BW), and a load adaptive control scheme will apply for improving the performance when load variations. Another one is the notch filter, it can eliminate double line frequency on put voltage to make input line current have low THD. Fig. shows the frequency responses of the control-to-put of the boost AC/DC converter, the circuit sweeping as blue line and the transfer function calculation as red line. B. Design of Digital P Controller Form of the P controller in z-domain can be expressed as z Av C( z) = Kv. (8) z B n order to obtain the enough phase-margin (PM) and the appropriate crossover frequency in voltage loop, in this paper sets crossover frequency at Hz at 9 % load v

PEDS9 4 4 394.98.99...3.4..6 Current distortion - -.98.99...3.4..6 Line Current (A) Fig.. The transient response of put voltage and input line current waveform with notch filter, load changes from % to 9 %. condition with 7 degrees phase-margin. According to these conditions to further determine parameters of the P controller are K v =., A v = -.998, and B v =, respectively. C. Design of Digital Notch Filter The transfer function of a second-order notch filter can be express as s λ N( s) = K. (9) n s bs λ When the notch filter center frequency ω o = λ, there is no signal transmission through the filter. And b is the 3 db rejection bandwidth. Using the bilinear transformation [] to transfer N(s) to z-domain as follow ( λ ) ( λ ) z ( λ ) z N( z) = K. () n ( λ b) ( λ ) z ( λ b) z The center frequency of the notch filter in z-domain can be obtained by setting the value of magnitude is equal to zero, which yields the magnitude of the notch filter is dropped to 3 db from the dc value of the notch filter in z-domain are found as follow λ cos( ω T sample) =. () o λ Note that the frequencies ω and ω where the magnitude is determined by cos( ΩTsample) = cos[( ω ω) Tsample] () ( λ ) b = ( λ ) b where Ω is the 3 db bandwidth of the notch filter. From () and (3), the λ and b can be determined as ω o λ = tan ( T sample ) (3) ΩT b = ( λ ) tan( sample ). (4) The center frequency of notch filter be placed at double line frequency which is Hz (ω line = ω o ), and the 3 db bandwidth of the notch filter sets at Hz. This paper sets the parameters of the notch filter are λ =.38 and b =.9 Line Current (A) 4 4 394.98.99...3.4..6 - -.98.99...3.4..6 Fig.. The transient response of put voltage and input line current waveform with notch filter, load changes from % to 9 %. TABLE LOAD LOOK-UP TABLE Load (%) 3 7 9 i (A)..7..7. α.36..7.8.4 β.... to satisfy the requirement. Fig. and Fig. show the input line current with and with notch filter, the load variation sets a step current load and changes from % to 9 %. n Fig., the put voltage transient time is 4 ms and the input line current THD is %. When the notch filter is applied in the voltage loop, the transient time still maintains at 4 ms but the input line current THD can be improved down to 4 % as shown in Fig.. D. Adaptive Gain Adjustments Scheme From previous section discuss, added notch filter can increase voltage loop BW and maintain the input line current low distortion. But at different load conditions, the dynamic characteristic of the boost AC/DC converter has also different. Therefore, a load adaptive control scheme is given to address different load conditions variation maintain perfect dynamic response. The load adaptive control scheme applies a look-up table to estimate the modified gain, and the modified gain is determined by using linear interpolation method [], [] α( m ) α( m) α = α( m) ( i i ( m)) () i ( m ) i ( m) TABLE SYSTEM PARAMETERS V g,rms input line voltage rms value V V dc put voltage average value 4 V P o rated put average power W f sw,min minimal switching frequency khz L in input inductor 8 μh C put capacitor μf β ( m ) β ( m) β = β ( m) ( i i ( m)). (6) i ( m ) i ( m) The look-up table of the modified gain of the digital P 6

PEDS9 4 4 Load from W to W.88.9.9.94.96.98 4 4 4 3 ms 43 ms Load from 6 W to W.88.9.9.94.96.98 Fig. 3. The transient responses of put voltage with load adaptive control scheme, load changes from W to W and 6 W to W. 4 Load form W to W Load from W to W - 48 ms -... Load from 6 W to W 4 V 4 V - 48 ms -... Fig.. The experimental results of transient responses of put voltage from W to W and 6 W to W with load adaptive control law. 4.88.9.9.94.96.98 4 4 4 3 ms 3 ms Load form 6 W to W.88.9.9.94.96.98 Fig. 4. The transient responses of put voltage with load adaptive control scheme, load changes from W to W and 6 W to W.. controller is shown in Table. The digital P controller with load adaptive control scheme can be modified as z β Av C( z) = α K. (7) v z Fig. 3 and Fig. 4 show the transient responses of put voltage with and with the load adaptive control scheme. n Fig. 3, the transient time is 43 ms from W to W and 3 ms from 6 W to W, these reveal when with load adaptive control scheme, dynamic response of the put voltage is different at different load conditions change. Applied the adaptive control scheme, Fig. 4 shows the transient time is maintained 3 ms from W to W and 3 ms from 6 W to W, the dynamic responses become the same at different load conditions change after added the load adaptive scheme. V. EXPERMENTAL RESULTS The related system parameters of the boost AC/DC converter is shown in Table. This paper uses the STMicoelectronics CRM PFC C, L66, to implement the analog current control and Texas nstrument (T) DSP, TMS3LF47, to develop the digital voltage control. Fig. shows the experimental result of the transient responses of put voltage with load adaptive control scheme. The load varies from W to W with 6 W to W, Fig. reveals the transient times is 48 ms at different load conditions change. V. CONCLUSON This paper proposes a mixed-signal realization technique for the CRM boost PFC AC/DC converters, including analog peak current mode control and digital voltage loop with load adaptive control scheme. The effect of hysteresis band of the current arator be implemented in analog circuit is analyzed. n digital voltage loop, notch filter is applied to eliminate the double line frequency on put voltage to improve dynamic response and to maintain low input line current THD. Moreover, the load adaptive control scheme is used to maintain the dynamic response at different load conditions change. Through the simulation with the experimental results verify the proposed feasibility. REFERENCES [] L. Rossetto, G. Spiazzi, and P. Tenti, Control techniques for power factor correction converters, in Proc. PEMC Conf., 994. [] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, A review of single-phase improved power quality AC-DC converters, EEE Trans. nd. Electron., vol., no., pp. 96-98, Oct. 3. [3] A. Prodic, J. Chen, R. W. Erickson, and D. Maksimovic, Digitally controlled low-harmonic rectifier having fast dynamic responses, in Proc. EEE APEC Conf., Mar., vol., pp. 476-48. [4] R. Zane and D. Maksimovic, A mixed-signal ASC power-factorcorrection (PFC) controller for high frequency switching rectifiers, in Proc. EEE PESC Conf., Jul. 999, vol., pp. 7-. [] D. S. Chen and J. S. Lai, A study of power correction boost converter operating at CCM-DCM mode, in Proc. EEE Sheastcon 93 Conf., Apr. 993. [6] A. Abramovitz, Effect of the ripple current on power factor of CRM boost APFC, in Proc. EEE PEMC Conf., Aug. 6, vol., pp. -4. [7] J. Turchi, Power factor correction stages operating in critical conduction mode, ON Semiconductor, Appl. Note AND83, Sep. 3. [8] C. Adragna, Control loop modeling of L66-baded TM PFC, STMicroelectronics, Appl. Note AN89, Mar.. [9] R. B. Ridley, Average small-signal analysis of the boost power factor correction circuit, VPEC Seminar, 989. [] K. Hirano, S. Nishimura, and S. Mitra, Design of digital notch filters, EEE Trans. Commun., vol., no. 7, pp. 964-97, Jul. 974. [] M. lic and D. Maksimovic, Digital Average Current-Mode Controller for DC DC Converters in Physical Vapor Deposition Applications, EEE Trans. Power Electron., vol. 3, no. 3, pp. 48-436, May 8. [] K. J. Astrom and B. Wittenmark, Adaptive Control, nd ed. Reading, MA: Addison Wesley, 994. 7