LCL VSC Converter for High-Power Applications

IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 1, JANUARY 2013 137 LCL VSC Converter for High-Power Applications Dragan Jovcic, Senior Member, IEEE, Lu Zhang, Student Member, IEEE, and Masood Hajian, Member, IEEE Abstract This paper studies an inductor-capacitor-inductor (LCL) voltage-source converter (VSC) ac/dc converter concept which can be employed as high-power static converter. The converter is designed to have fault current near or below the rated value under the dc-side short circuits. This is very important for applications with HVDC and, in particular, with high-power dc transmission networks. This converter is composedofanac/dcinsulated-gate bipolar transistor-based VSC converter and a passive LCL circuit. A transformer is not required since LCL circuit can achieve voltage stepping. The converter parameters are designed to have optimal response during the faults, good controllability, and to minimize converter losses. A detailed model is developed on the PSCAD platform for a 500-MW test system. The simulation confirms capability to independently control active and reactive power and demonstrates favorable fault responses. The transient fault current peaks are not significant and can be overcome with slight overrating. Index Terms AC DC power conversion, dc grids, high-voltage dc transmission, HVDC converter, insulated-gate biploar transistor (IGBT) converter. I. INTRODUCTION T HE VSC HVDC represents a significant advance over the traditional thyristor HVDC. It generates fewer harmonics, enables controllable reactive power exchange, and even achieves operation with passive ac grids [1]. On the downside, VSC converters are vulnerable to dc faults. A dc voltage depression causes overcurrents in IGBTs, and system protection will trip IGBTs. Consequently, the converter becomes an uncontrollable diode bridge, discharging the ac grid into the dc fault. This is a serious problem with HVDC since: the VSC converter becomes uncontrollable; the fault current magnitude can reach extreme values; it is only limited by the impedance on the ac side; diodes have good overcurrent capability and typically may sustain 10-p.u. current for a 10-ms ( rating from manufacturer s sheets); however, the ac protection operating time is typically longer than 10 ms, and the current magnitude frequently exceeds 10 p.u.; the high fault current implies that ac-side voltage will also be depressed, and the fault is propagated to the ac system. Manuscript received November 04, 2011; revised August 02, 2012; accepted September 09, 2012. Date of publication December 13, 2012; date of current version December 19, 2012. This work was supported by the Engineering and Physical Sciences Research Council U.K. (EPSRC) under Grant EP/H010262/1. Paper no. TPWRD-00938-2011. The authors are with the Electrical Engineering Department, University of Aberdeen, Aberdeen, AB24 3UE, U.K. (e-mail: d.jovcic@abdn.ac.uk; r02lz0@abdn.ac.uk; m.hajian@abdn.ac.uk). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPWRD.2012.2219560 A two-terminal VSC HVDC will clear the dc faults using ac CBs. The clearing time is limited by the speed of mechanical CBs to 30 50 ms. In order to limit the fault current magnitude, series reactors are introduced on both ac and dc sides. Since the entire HVDC system (two VSC converters and dc line)is tripped for a dc fault, the recovery is slow and may take 5 10 s. The VSC converters are being extensively studied for multiterminal HVDC and dc grids [2]. They are suitable for paralleling, can change power direction by reversing only current, andtheyarenotvulnerabletoacgriddisturbances. Nevertheless,thedcfaultsbecomeamuchmoreserious issue with dc grids. It will not be acceptable to clear dc faults by opening all ac CBs. The dc grids will need dc CBs, practically on each dc cable [3]. However, it has proven very challenging to develop dc CBs that can interrupt extreme currents (of the order of 50 ka) in very fast time (of the order of a few milliseconds) [4]. The semiconductor dc CBs can be combined with mechanical switches to achieve good operation speed and low losses, and they are becoming commercially available [5]. However, they have limitations in fault current magnitude, and the operating time is extended when protecting long transmission systems. The alternative approachtomanagingdcgridfaultsistocontrol dc fault current at the VSC converters. The fault currents can only be supplied from ac grids through ac/dc converters since there will be no other power sources in dc grids. If the fault level in the entire dc grid is reduced, the performance demand on dc CBs becomes less stringent in terms of peak current and operating time. In addition, the impact of dc faults on the ac grid is reduced. One method to achieve dc fault control in VSC converters is to use full H-bridge multilevel converters [6]. This converter retains full control under ac faults and under dc faults. On the downside, a full H-bridge converter has four times the number of switches compared with an ordinary two-level VSC converter. Another method recently studied is the topology with an alternate arm multilevel converter [7]. Similarly, this topology suffers from an excessive number of switches. The LCL passive circuits have some interesting properties under faults, which have been explored for developing highpower dc/dc converters [8], [9]. An adequately designed LCL filter can automatically regulate the power in such a way that voltage depressionononesideleadstocurrentreductiononthe opposite side. This approach has three important advantages: 1) the power reduction is inherent and does not rely on any protection circuits; 2) the cost of LCL components is considerably lower than semiconductors; and 3) the converter control is retained even during the most severe faults. This paper studies an ac/dc converter topology that employs apassive LCL circuit. The goal of the research is to develop a high-power VSC ac/dc converter that inherently limits the fault current and retains full control under ac or dc faults. The con- 0885-8977/$31.00 2012 IEEE

138 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 1, JANUARY 2013 (5) (6) where are - components of the PWM modulated control signal and is pole dc voltage. The basic circuit equations are Fig. 1. Proposed ac/dc converter. (7) (8) (9) verter should retain low cost/losses and good control in nominal operation. II. ANALYSIS OF CONVERTER TOPOLOGY A. Converter Topology The proposed three-phase ac/dc converter topology is shown in Fig. 1. The converter is comprised of a passive LCL circuit and a VSC converter. We assume a simple two-level three-phase sinusoidal pulsewidth modulation (SPWM)-controlled VSC, but any other topology (like Modular Multilevel Converter) is suitable. The point of connection with the grid (PCC) is at the voltage. Under normal conditions, we should have controllable and at and we should try to minimize converter current to reduce losses. Under faults, the converter can control current unless the gradient is very high. Under dc faults, we aim to have converter current within the rated values and the grid voltage closetotheratedvalue. B. LCL Circuit Equations and Controllability The LCL circuit is viewed as a power network with input connection ( and ) and output connection ( and ). The ac voltage vectors and are expressed as (1) (2) where are the voltage phasors, are the magnitudes, and are the phase angles of respective voltages. The subscripts and denote corresponding phasor components. We can position the coordinate frame arbitrarily and without loss of generality, is located on the -axis where,and 50 Hz. From (7) (9), we can express the capacitor voltage and the currents We will conveniently rewrite (11) (12) as where (10) (11) (12) (13) (14) (15) (16) (17) The above variables,and are conveniently introduced to study converter behavior. Ultimately, we need to determine the three parameters:,and, which can be obtained from the three equations (15) (17). The coefficient is a positive nonzero constant that is fully determined by the power transfer level as is explained later. Coefficients and are manipulated in the design stage, as will be discussed in Section III. Since,from (15) (17), we have (18) is control- In this topology, only the converter voltage lable, and the converter line-neutral rms voltage is (3) C. LCL Circuit for Case Replacing in (13) (14), we obtain (19) (4) (20)

JOVCIC et al.: LCL VSC CONVERTER FOR HIGH-POWER APPLICATIONS 139 Considering the normal operating conditions, there are several important conclusions from (19) (20) as follows. Grid current depends only on the converter voltage (not on the grid voltage). This implies very simple control and immunity to ac grid faults. The aforementioned conclusion also implies that the LCL circuit can achieve any stepping ratio and keep zero reactive power at and.wecan change the current sign and, therefore, change power direction (active and reactive) just by changing the sign of. As a consequence, we may not need transformers. Converter current depends only on the grid voltage. This current is on the axis and converter voltage is also on the axis (assuming a typical condition of ). This implies minimal current through the converter and low loss. Since depends only on the grid voltage, it cannot be controlled by the converter. This is a major disadvantage, since at partial loading, we will still have high current and losses in the converter. Unless the converter is always operated at full power, we cannot use case 0. Considering a dc fault condition, we have in (19) (20) and the following conclusions emerge: Grid current will be reduced to zero. This is a very much desired response since the ac grid sees an open circuit for dc faults. Converter current is not affected and remains at the rated value. This is a circulating reactive current between the converter and ac capacitor C. Therefore, the converter can sustain a dc fault indefinitely without damage. III. CONVERTER DESIGN The aforementioned case 0 shows excellent fault responses and controllability. The principal issue is the lack of direct control of converter current, which implies that relative converter losses will be high at low loading. In this section, we aim to reduce losses while retaining good fault responses by varying 0and 0. Dividing (23) with (24) and replacing (4) (5) (25) At rated power, we assume in (6) and replacing (25), we can obtain a quadratic equation that enables us to obtain for assumed and given,and (rated values). Once and are determined, we replace in (23) and calculate. B. Converter Operation Under Faults We assume that the converter is operating at full power just prior to the fault. We study inherent converter response and assume that the controller is inactive during faults ( and remain at rated values). In order to simplify the study and without loss of generality, we assume that the converter is designed for 0. From (24), we obtain the rated component of the converter voltage (26) where subscript denotes rated values. 1) Faults on : The converter currents under the extreme fault on can be obtained from (13) and (14) by replacing. Therefore, the magnitude of the grid fault current is (27) The magnitude of fault current relative to the rated current can be obtained by dividing (27) with (13) where the stepping ratio is introduced as (28) (29) A. Calculating In the general case be calculated as, the PCC complex power can (21) The singularity case of is not feasible in (28) since this would imply that in (23). This condition poses the following general limit on : (30) The magnitude of fault current is from (14): where is the number of phases ( in Fig. 1). Replacing (1) (2) in (21), we will have (22) (23) (24) (31) Dividing (31) with (14), the magnitude of fault current relative to the rated current will be (32) Equating (32) with 1, we obtain the condition where fault current exceeds the rated current

140 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 1, JANUARY 2013 for for (33) 2) Faults on DC Voltage : The converter currents under the most extreme pole-pole dc fault 0 can be obtained from (13) and (14) by replacing 0. The magnitude of grid fault current is (34) Dividing (34) with (13), the magnitude of fault current relative to the rated current will be (35) Equating (35) with 1, we obtain the condition where fault current exceeds the rated current Fig. 2. Ratio of fault current over rated current for faults on and on, versus the stepping ratio 0.25 1. Traces labeled 0.9 0.8, traces labelled 0.05 0.2. (36) The magnitude of converter fault current in (14) is (37) Dividing (37) with (14), the magnitude of the converter dc fault current relative to the rated current will be (38) Equating (38) with 1, we obtain the condition where fault current exceeds the rated current (39) The maximum value of (38) corresponds to the minimal rated current which occurs for. Figs. 2 and 3 show the aforementioned relative fault current magnitudes in (28), (32), (35), and (38) for a range of stepping ratios. Two different sets of values for and are shown in Figs. 2 and 3, with curves labeled a and b. Fig. 2 considers the case where the converter voltage is higher than the ac grid voltage. This case would be most commonly encountered with practical HVDC since high dc voltage is desired for long distance transmission. It is seen that the converter fault current will be close to or below the rated value for most and values. The worst case occurs with a stepping ratio close to 1 and very high and. In such cases, the fault current can approach 2 times the rated value, but this fault current can be readily controlled by the converter. The current on grid side also stays close to the rated value for or faults. Fig. 3 shows the case where converter voltage is lower than grid voltage 4). In this case, can only assume very low values since it is bounded by in (30). In practical HVDC systems, lower converter voltage may be adopted with monopolar cable dc systems where dc voltage is limited by the cable ratings. We can observe even more favorable fault Fig. 3. Ratio of fault current over rated current for faults on and on, versus the stepping ratio. Traces labelled 0.05 0.8, traces labelled 0.01 0.2. responses than in Fig. 2, since, in most cases, the fault current magnitude stays below the rated values. Note that is very low in both cases and. As a general conclusion, lower values are best for fault responses but the fault responses are still good (below 2 p.u.) even for very high values for and. By restricting values for and, we can keep fault currents below rated values. C. Selection of and In this section, we study the influence of and on LCL parameter values and on converter losses. A 500-MW test system is selected and parameters are given in Table I. Fig. 4 shows the system variables considering the case with 0.9 and with varied. It is seen that and are reducing as is increasing, but is increasing. It is convenient that the peak capacitor voltage is also reducing as is in-

JOVCIC et al.: LCL VSC CONVERTER FOR HIGH-POWER APPLICATIONS 141 TABLE I TEST SYSTEM DATA (TWO-LEVEL CONVERTER) creasing. The max and min labels correspond to maximum active power of 500 MW and minimum active power of 0, assuming 100 MVAr. As is increasing, the current at minimal power is reducing which reduces partial loading losses. The rated current curve is a parabola and is simplified further with 0; from (14), it can be shown that the minimum occurs at. Therefore, the drawback of high and is that the losses at high power will increase. It is evident that in the region 0.4 0.7, both the maximum and minimum currents are reasonably low. The frequency graph shows the operating frequency ( 50 Hz), the global resonance,thefirst local resonance, and the second local resonance. A proximity to global resonance indicates poorly damped modes. The last two graphs show the magnitude of and for faults on and on. These graphs confirm the study in Fig. 2 but note that 100 MVAr in Fig. 4. D. Converter Losses In order to finalize the values for and, the test converter losses are calculated. The losses in this converter include: conduction losses and switching losses, for IGBT and diodes (inductor and capacitor losses are not considered). The losses are calculated as [10] (40) (41) where is the peak current through the switches, and is the switch test voltage given in the manufacturer s datasheets. The PWM modulation index and phase angle can be obtained from the simulation at a particular power level. All circuit variables at the 500-MW power level that are used in (40) (41) areshownintableii.thevaluesofon-stateresistance, Fig. 4. System variables as is varied, with 0.9. TABLE II VARIABLES FOR LOSS CALCULATION AT 500 MW threshold voltage, voltage and are taken from the manufacturer s sheets for IGBTs switches. Fig. 5 shows the converter losses with different, fixed, and considering three power levels (Full power 100%, 50%, and 20%). Note that case of at full power would be a benchmark value for comparison with a conventional 2-level HVDC VSC converter. At full power, as is increasing, the losses are increasing. When the converter operates at lower power levels, the relative losses are higher comparing with full power case. Nevertheless, we believe that the loss of 3% 4% at 50% power and 6% 7% at 20% power level would be acceptable. For comparison, Fig. 6 shows the losses when is varied with fixed at three power levels also. The final selection of parameters will depend on the operating

142 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 1, JANUARY 2013 Fig. 5. Total converter losses based on respective power level as is varied. Fig. 6. Total converter losses based on respective power level as is varied. Fig. 7. Controller for the ac/dc converter. regime. Placing more emphasize on high power operation, we finally selected parameters as. E. Summary Design Steps The converter design procedure is summarized as follows. 1) Given data are,and. 2) Assume values for and, by observing the allowed range. 3) and are calculated using (25). 4) Calculating using (23). 5) Determine inductance, and capacitance C by using Fig. 8. Converter operation in steady state. (43) (42) (44)

JOVCIC et al.: LCL VSC CONVERTER FOR HIGH-POWER APPLICATIONS 143 Fig. 9. Converter response after a 0.1-s three-phase fault on. Fig. 10. Converter response after a dc fault on. 6) Plot graphs in Fig. 4 to determine the converter-rated currents and fault currents. 7) Select switches and switching frequency and using (40) (41), calculate losses for given parameters. 8) Repeat the above steps for different and until optimum values are selected. IV. PSCAD SIMULATION A. Controller System Design In order to demonstrate the feasibility of this topology, a simple controller is designed based on (13) and (14). This is

144 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 1, JANUARY 2013 a PQ controller with inner current control loops as shown in Fig. 7. B. PSCAD Simulation The PSCAD model includes detailed switch models and all parasitic resistances. Fig. 8 shows the PSCAD simulation in steady-state operation. We simulate the positive and negative step on active power at 0.85 s and 1.05 s, and positive and negative step on reactive power at 1.2 and 1.4 s. The converter controllability and transient stability are confirmed. In this figure, we can observe that the magnitude of is reduced as active power is reducing, which is a consequence of selecting 0. Fig. 9 shows the PSCAD simulation of the worst case threephase 0.1-s fault on at PCC. It is seen that the currents and only marginally transiently increase during the fault. There is no overvoltage on the LCL circuit capacitor. The converter normally operates during the fault and the recovery is fast. Fig. 10 shows the worst case pole-pole fault at the dc capacitors 0). It is observed that the converter current settles at close to the rated value as predicted in theoretical analysis. There is, however, a transient overcurrent which cannot be predicted with phasor modeling. The magnitude and duration of this overcurrent are not significant (2.7-p.u. negative peak and fully decaying after 700 ms) and may require only modest diode overrating. Alternatively, a small dc-side inductor can remove this transient peak. The voltage at PCC stays close to the rated value, and the dc fault is not transferred to the ac side. The small depression in is the result of reactive power circulation. The grid current is close to the rated value but active power is not drawn from the grid. [2] G.Asplund,B.Jacobson,B.Berggren,andK.Lindén, Continental overlay HVDC-grid, in Proc, CIGRÉ Session, Paris, France, 2010. [3] L. Tang and B. T. Ooi, Protection of VSC-multi-terminal HVDC against DC faults, in Proc. IEEE 33rd Annu. Power Electron. Specialists Conf., Jun. 2002, vol. 2, pp. 719 724. [4] D. Van Hertem, M. Ghandhari, J. B. Curis, O. Despouys, and A. Marzin, Protection requirements for a multi-terminal meshed DC grid, presented at the CIGRÉ Bologna Symp., Bologna, Italy, 2011, paper 282. [5] J. Häfner and B. Jacobson, Proactive hybrid HVDC breakers A key innovation for reliable HVDC grids, in Proc., CIGRÉ 2011 Bologna Symp., Bologna, Italy, paper 264. [6] C. C. Davidson and D. R. Trainer, Innovative concepts for hybrid multi-level converters for HVDC power transmission, in Proc. 9th Inst. Eng. Technol. Int. Conf. AC DC Power Transm., London, U.K., Oct. 2010, pp. 1 5. [7]M.M.C.Merlin,T.C.Green,P.D.Mitcheson,D.R.Trainer,D. R. Critchley, and R. W. Crookes, A new hybrid multi-level voltagesource converter with DC fault blocking capability, in Proc. 9th Inst. Eng. Technol. Int. Conf. AC DC Power Transm., London, U.K., Oct. 2010, pp. 1 5. [8] D. Jovcic, Bidirectional high power DC transformer, IEEE Trans. Power Del., vol. 24, no. 4, pp. 2276 2283, Oct. 2009. [9] D. Jovcic and B. T. Ooi, Theoretical aspects of fault isolation on highpower DC lines using resonant DC/DC converters, Proc. Inst. Eng. Technol. Gen., Transm. Distrib., vol. 5, no. 2, pp. 153 160, Feb. 2011. [10] B. Backlund, R. Schnell, U. Schlapbach, R. Fischer, and E. Tsyplakov, Applying IGBTs, Apr. 2009, Tech. Note ABB Switzerland Ltd., 5SYA2053-03. Dragan Jovcic (S 97 M 00 SM 06) received the D.Eng. degree in control engineering from the University of Belgrade, Belgrade, Serbia, in 1993 and the Ph.D. degree in electrical engineering from the University of Auckland, Auckland, New Zealand, in 1999. Currently, he is a Professor with the University of Aberdeen, Aberdeen, U.K., where he has been since 2004. He was also a Lecturer with the University of Ulster,Ulster,U.K.,from2000to2004andasaDesign Engineer in the New Zealand power industry from 1999 to 2000. His research interests are flexible ac transmission systems, HVDC, as well as integration of renewable sources and control systems. V. CONCLUSION A novel LCL VSC converter concept is presented which is recommended for use with HVDC transmission. Analytical modeling concludes that this topology has very favorable responses for either ac or dc faults. The fault currents will be below the rated values for a very wide range of design parameters. A model of the 500-MW 220-kV ac- to 600-kV dc converter is developed in PSCAD/EMTDC software and tested for normal operation and faults. The simulation confirms the ability to control active and reactive power independently. The dc-line and ac-line faults are tested, and responses indicate that currents are below rated values. The calculation of losses concludes that the converter has comparable efficiency to conventional VSC ac/dc converters. REFERENCES [1] G. Asplund, K. Eriksson, and K. Svensson, DC transmission based on voltage source converters, CIGRE SC14 Colloq. South Africa, 1997. Lu Zhang (S 11) received the B.Sc. and M.Sc. degrees in control engineering from the Harbin Institute of Technology, Harbin, China, in 2006 and 2008, respectively, and is currently pursuing the Ph.D. degree in electrical engineering at the University of Aberdeen, Aberdeen, U.K. His research interests are in control engineering and power electronics. Masood Hajian (M 10) received the B.Sc. degree in control engineering from Sharif University of Technology, Tehran, Iran, and the M.Sc. and Ph.D. degrees in power electronics from Isfahan University of Technology, Isfahan, Iran. Currently, he is a Research Fellow at the University of Aberdeen, Aberdeen, U.K.Hismainresearch interests include power electronics, electrical machines, nonlinear control, and variable-speed electrical drives.