Poceedings of the Intenational Confeence on Electonics and Softwae Science, Takaatsu, Japan, 05 Analyze Powe Supply ejection atio of LDO egulato Based on Accuate Sall Signal Model Po-Yu Kuo*, Gang-Zhi Fan and Chi-Huang Chiu Depatent of Electonic Engineeing, National Yunlin Univesity of Science and Technology 3 Univesity oad, Section 3,Douliou, Yunlin 6400, Taiwan,.O.C. *Eail:kuopy@yuntech.edu.tw ABSTACT The powe supply ejection atio (PS is a cucial specification fo the low-dopout egulato (LDO. Many cicuit topologies have been poposed to achieve high PS fo the LDO. To siplify the design flow, ost analog cicuit designes estiate the PS pefoance based on the sall signal odel. Howeve, the accuacy of the sall signal odel fo PS has not been veified. In this pape, the accuacy of the geneal sall signal odel has been analyzed. A new sall signal odel fo PS of LDO has been developed and veified. The siulation esults shows that the accuacy has been ipoved significantly while the new odel is applied copaing to the geneal odel. The siulation esults has been veified using a standad 0.35-µ CMOS pocess technology. KEYWODS Powe supply ejection atio (PS; low-dopout egulato (LDO; sall signal odel; CMOS pocess technology. INTODUCTION The low-dopout egulato (LDO is a vey coon cicuit block in the dc-dc convete. When an opeation voltage of an electonic device is supplied by a LDO, it is ipossible to avoid ipple noise voltage that coes along a powe supply line. To tackle the issue, it is necessay to design a LDO with high powe supply ejection atio (PS so that the ipact caused by the ipple noise voltage can be educed as uch as possible. Theefoe, any cicuit topologies have been poposed to achieve high PS fo the LDO [] [4]. To siplify the design flow, ost analog cicuit designes estiate the PS pefoance based on the sall signal odel. Howeve, the sall signal odel fo PS is not staightfowad to obtain. The sall signal odel of PS fo LDO has been discussed in []. The poposed odel is geneally used by ost cicuit designes. Howeve, this odel is not accuate to analyze the PS pefoance of LDO. In this pape, the PS odel in [] has been veified and the esults show that it beas a significant diffeence copaed with the LDO at low fequencies. The eos fo this odel ae up to.db. Theefoe, a new sall signal odel fo PS of LDO has been developed and veified, by consideing the effects caused by the paasitic capacitos. The esults show that the eos of PS ae educed to.7db while new odel is applied. With this new odel, the analog cicuit designes can estiate the accuate PS in the pe-design stage. Geneal PS Model of LDO. PS Model fo Eo Aplifie The PS is ainly caused by the device connected diectly to the powe supply input and output []. In the LDO, any tansistos in the eo aplifie ae connected to the powe supply input and output. Hence, we ust conside the PS odel fo eo aplifie. To pefo double-to-single-ended convesion, and add the ac signal obtained fo the input diffeential pai to a single-ended signal, ost eo aplifie that has a single-ended output ISBN: 978--94968-7-8 05 SDIWC 4
Poceedings of the Intenational Confeence on Electonics and Softwae Science, Takaatsu, Japan, 05 (a (b Figue. (a Type-A eo aplifie and (b its sall signal odel fo PS. use a cuent-io load. The cuent-io load can be ipleented by connecting the PMOS to the supply voltage, o by connecting the NMOS to the gound. In the following of this pape, the PMOS-io is classified as Type-A topologies and NMOS-io is classified as Type-B topologies. Hence, it is appaent that the ipleentation of the cuent io is cucial in deteining the PS of eo aplifie. To analyze the PS, V dd and V out-a has been defined as ac ipple at the powe supply and the output of the aplifie, espectively. The intenal paatactic capacitance has been ignoed fo siplicity because they ae uch salle copaing to the capacitance of the lage output powe device.. Type-A Topologies A stuctue of Type-A eo aplifie and its sall signal odel fo PS ae shown in Fig. []. The aplifie consists of an NMOS input diffeential pai with the PMOS cuent io load connected to the powe supply. The sall signal PS odel of the Type-A eo aplifie is shown in Fig. (a. The odel is obtained by gounding the two diffeential inputs and applying the AC voltage souce V dd as the input supply. The channel esistances of the PMOS and NMOS devices ae and, espectively. The cuent-dependent cuent souce i is the cuent flowing though into the output. Thus, this cuent odels the effect of cuent io. Because the diode-connected (a (b Figue. (a Type-B eo aplifie and (b its sall signal odel fo PS. PMOS load of Mp is uch salle than, the /g esistance can be ignoed so that powe supply ipple is entiely eflected at the output. The elationship of V out-a and V dd is shown as follows: Vdd i ( A = + V dd V dd = Vdd + ( + + Vout + Fo Type-A aplifie topologies, the entiely supply ipple is tansfeed to the output ove a wide fequency ange..3 Type-B Topologies A stuctue of Type-B eo aplifie and its sall signal odel fo PS ae shown in Fig. []. The aplifie in Fig. (a is a geneal stuctue of the Type-B Topology eo aplifie. The aplifie consists of PMOS input diffeential pai with the NMOS cuent io load connected to the gound. The PS odel to this eo aplifie can be deived by using the sae analysis pocedue in pevious section. The odel is obtained by gounding the two diffeential inputs and applying the AC voltage souce V dd as the input supply. The cuent-dependent cuent souce i is the cuent flowing though into the output. Thus, this cuent odels the effect of cuent io. Because the diode-connected NMOS ISBN: 978--94968-7-8 05 SDIWC 5
Poceedings of the Intenational Confeence on Electonics and Softwae Science, Takaatsu, Japan, 05 Figue 3. The scheatic of a conventional LDO. Vout Vdd i( A = + V dd Vdd = 0 ( + + load of MN is uch salle than the channel esistance, the /g esistance can be ignoed so that powe supply ipple is entiely eflected at the output. The elationship of V out- A and V dd is shown as follows: Fo (, it is vey clea that thee is not dc ipple appeas at the output and theoetically isolating the output fo the input supply ipple. Fo the geneal LDO, ost cicuit designes use a PMOS tansisto as powe tansisto at the output because it exhibits a low fowad dop and consequently a low powe loss acoss the PMOS device. The PS odel of LDO can be obtained by including the PS odels of eo aplifie and PMOS powe tansisto..4 Conventional PS Model fo LDO The conventional sall signal odel fo PS of a geneal LDO shown in Fig. 3, has been discussed in []. The syste tansfe function can be deived fo the odel as shown in (3 as follows: whee a = a0 + as + as H LDO ( s b0 + b s + bs = (3 ( + + g ( 0 ds p ds ( C C a = Cgspds ds ds 4 gdp + a = + + g + g ds ds b = 0 + C + C + p ds g ( C + C + Cgsp ( C + ( C Cgdp ds + ( C + C + C gdp ( + + ( + ds p ds ds 4 b = ds gdp out ds ds 4 + C + C gdp ds ds b = C ds ds 4 ( C + C + C + C gsp gdp ( + + C ( 4 + ds ds ds ds 4 ( + ds ( C + C + Cgsp ( g 4 p g ds ( gp g ( ds 4 C + Cout ( C + C ds + C + C + C C gdp ds ds 4 gsp ds ds 4 out ds ds 4 gsp ( C + C out out In the equation, g p is the tansconductance of tansisto Mp, g is the tansconductance of input diffeential pai M and M, oa is the output esistance of the single stage aplifie, dsmp is the dain-souce esistance of tansisto Mp, C is the ille copensation capacito, C ol is the output capacito of LDO, and C oa is the output capacito of single stage aplifie. In the following expeients, the SPICE siulation esults wee caied out using a standad 0.35-µ CMOS pocess technology. The siulated PS of the syste tansfe function (3 and the LDO ae shown in Fig. 4. Fo the siulation esults, the PS pefoance fo the syste tansfe function beas a significant diffeence up to.db at low fequencies. The eos in agnitude at low fequencies ae up to 3.% when the tansfe function (3 is applied. Since the eos ae too lage to deonstate accuate PS behavio of the LDO, the tansfe function (3 cannot be used to estiate PS behavio of the LDO. 3 POPOSED NEW PS MODEL OF LDO To achieve high accuacy, the sall signal odel can be constucted based on the coplete sall signal equivalent cicuit of CMOS tansisto discussed in [5][6]. In ode to ISBN: 978--94968-7-8 05 SDIWC 6
Poceedings of the Intenational Confeence on Electonics and Softwae Science, Takaatsu, Japan, 05 Figue 4. function (3. Siulated PS of the syste tansfe Figue 6. Siulated PS of the the poposed PS odel. achieve siplicity without losing of accuacy, the intinsic pat of coplete sall signal equivalent cicuit of CMOS tansisto, has been applied in the new odel. Fig. 5 shows the poposed PS odel of LDO. To ipove the accuacy of the geneal odel, two paasitic capacitos C gsp and C gdp, have been added in the poposed odel. The Gate-Souce capacito of Mp, C gsp, ust be consideed in the sall signal odel since this capacito is connected to the powe supply V dd. The Gate-Dain capacito of Mp, C gdp, is connected to the output node V out. Thus, capacito C gdp will affect the PS of the LDO and cannot be ignoed in the sall signal odel. The siulated PS of the poposed odel is shown in Fig. 6. Fo the siulation esults, the PS pefoance fo the poposed odel is identical to the CMOS LDO. The axiu eo of agnitude fo the sall signal odel at low fequencies is educed to.7 db copaed with that fo the tansfe function (3. The eo at low fequencies ae.38% when the poposed PS odel is applied. Hence, the poposed new odel can achieve accuate estiation fo PS of LDO. 4 CONCLUSIONS This pape poposed a new sall signal odel fo PS of LDO. The accuacy of the geneal and new odels have been veified with CMOS LDO. The eos of PS at low fequencies ae up to 3.% when the geneal odel is applied. The eos at low fequencies ae educed to.38% if the new odel is applied. With the poposed odel, the cicuit designes can estiate accuate PS pefoance duing the pe-design stage and speed up the whole design flow. ACKNOWLEDGEMENT The authos would like to appeciate the suppot fo Ministy of Science and Technology, Taiwan, unde the Gants: MOST 03--E-4-079 and the technical suppot fo the National Chip Ipleentation Cente (CIC. EFEENCES Figue 5. Poposed PS odel of LDO. [] V. Gupta, G. A. incon-moa, and P. aha, Analysis and design of onolithic, high PS, linea egulatos fo SoC applications, in Poc. IEEE Int. SOC Conf., pp. 3 35, Sep. 004. ISBN: 978--94968-7-8 05 SDIWC 7
Poceedings of the Intenational Confeence on Electonics and Softwae Science, Takaatsu, Japan, 05 [] B. Foejt, V. entala, J. D. Ateaga, and G. Bua, A 700+-W class D design with diect battey hookup in a 90-n pocess, IEEE J. Solid-States Cicuits, vol. 40, no. 9, pp. 880 887, Sep. 005. [3] S. Heng and C.-K. Pha, A low-powe high-ps low-dopout egulato with bulk-gate contolled cicuit, IEEE Tans. Cicuits Syst. II, vol. 57, no. 4, pp. 45 49, Ap. 00. [4] M. Ho, K. N. Leung, and K.-L. Mak, A low-powe fast-tansient 90-n low-dopout egulato with ultiple sall-gain stages, IEEE J. Solid-States Cicuits, vol. 45, no., pp. 466 475, Nov. 00. [5] J. Guo and A. Wethof, Diect paaete extaction ethod fo deep subicoete etal oxide seiconducto field effect tansisto sall signal equivalent cicuit, IET Micowaves, Antennas & Popagation, vol. 3, no.4, pp. 564 57, Jun. 009. [6] Ooi, B. L., Z. Zhong, and M. S. Leong. Analytical Extaction of Extinsic and Intinsic FET Paaetes. IEEE Tansactions on Micowave Theoy and Techniques, vol. 57, no., pp. 54 6, Feb. 009. ISBN: 978--94968-7-8 05 SDIWC 8