FEATURES n Wide Input Votage Range: 3V to 8V n Low Quiescent Current: 7µA n Low Dropout Votage: 35mV n Output Current: 2mA n LT31HV Survives 1V Transients (2ms) n No Protection Diodes Needed n Adjustabe Output from 1.22V to 6V n 1µA Quiescent Current in Shutdown n Stabe with.7µf Output Capacitor n Stabe with Auminum, Tantaum or Ceramic Capacitors n Reverse-Battery Protection n No Reverse Current Fow from Output n Therma Limiting Avaiabe in 5-Lead ThinSOT TM and 8-Lead DFN Packages APPLICATIONS n Low Current High Votage Reguators n Reguator for Battery-Powered Systems n Teecom Appications n Automotive Appications LT31 2mA, 3V to 8V Low Dropout Micropower Linear Reguator DESCRIPTION The LT 31 is a high votage, micropower ow dropout inear reguator. The device is capabe of suppying 2mA of output current with a dropout votage of 35mV. Designed for use in battery-powered or high votage systems, the ow quiescent current (7μA operating and 1μA in shutdown) makes the LT31 an idea choice. Quiescent current is aso we controed in dropout. Other features of the LT31 incude the abiity to operate with very sma output capacitors. The reguators are stabe with ony.7μf on the output whie most oder devices require between 1μF and 1μF for stabiity. Sma ceramic capacitors can be used without the necessary addition of ESR as is common with other reguators. Interna protection circuitry incudes reverse-battery protection, current imiting, therma imiting and reverse current protection. The device is avaiabe as an adjustabe device with a 1.22V reference votage. The LT31 reguator is avaiabe in the 5-ead ThinSOT and 8-ead DFN packages. L, LT, LTC and LTM are registered trademarks of Linear Technoogy Corporation. ThinSOT is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents incuding 6118263, 6125. TYPICAL APPLICATION 5V Suppy with Shutdown Dropout Votage V IN 5.V TO 8V V SHDN <.3V >2.V OUTPUT OFF ON 1μF IN OUT LT31 SHDN ADJ GND 3.92M 1.27M 31 TA1 V OUT 5V 2mA.7μF DROPOUT VOLTAGE (mv) 35 3 25 2 15 1 5 2 6 8 1 12 1 16 18 2 OUTPUT CURRENT (ma) 31 TA2 31fd 1
LT31 ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Votage, Operating... ±8V Transient (2ms Surviva, LT31HV)... +1V OUT Pin Votage... ±6V IN to OUT Differentia Votage...±8V ADJ Pin Votage... ±7V SHDN Pin Input Votage... ±8V Output Short-Circuit Duration...Indefi nite Storage Temperature Range ThinSOT Package... 65 C to 15 C DFN Package... 65 C to 125 C Operating Junction Temperature Range (Notes 3, 1, 11)... C to 125 C Lead Temperature (Sodering, 1 sec, SOT-23 Package)...3 C PIN CONFIGURATION IN 1 GND 2 SHDN 3 TOP VIEW S5 PACKAGE 5-LEAD PLASTIC SOT-23 5 OUT ADJ T JMAX = 125 C, θ JA = 15 C/ W θ JC = 25 C/W MEASURED AT PIN 2 SEE APPLICATIONS INFORMATION SECTION OUT ADJ NC GND 1 2 3 TOP VIEW 9 DD PACKAGE 8-LEAD (3mm 3mm) PLASTIC DFN EXPOSED PAD IS GND (PIN 9) MUST BE SOLDERED TO PCB T JMAX = 125 C, θ JA = C/ W θ JC = 1 C/W MEASURED AT PIN 9 8 7 6 5 IN NC NC SHDN ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT31ES5#PBF LT31ES5#TRPBF LTBMF 5-Lead Pastic SOT-23 C to 125 C LT31IS5#PBF LT31IS5#TRPBF LTBMF 5-Lead Pastic SOT-23 C to 125 C LT31HVES5#PBF LT31HVES5#TRPBF LTBRS 5-Lead Pastic SOT-23 C to 125 C LT31HVIS5#PBF LT31HVIS5#TRPBF LTBRS 5-Lead Pastic SOT-23 C to 125 C LT31EDD#PBF LT31EDD#TRPBF LBMG 8-Lead (3mm 3mm) Pastic DFN C to 125 C LT31IDD#PBF LT31IDD#TRPBF LBMG 8-Lead (3mm 3mm) Pastic DFN C to 125 C LT31HVEDD#PBF LT31HVEDD#TRPBF LBRT 8-Lead (3mm 3mm) Pastic DFN C to 125 C LT31HVIDD#PBF LT31HVIDD#TRPBF LBRT 8-Lead (3mm 3mm) Pastic DFN C to 125 C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT31ES5 LT31ES5#TR LTBMF 5-Lead Pastic SOT-23 C to 125 C LT31IS5 LT31IS5#TR LTBMF 5-Lead Pastic SOT-23 C to 125 C LT31HVES5 LT31HVES5#TR LTBRS 5-Lead Pastic SOT-23 C to 125 C LT31HVIS5 LT31HVIS5#TR LTBRS 5-Lead Pastic SOT-23 C to 125 C LT31EDD LT31EDD#TR LBMG 8-Lead (3mm 3mm) Pastic DFN C to 125 C LT31IDD LT31IDD#TR LBMG 8-Lead (3mm 3mm) Pastic DFN C to 125 C LT31HVEDD LT31HVEDD#TR LBRT 8-Lead (3mm 3mm) Pastic DFN C to 125 C LT31HVIDD LT31HVIDD#TR LBRT 8-Lead (3mm 3mm) Pastic DFN C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifi cations, go to: http://www.inear.com/tapeandree/ 2 31fd
ELECTRICAL CHARACTERISTICS LT31 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T J = 25 C. SYMBOL CONDITIONS MIN TYP MAX UNITS Minimum Input Votage I LOAD = 2mA 3 3.3 V ADJ Pin Votage (Notes 2, 3) V IN = 3.3V, I LOAD = 1μA 3.3V < V IN < 8V, 1μA < I LOAD < 2mA Line Reguation ΔV IN = 3.3V to 8V, I LOAD = 1μA (Note 2) 1 1 mv Load Reguation (Note 2) V IN = 3.3V, ΔI LOAD = 1μA to 2mA 13 25 mv V IN = 3.3V, ΔI LOAD = 1μA to 2mA mv Dropout Votage V IN = V OUT(NOMINAL) (Notes, 5) GND Pin Current V IN = V OUT(NOMINAL) (Notes, 6) I LOAD = 1μA I LOAD = 1μA I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 2mA I LOAD = 2mA I LOAD = ma I LOAD = 1μA I LOAD = 1mA I LOAD = 1mA I LOAD = 2mA 1.2 1.18 1.22 1.22 1.2 1.26 12 18 25 2 27 36 3 35 5 35 1 57 Output Votage Noise C OUT =.7μF, I LOAD = 2mA, BW = 1Hz to 1kHz 115 μv RMS ADJ Pin Bias Current (Note 7) 1 na Shutdown Threshod V OUT = Off to On 1.3 2 V V OUT = On to Off.25 1.3 V SHDN Pin Current (Note 8) V SHDN = V V SHDN = 6V Quiescent Current in Shutdown V IN = 6V, V SHDN = V 1 μa Rippe Rejection V IN = 7V (Avg), V RIPPLE =.5V P-P, f RIPPLE = 12Hz, 6 7 db I LOAD = 2mA Current Limit V IN = 7V, V OUT = V 7 ma V IN = 3.3V, ΔV OUT =.1V (Note 2) 25 ma Input Reverse Leakage Current V IN = 8V, V OUT = V 6 ma Reverse Output Current (Note 9) V OUT = 1.22V, V IN < 1.22V (Note 2) 2 μa 7 12 25 65 1 2 3 1 5 1 1 V V mv mv mv mv mv mv mv mv μa μa μa μa μa μa μa Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The LT31 is tested and specifi ed for these conditions with the ADJ pin connected to the OUT pin. Note 3: Operating conditions are imited by maximum junction temperature. The reguated output votage specifi cation wi not appy for a possibe combinations of input votage and output current. When operating at maximum input votage, the output current range must be imited. When operating at maximum output current, the input votage range must be imited. Note : To satisfy requirements for minimum input votage, the LT31 is tested and specified for these conditions with an externa resistor divider (29k bottom, 392k top) for an output votage of 3.3V. The externa resistor divider adds a 5µA DC oad on the output. Note 5: Dropout votage is the minimum input to output votage differentia needed to maintain reguation at a specifi ed output current. In dropout, the output votage is equa to (V IN V DROPOUT ). Note 6: GND pin current is tested with V IN = V OUT (nomina) and a current source oad. This means the device is tested whie operating in its dropout region. This is the worst-case GND pin current. The GND pin current decreases sighty at higher input votages. Note 7: ADJ pin bias current f ows into the ADJ pin. Note 8: SHDN pin current f ows out of the SHDN pin. Note 9: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output votage. This current f ows into the OUT pin and out of the GND pin. Note 1: The LT31 is tested and specifi ed under puse oad conditions such that T J T A. The LT31E is 1% tested at T A = 25 C. Performance at C to 125 C is assured by design, characterization, and statistica 31fd 3
LT31 ELECTRICAL CHARACTERISTICS process contros. The LT31I is guaranteed over the fu C to 125 C operating junction temperature. Note 11: This IC incudes overtemperature protection that is intended to protect the device during momentary overoad conditions. Junction temperature wi exceed 125 C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reiabiity. TYPICAL PERFORMANCE CHARACTERISTICS DROPOUT VOLTAGE (mv) 5 5 35 3 25 2 15 1 5 Typica Dropout Votage Guaranteed Dropout Votage Dropout Votage T J = 125 C T J = 25 C 2 6 8 1 12 1 16 18 2 OUTPUT CURRENT (ma) DROPOUT VOLTAGE (mv) 6 5 3 2 1 = TEST POINTS T J 125 C T J 25 C 2 6 8 1 12 1 16 18 2 OUTPUT CURRENT (ma) DROPOUT VOLTAGE (mv) 5 5 35 3 25 2 15 1 5 5 I L = 2mA I L = 1mA I L = 1mA I L = 1 A 25 25 5 75 1 125 31 G1 31 G2 31 G3 QUIESCENT CURRENT (μa) 16 1 12 1 8 6 Quiescent Current ADJ Pin Votage Quiescent Current V IN = 6V R L = I L = V SHDN = V IN ADJ PIN VOLTAGE (V) 1.2 1.235 1.23 1.225 1.22 1.215 1.21 I L = 1μA QUIESCENT CURRENT (μa) 16 1 12 1 8 6 T J = 25 C R L = V OUT = 1.22V V SHDN = V IN 2 V SHDN = V 1.25 2 V SHDN = V 5 25 25 5 75 1 125 1.2 5 25 25 5 75 1 125 1 2 3 5 6 7 8 9 1 INPUT VOLTAGE (V) 31 G 31 G5 31 G6 31fd
TYPICAL PERFORMANCE CHARACTERISTICS LT31 GND PIN CURRENT (μa) 1 9 8 7 6 5 3 2 1 GND Pin Current GND Pin Current vs I LOAD SHDN Pin Threshod T J = 25 C *FOR V OUT = 1.22V R L = 61 I L = 2mA* R L = 122 I L = 1mA* R L = 1.22k I L = 1mA* 1 2 3 5 6 7 8 9 1 INPUT VOLTAGE (V) 31 G7 GND PIN CURRENT (μa) 1 9 8 7 6 5 3 2 1 V IN = 3.3V T J = 25 C V OUT = 1.22V 2 6 8 1 12 1 16 18 2 OUTPUT CURRENT (ma) 31 G8 SHDN PIN THRESHOLD (V) 2. 1.8 1.6 1. 1.2 1..8.6..2 5 25 25 5 75 1 125 31 G9 SHDN PIN CURRENT (μa) 1.2 1..8.6..2 SHDN Pin Current SHDN Pin Current ADJ Pin Bias Current T J = 25 C CURRENT FLOWS OUT OF SHDN PIN SHDN PIN CURRENT (μa) 1.6 1. 1.2 1..8.6..2 V SHDN = V CURRENT FLOWS OUT OF SHDN PIN ADJ PIN BIAS CURRENT (na) 1 12 1 8 6 2.5 1 1.5 2 2.5 3 3.5 SHDN PIN VOLTAGE (V) 5 25 25 5 75 1 125 5 25 25 5 75 1 125 31 G1 31 G11 31 G12 CURRENT LIMIT (ma) 8 7 6 5 3 2 1 Current Limit Current Limit Reverse Output Current V OUT = V T J = 25 C 2 6 8 1 12 1 16 18 2 INPUT VOLTAGE (V) CURRENT LIMIT (ma) 1 9 8 7 6 5 3 2 1 5 V IN = 7V V OUT = V 25 25 5 75 1 125 REVERSE OUTPUT CURRENT (μa) 5 5 35 3 25 2 15 1 5 T J = 25 C V IN = V V OUT = V ADJ CURRENT FLOWS INTO OUTPUT PIN ADJ PIN ESD CLAMP 1 2 3 5 6 7 8 9 1 OUTPUT VOLTAGE (V) 31 G13 31 G1 31 G15 31fd 5
LT31 TYPICAL PERFORMANCE CHARACTERISTICS REVERSE OUTPUT CURRENT (μa) 8 7 6 5 3 2 1 Reverse Output Current Input Rippe Rejection Input Rippe Rejection V IN = V V OUT = V ADJ = 1.22V RIPPLE REJECTION (db) 72 7 68 66 6 62 6 58 V IN = 7V +.5V P-P RIPPLE AT f = 12Hz I L = 2mA RIPPLE REJECTION (db) 8 7 6 5 3 2 1 V IN = 7V + 5mV RMS RIPPLE I L = 2mA C OUT =.7μF C OUT =.7μF 5 25 25 5 75 1 125 56 5 25 25 5 75 1 125 1 1 1k 1k 1k 1M FREQUENCY (Hz) 31 G16 31 G17 31 G18 MINIMUM INPUT VOLTAGE (V) 3.5 3. 2.5 2. 1.5 1..5 5 Minimum Input Votage Load Reguation Output Noise Spectra Density I LOAD = 2mA 25 25 5 75 1 125 31 G19 LOAD REGULATION (mv) 5 1 15 2 25 3 35 5 I L = 1μA TO 2mA V OUT = 1.22V 25 25 5 75 1 125 31 G2 OUTPUT NOISE SPECTRAL DENSITY ( V/ Hz) 1 1.1 C OUT =.7μF I L = 2mA V OUT = 1.22V.1 1 1 1k 1k 1k FREQUENCY (Hz) 31 G21 1Hz to 1kHz Output Noise Transient Response V OUT 2μV/DIV C OUT =.7μF I L = 2mA V OUT = 1.22V 1ms/DIV 31 G22 OUTPUT VOLTAGE DEVIATION (V) LOAD CURRENT (ma)..2.2. 6 2 V IN = 7V V OUT = 5V C IN = C OUT =.7μF CERAMIC I LOAD = 1mA TO 5mA 2 6 8 1 TIME (μs) 31 G23 6 31fd
PIN FUNCTIONS (SOT-23 Package/DD Package) IN (Pin 1/Pin 8): Input. Power is suppied to the device through the IN pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main input fi ter capacitor. In genera, the output impedance of a battery rises with frequency, so it is advisabe to incude a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of.1μf to 1μF is sufficient. The LT31 is designed to withstand reverse votages on the IN pin with respect to ground and the OUT pin. In the case of a reversed input, which can happen if a battery is pugged in backwards, the LT31 wi act as if there is a diode in series with its input. There wi be no reverse current fow into the LT31 and no reverse votage wi appear at the oad. The device wi protect both itsef and the oad. GND (Pin 2/Pins, 9): Ground. SHDN (Pin 3/Pin 5): Shutdown. The SHDN pin is used to put the LT31 into a ow power shutdown state. The output wi be off when the SHDN pin is pued ow. The SHDN pin can be driven either by 5V ogic or open-coector LT31 ogic with a pu-up resistor. The pu-up resistor is ony required to suppy the pu-up current of the open-coector gate, normay severa microamperes. If unused, the SHDN pin must be tied to IN or to a ogic high. ADJ (Pin /Pin 2): Adjust. This is the input to the error ampifier. This pin is internay camped to ±7V. It has a bias current of na which fows into the pin (see curve of ADJ Pin Bias Current vs Temperature in the Typica Performance Characteristics). The ADJ pin votage is 1.22V referenced to ground, and the output votage range is 1.22V to 6V. OUT (Pin 5/Pin 1): Output. The output suppies power to the oad. A minimum output capacitor of.7μf is required to prevent osciations. Larger output capacitors wi be required for appications with arge transient oads to imit peak votage transients. See the Appications Information section for more information on output capacitance and reverse output characteristics. 31fd 7
LT31 APPLICATIONS INFORMATION The LT31 is a 2mA high votage ow dropout reguator with micropower quiescent current and shutdown. The device is capabe of suppying 2mA at a dropout votage of 35mV. The ow operating quiescent current (7μA) drops to 1μA in shutdown. In addition to the ow quiescent current, the LT31 incorporates severa protection features which make it idea for use in battery-powered systems. The device is protected against both reverse input and reverse output votages. In battery backup appications where the output can be hed up by a backup battery when the input is pued to ground, the LT31 acts ike it has a diode in series with its output and prevents reverse current f ow. Adjustabe Operation The LT31 has an output votage range of 1.22V to 6V. The output votage is set by the ratio of two externa resistors as shown in Figure 1. The device servos the output to maintain the votage at the adjust pin at 1.22V referenced to ground. The current in R1 is then equa to 1.22V/R1 and the current in R2 is the current in R1 pus the ADJ pin bias current. The ADJ pin bias current, na at 25 C, f ows through R2 into the ADJ pin. The output votage can be cacuated using the formua in Figure 1. The vaue of R1 shoud be ess than 1.62M to minimize errors in the output votage caused by the ADJ pin bias current. Note that in shutdown the output is turned off and the divider current wi be zero. The device is tested and specified with the ADJ pin tied to the OUT pin and a 5μA DC oad (uness otherwise specified) for an output votage of 1.22V. Specifi cations for output votages greater than 1.22V wi be proportiona to the ratio of the desired output votage to 1.22V (V OUT /1.22V). For exampe, oad reguation for an output current change of 1mA to 2mA 8 V IN IN OUT LT31 ADJ GND R2 R1 V R2 OUT = 1.22V 1 + + (I ADJ )(R2) R1 V ADJ = 1.22V I ADJ = na AT 25 C OUTPUT RANGE = 1.22V TO 6V Figure 1. Adjustabe Operation + V OUT 31 F1 is 13mV typica at V OUT = 1.22V. At V OUT = 12V, oad reguation is: (12V/1.22V) ( 13mV) = 128mV Output Capacitance and Transient Response The LT31 is designed to be stabe with a wide range of output capacitors. The ESR of the output capacitor affects stabiity, most notaby with sma capacitors. A minimum output capacitor of.7μf with an ESR of 3Ω or ess is recommended to prevent osciations. The LT31 is a micropower device and output transient response wi be a function of output capacitance. Larger vaues of output capacitance decrease the peak deviations and provide improved transient response for arger oad current changes. Bypass capacitors, used to decoupe individua components powered by the LT31, wi increase the effective output capacitor vaue. Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dieectrics, each with different behavior across temperature and appied votage. The most common dieectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dieectrics are good for providing high capacitances in a sma package, but they tend to have strong votage and temperature coefficients as shown in Figures 2 and 3. When used with a 5V reguator, a 16V 1μF Y5V capacitor can exhibit an effective vaue as ow as 1μF to 2μF for the DC bias votage appied and over the operating temperature range. The X5R and X7R dieectrics resut in more stabe characteristics and are more suitabe for use as the output capacitor. The X7R type has better stabiity across temperature, whie the X5R is ess expensive and is avaiabe in higher vaues. Care sti must be exercised when using X5R and X7R capacitors; the X5R and X7R codes ony specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can sti be significant enough to drop capacitor vaues beow appropriate eves. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating votage shoud be verified. 31fd
APPLICATIONS INFORMATION Votage and temperature coefficients are not the ony sources of probems. Some ceramic capacitors have a piezoeectric response. A piezoeectric device generates votage across its terminas due to mechanica stress, simiar to the way a piezoeectric acceerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or therma transients. CHANGE IN VALUE (%) 2 2 6 8 BOTH CAPACITORS ARE 16V, 121 CASE SIZE, 1μF 1 2 6 8 1 12 1 DC BIAS VOLTAGE (V) 31 F2 Figure 2. Ceramic Capacitor DC Bias Characteristics Therma Considerations The power handing capabiity of the device wi be imited by the maximum rated junction temperature (125 C). The power dissipated by the device wi be made up of two components: 1. Output current mutipied by the input/output votage differentia: I OUT (V IN V OUT ) and, 2. GND pin current mutipied by the input votage: I GND V IN. The GND pin current can be found by examining the GND Pin Current curves in the Typica Performance Characteristics. Power dissipation wi be equa to the sum of the two components isted above. The LT31 reguator has interna therma imiting designed to protect the device during overoad conditions. For continuous norma conditions the maximum junction temperature rating of 125 C must not be exceeded. It is important to give carefu consideration to a sources of therma resistance from junction to ambient. Additiona heat sources mounted nearby must aso be considered. X5R Y5V 16 Tabe 1. SOT-23 Measured Therma Resistance COPPER AREA TOPSIDE BACKSIDE BOARD AREA LT31 For surface mount devices, heat sinking is accompished by using the heat spreading capabiities of the PC board and its copper traces. Copper board stiffeners and pated through-hoes can aso be used to spread the heat generated by power devices. The foowing tabe ists therma resistance for severa different board sizes and copper areas. A measurements were taken in sti air on 3/32 FR- board with one ounce copper. THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 25 sq mm 25 sq mm 25 sq mm 125 C/W 1 sq mm 25 sq mm 25 sq mm 125 C/W 225 sq mm 25 sq mm 25 sq mm 13 C/W 1 sq mm 25 sq mm 25 sq mm 135 C/W 5 sq mm 25 sq mm 25 sq mm 15 C/W Tabe 2. DFN Measured Therma Resistance COPPER AREA TOPSIDE BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 25 sq mm 25 sq mm 25 sq mm C/W 1 sq mm 25 sq mm 25 sq mm 5 C/W 225 sq mm 25 sq mm 25 sq mm 5 C/W 1 sq mm 25 sq mm 25 sq mm 62 C/W For the DFN package, the therma resistance junction-tocase (θ JC ), measured at the Exposed Pad on the back of the die, is 16 C/W. CHANGE IN VALUE (%) 2 2 6 X5R Y5V 8 BOTH CAPACITORS ARE 16V, 121 CASE SIZE, 1μF 1 5 25 25 5 75 1 125 31 F3 Figure 3. Ceramic Capacitor Temperature Characteristics 31fd 9
LT31 APPLICATIONS INFORMATION Continuous operation at arge input/output votage differentias and maximum oad current is not practica due to therma imitations. Transient operation at high input/output differentias is possibe. The approximate therma time constant for a 25sq mm 3/32" FR- board with maximum topside and backside area for one ounce copper is 3 seconds. This time constant wi increase as more therma mass is added (i.e. vias, arger board, and other components). For an appication with transient high power peaks, average power dissipation can be used for junction temperature cacuations as ong as the puse period is significanty ess than the therma time constant of the device and board. Cacuating Junction Temperature Exampe 1: Given an output votage of 5V, an input votage range of 2V to 3V, an output current range of ma to 2mA, and a maximum ambient temperature of 5 C, what wi the maximum junction temperature be? The power dissipated by the device wi be equa to: I OUT(MAX) (V IN(MAX) V OUT ) + (I GND V IN(MAX) ) where: I OUT(MAX) = 2mA V IN(MAX) = 3V I GND at (I OUT = 2mA, V IN = 3V) =.55mA So: P = 2mA (3V 5V) + (.55mA 3V) =.52W The therma resistance for the DFN package wi be in the range of C/W to 62 C/W depending on the copper area. So the junction temperature rise above ambient wi be approximatey equa to:.52w 5 C/W = 26 C The maximum junction temperature wi then be equa to the maximum junction temperature rise above ambient pus the maximum ambient temperature or: T JMAX = 5 C + 26 C = 76 C Exampe 2: Given an output votage of 5V, an input votage of 8V that rises to 72V for 5ms(max) out of every 1ms, and a 5mA oad that steps to 2mA for 5ms out of every 25ms, what is the junction temperature rise above ambient? Using a 5ms period (we under the time constant of the board), power dissipation is as foows: P1(8V in, 5mA oad) = 5mA (8V 5V) + (1μA 8V) =.22W P2(8V in, 2mA oad) = 2mA (8V 5V) + (.55mA 8V) =.89W P3(72V in, 5mA oad) = 5mA (72V 5V) + (1μA 72V) =.3W P(72V in, 2mA oad) = 2mA (72V 5V) + (.55mA 72V) = 1.38W Operation at the different power eves is as foows: 76% operation at P1, 19% for P2, % for P3, and 1% for P. P EFF = 76%(.22W) + 19%(.89W) + %(.3W) + 1%(1.38W) =.36W With a therma resistance in the range of C/W to 62 C/W, this transates to a junction temperature rise above ambient of 2 C. 1 31fd
LT31 APPLICATIONS INFORMATION Protection Features The LT31 incorporates severa protection features which make it idea for use in battery-powered circuits. In addition to the norma protection features associated with monoithic reguators, such as current imiting and therma imiting, the device is protected against reverse-input votages, and reverse votages from output to input. Current imit protection and therma overoad protection are intended to protect the device against current overoad conditions at the output of the device. For norma operation, the junction temperature shoud not exceed 125 C. The input of the device wi withstand reverse votages of 8V. Current f ow into the device wi be imited to ess than 6mA (typicay ess than 1μA) and no negative votage wi appear at the output. The device wi protect both itsef and the oad. This provides protection against batteries which can be pugged in backward. The ADJ pin can be pued above or beow ground by as much as 7V without damaging the device. If the input is eft open circuit or grounded, the ADJ pin wi act ike an open circuit when pued beow ground, and ike a arge resistor (typicay 1k) in series with a diode when pued above ground. If the input is powered by a votage source, puing the ADJ pin beow the reference votage wi cause the device to current imit. This wi cause the output to go to an unreguated high votage. Puing the ADJ pin above the reference votage wi turn off a output current. In situations where the ADJ pin is connected to a resistor divider that woud pu the ADJ pin above its 7V camp votage if the output is pued high, the ADJ pin input current must be imited to ess than 5mA. For exampe, a resistor divider is used to provide a reguated 1.5V output from the 1.22V reference when the output is forced to 6V. The top resistor of the resistor divider must be chosen to imit the current into the ADJ pin to ess than 5mA when the ADJ pin is at 7V. The 53V difference between the OUT and ADJ pins divided by the 5mA maximum current into the ADJ pin yieds a minimum top resistor vaue of 1.6k. In circuits where a backup battery is required, severa different input/output conditions can occur. The output votage may be hed up whie the input is either pued to ground, pued to some intermediate votage, or is eft open circuit. Current fow back into the output wi foow the curve shown in Figure. The rise in reverse output current above 7V occurs from the breakdown of the 7V camp on the ADJ pin. With a resistor divider on the reguator output, this current wi be reduced depending on the size of the resistor divider. When the IN pin of the LT31 is forced beow the OUT pin or the OUT pin is pued above the IN pin, input current wi typicay drop to ess than 2μA. This can happen if the input of the LT31 is connected to a discharged (ow votage) battery and the output is hed up by either a backup battery or a second reguator circuit. The state of the SHDN pin wi have no effect on the reverse output current when the output is pued above the input. REVERSE OUTPUT CURRENT (μa) 5 5 35 3 25 2 15 1 5 T J = 25 C V IN = V V OUT = V ADJ CURRENT FLOWS INTO OUTPUT PIN ADJ PIN ESD CLAMP 1 2 3 5 6 7 8 9 1 OUTPUT VOLTAGE (V) 31 F Figure. Reverse Output Current 31fd 11
LT31 TYPICAL APPLICATIONS 5V Buck Converter with Low Current Keep Aive Backup D2 D1N91 V IN 5.5V* TO 6V C3.7μF 1V CERAMIC 15 1 V IN SHDN SYNC GND 6 BOOST LT1766 1, 8, 9, 16 SW BIAS FB V C 2 1 12 11 C C 1nF C2.33μF D1 1MQ6N L1 15μH R1 15.k R2.99k + C1 1μF 1V SOLID TANTALUM V OUT 5V 1A/2mA OPERATING CURRENT LOW HIGH IN OUT LT31 SHDN ADJ GND 3.92M 1.27M * FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY INCREASE L1 TO 3μH FOR LOAD CURRENTS ABOVE.6A AND TO 6μH ABOVE 1A 31 TA3 Buck Converter Effi ciency vs Load Current 1 9 V OUT = 5V L = 68μH V IN = 1V EFFICIENCY (%) 8 7 V IN = 2V 6 5.25.5.75 1. 1.25 LOAD CURRENT (A) 31 TA 12 31fd
TYPICAL APPLICATIONS LT31 Automotive Appication LT31 V IN 12V (LATER 2V) + 1μF NO PROTECTION DIODE NEEDED! IN LT31 SHDN GND OUT ADJ R1 R2 1μF LOAD: CLOCK, SECURITY SYSTEM ETC OFF ON LT31 Teecom Appication V IN 8V (72V TRANSIENT) 1μF IN OUT LT31 SHDN ADJ GND R1 R2 NO PROTECTION DIODE NEEDED! 1μF LOAD: SYSTEM MONITOR ETC + BACKUP BATTERY OFF ON 31 TA5 Constant Brightness for Indicator LED over Wide Input Votage Range RETURN OFF ON 8V 1μF IN OUT LT31 SHDN ADJ GND I LED = 1.22V/R SET 8V CAN VARY FROM 3.3V TO 8V R SET 31 TA6 1μF 31fd 13
LT31 PACKAGE DESCRIPTION S5 Package 5-Lead Pastic TSOT-23 (Reference LTC DWG # 5-8-1635).62 MAX.95 REF 2.9 BSC (NOTE ) 1.22 REF 3.85 MAX 2.62 REF 1. MIN 2.8 BSC 1.5 1.75 (NOTE ) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR.95 BSC.3.5 TYP 5 PLCS (NOTE 3).8.9.2 BSC DATUM A 1. MAX.1.1.3.5 REF.9.2 NOTE: (NOTE 3) 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED.25mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.9 BSC S5 TSOT-23 32 REV B 1 31fd
PACKAGE DESCRIPTION DD Package 8-Lead Pastic DFN (3mm 3mm) (Reference LTC DWG # 5-8-1698) LT31.675.5 3.5.5 2.15.5 1.65.5 (2 SIDES) PACKAGE OUTLINE.25.5.5 BSC 2.38.5 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R =.115 TYP 5 8.38.1 PIN 1 TOP MARK (NOTE 6).2 REF 3..1 ( SIDES).75.5..5 1.65.1 (2 SIDES).25.5 2.38.1 (2 SIDES) BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 1.5 BSC (DD) DFN 123 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 31fd 15
LT31 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1129 7mA, Micropower, LDO V IN :.2V to 3V, V OUT(MIN) = 3.75V, V DO =.V, I Q = 5μA, I SD = 16μA, DD, SOT-223, S8, TO22, TSSOP-2 Packages LT1175 5mA, Micropower Negative LDO V IN : 2V to.3v, V OUT(MIN) = 3.8V, V DO =.5V, I Q = 5μA, I SD = 1μA, DD, SOT-223, S8 Packages LT1185 3A, Negative LDO V IN : 35V to.2v, V OUT(MIN) = 2.V, V DO =.8V, I Q = 2.5mA, I SD <1μA, TO22-5 Package LT1761 1mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 2μA, I SD <1μA, ThinSOT Package LT1762 15mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 25μA, I SD <1μA, MS8 Package LT1763 5mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 3μA, I SD <1μA, S8 Package LT176/LT176A 3A, Low Noise, Fast Transient Response, LDO V IN : 2.7V to 2V, V OUT(MIN) = 1.21V, V DO =.3V, I Q = 1mA, I SD <1μA, DD, TO22 Packages LTC18 15mA, Very Low Dropout LDO V IN : 1.6V to 6.5V, V OUT(MIN) = 1.25V, V DO =.8V, I Q = μa, I SD <1μA, ThinSOT Package LT1962 3mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.27V, I Q = 3μA, I SD <1μA, MS8 Package LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO V IN : 2.1V to 2V, V OUT(MIN) = 1.21V, V DO =.3V, I Q = 1mA, I SD <1μA, DD, TO22, SOT Packages LT196 2mA, Low Noise Micropower, Negative LDO V IN : 1.9V to 2V, V OUT(MIN) = 1.21V, V DO =.3V, I Q = 3μA, I SD = 3μA, ThinSOT Package LT31 5mA, 8V, Low Noise Micropower, LDO V IN : 3V to 8V, V OUT(MIN) = 1.28V, V DO =.3V, I Q = 3μA, I SD <1μA, MS8E Package LT32 1mA, Low V IN, Low V OUT Micropower, VLDO V IN :.9V to 1V, V OUT(MIN) =.2V, V DO =.15V, I Q = 12μA, I SD <1μA, DFN, MS8 Packages LT323 Dua 1mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = μa, I SD <1μA, DFN, MS1 Packages LT32 Dua 1mA/5mA, Low Noise Micropower, LDO V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 6μA, I SD <1μA, DFN, TSSOP-16E Packages LT327 Dua 1mA, Low Noise LDO with Independent Inputs V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = μa, I SD <1μA, DFN, MS1E Packages LT328 Dua 1mA/5mA, Low Noise LDO with Independent Inputs V IN : 1.8V to 2V, V OUT(MIN) = 1.22V, V DO =.3V, I Q = 6μA, I SD <1μA, DFN, TSSOP-16E Packages 16 LT 88 REV D PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA 9535-717 (8) 32-19 FAX: (8) 3-57 www.inear.com LINEAR TECHNOLOGY CORPORATION 25 31fd