An Efficient keeper technique for dynamic logic circuits

An Efficient keeper technique for dynamic logic circuits Salendra.Govindarajulu 1 Associate Professor, ECE RGMCET, JNTU Nandyal, A.P, India Email: rajulusg06@yahoo.co.in Kuttubadi Noorruddin 2 M.Tech Student, ECE RGMCET, JNTU Nandyal, A.P, India Email: nooruddink@gmail.com Abstract Dynamic domino logic circuits are widely used in modern digital VLSI circuits. The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers can no longer improve the performance of wide dynamic gates for the future technologies. In this work, an adaptive keeper technique called rate sensing keeper(rsk)that enables faster switching and tracks the variation across different process corners is proposed. The switching speed increased faster than conventional feedback keepers. The delay tracking reduced critical path delay across different process corners, enhancing evaluation speed and noise immunity in domino logic circuits in 65 nm deep submicron technology (DSM). The proposed techniques are compared by performing detailed transistor simulations on benchmark circuits such as 16-bit, 8-bit and 4-bit Multiplexer, 8-bit,4-Bit,2-bit OR and AND Gates, using Microwind 3 and DSCH3 CMOS layout CAD tools. Keywords- CMOS, Critical path delay, DSM technology, Domino logic, Dynamic power, Evaluation, Keeper,Leakage, Power dissipation, Process corner, Rate sensing. I. INTRODUCTION The power consumed in high performance microprocessors has increased to levels that impose a fundamental limitation to increasing performance and functionality [1] [3]. If the current trend in increasing power continues, high performance microprocessors will soon consume thousands of watts. The power density of a high performance microprocessor will exceed the power density levels encountered in typical rocket nozzles within the next decade [2]. The generation, distribution, and dissipation of power are at the forefront of current problems faced by the integrated circuit industry [1] [5]. The application of aggressive circuit design techniques which only focus on enhancing circuit speed without considering power is no longer an acceptable approach in most high complexity digital systems. Dynamic switching power, the dominant component of the total power consumed in current CMOS technologies, is quadratically reduced by lowering the supply voltage. Lowering the supply voltage, however, degrades circuit speed due to reduced transistor currents. Threshold voltages are scaled to reduce the degradation in speed caused by supply voltage scaling while maintaining the dynamic power consumption within acceptable levels [1] [5]. At reduced threshold voltages, however, subthreshold leakage currents increase exponentially. Energy efficient circuit techniques aimed at lowering leakage currents are, therefore, highly desirable. Domino logic circuit techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics of domino CMOS circuits as compared to static CMOS circuits [7] [8]. However, deep sub micrometer (DSM) domino logic circuits utilizing low power supply and threshold voltages have decreased noise margins [9] [11]. As on-chip noise becomes more severe with technology scaling and increasing operating frequencies, error free operation of domino logic circuits has become a major challenge [9], [10], [11]. The focus of this paper is to implement Rate Sensing Keeper domino logic circuit techniques which offer reduced power, critical delay and decreased area in DSM technology. The organization of the paper is as follows. A brief review of the sources of power dissipation in CMOS circuits is provided in Section II. In Section III, various existing keeper techniques are revised. In Section IV Proposed Technique using domino logic is explained and circuits for power reduction are proposed. In Section V simulation and implementation results are presented. Finally, conclusions are presented insection VI. II. SOURCES OF The power consumed by CMOS circuits can be classified into two categories: A. Dynamic Power Dissipation For a fraction of an instant during the operation of a circuit, both the PMOS and NMOS devices are on simultaneously. The duration of the interval depends on the input and output transition (rise and fall) times. During this time, a path exists between V DD and G nd and a short-circuit current flows. 34

However, this is not the dominant factor in dynamic power dissipation. The major component of dynamic power dissipation arises from transient switching behavior of the nodes. Signals in CMOS devices transition back and forth between the two logic levels, resulting in the charging and discharging of parasitic capacitances in the circuit. Dynamic power dissipation is proportional to the square of the supply voltage. In deep sub-micron processes, supply voltages and threshold voltages for MOS transistors are greatly reduced. This, to an extent, reduces the dynamic power dissipation. B. Static Power Dissipation This is the power dissipation due to leakage currents which flow through a transistor when no transactions occur and the transistor is in a steady state. Leakage power depends on gate length and oxide thickness. It varies exponentially with threshold voltage and other parameters. Reduction of supply voltages and threshold voltages for MOS transistors, which helps to reduce dynamic power dissipation, becomes disadvantageous in this case. The subthreshold leakage current increases exponentially, thereby increasing static power dissipation. III. CIRCUIT S Dynamic domino logic circuits are widely used in modern VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic. An ideal keeper is expected to have minimum contention, good noise robustness, good process tracking, less power and area overhead and should support wide fan-in gates. The existing keeper techniques [14] [27] try to trade off one characteristic to gain in the other. Standard Keeper Technique(SKP):It uses a single pmos keeper Disadvantage: The impact of keeper upsizing on the delay and robustness of a larger circuits. Disadvantage: The above advantage comes at the cost of a significant amount of power dissipated in the inverter chain and NAND gate that are used to generate the delay. Fig. 2. Wide AND-OR domino gate with a conditional keeper and a pair of invertersto delay the keeper activation. Current Mirror-based Keeper Technique[16](LCRK): It consists of a replica transistor whose width is a safety factor times the total nmos pull down logic width. The gate of this transistor is connected to source and the leakage current is mirrored to the dynamic node through the pmos current mirror transistors. Fig.3.Wide AND-OR domino gate with a current mirror keeper. Advantage: This technique provides excellent tracking of the Delay. Disadvantage: the contention is still high because the keeper is strongly ON during the beginning of the evaluation phase. High speed feedback keeper technique[15](hsfbk): This is a variation of conditional keeper technique,in this weak keeper is removed. Advantage: it increases the speed of the domino gate. Disadvantage: noise immunity is reduced. Fig. 1. Conventional K-bit wide dynamic MUX with the standard keeper,pk0. Conditional Keeper Technique[14](CKP): It uses a weak keeper and a strong keeper. a weak keeper holds the state of the dynamic node during the transition window (when nmos logic pulls down)and a strong keeper is conditionally activated based on the state of the dynamic node after a certain delay(fig.2) Advantage: This reduces contention during the evaluation period, thereby enabling high speed and reducing the short circuit power dissipation. Fig. 4. An 8-input HS-Domino OR gate. 35

IV. PROPOSED We proposed Rate Sensing Keeper Technique which is superior to conditional keeper in terms of speed and power, while providing a very good process tracking capability comparable to current mirror-based keeper. RATE SENSING KEEPER (): The Rate Sensing Keeper () technique works based on the difference in the rate of change of voltage at the dynamic node of the gate during the ON(R dynon) and the leakage(r dyoff ) condition.r dynon represents the slowest pull down rate when the dynamic gate is ON ( when AN=BN=1 and all other inputs=0)and R dynoff represents the fastest pull down rate when the dynamic gate is leaky(off)(in fig-5 when A1... N=0 and B1.. N=1). The Rate Sensing Technique generates a reference rate which is in between two rates. This Reference rate is then compared with the dynamic node rate using a rate controller, the output of which is used to control the state of the keeper. The fact that the keeper is OFF during the start of the evaluation phase and the adaptive control of the keeper strength based on the process corner helps RSK to achieve higher speed and better tracking, respectively. Fig. 5 shows a wide AND-OR domino gate with the proposed keeper technique. The circuit consists of the keeper pmos transistor (M1), the rate controller comprising of the reference Fig.5.A N-input AND-OR domino gate using the proposed rate sensing keeper technique. rate generator transistor (M4), the feedback transistor (M2), feedback shutoff transistor (M5), clock shutoff transistor (M6),and the precharge transistor (M3).The reference rate is generated by biasing the transistor M4 using an appropriatebias voltage (VBIAS). The sense node (VSEN) is prechargedto VDD during the precharge phase causing M1 to shut offduring the start of the evaluation phase. This reduces the contention current to a large extent. The short circuit path during precharge is shutoff by M6.At the start of evaluation, the node VSEN starts discharging at rate R ref.this slowly turns on the keeper M1.However, if R dyn, the rate of change of voltage at the dynamic node Y, is faster than then M2 will pump larger current into the VSEN. The discharge of VSEN is further slowed by M5 shutting off. Thus VSEN will eventually be pulled back to VDD shutting the keeper off. However, if R dyn < R ref then VSEN would discharge completely turning the keeper ON, pulling the dynamic node back to VDD. In case of ON state the output voltage rises momentarily up to the allowed noise margin level given by the Unity Gain DC Noise(UGDN) of the dynamic gate. The discharge rate is chosen such that under all conditions the peak noise voltage at the output exceed this UGDN level. Fig.6. 8-bit Multiplexer using Rate Sensing Keeper Technique. V. SIMULATION RESULTS does not In this work, the benchmark circuits using the stated Five techniques are implemented. The figures of merits used to compare these techniques are power dissipation, critical path delay and power delay product (),area. The benchmark circuits implemented are 8-bit,4-bit Multiplexer, 8-bit,4-bit,2- bit OR gate,2-bit AND Gate. These design styles are compared by performing detailed transistor-level simulations on benchmark circuits using DSCH3 and Microwind3 CAD tool in 65 nm technology. The results of the benchmark circuits for all techniques are given below. Table-1 shows the comparison of all the four existing and proposed techniques for 8-bit Multiplexer. Table-2 shows the comparison of all the techniques for 16-bit Multiplexer. Table-3 shows the comparison of all the techniques for 8-bit OR Gate. Table4 shows the comparison of all the techniques for 4-bit OR Gate,. Table5 shows the comparison of all the techniques for 2-bit And Gate. From the results, it can be observed that the proposed logic techniques provide lower values of power dissipation, propagation delay and power delay product() when compared to the standard domino logic structure. Comparison: TABLE I: simulation results of MUX-8 SKP 0.101 mw 0.204 0.020 85.508 CKP 0.270 mw 0.326 0.088 498.040 LCRK 2.163 mw 0.116 0.250 1352.48 HSFBK 0.224 mw 0.116 0.025 689.841 0.106 mw 0.051 0.005 207.33 36

TABLE II: simulation results of MUX-16 SKP 0.0732mw 0.146 0.016 1115.52 CKP 0.264 mw 0.374 0.098 972.765 LCRK 0.138mw 0.132 0.018 1245.56 HSFBK 0.158mw 0.205 0.032 1191.42 0.111mw 0.115 0.127 539.966 TABLE III: simulation results of OR-8 SKP 0.323 mw 0.030 0.009 61.685 CKP 0.335 mw 0.294 0.098 192.44 LCRK 0.282 mw 0.072 0.020 214.032 HSFBK 0.242 mw 0.084 0.020 208.001 0.129 mw 0.051 0.006 106.98 TABLE IV: simulation results of OR-4 SKP 0.285 mw 0.152 0.043 60.450 CKP 0.280 mw 0.27 0.075 109.255 LCRK 0.283 mw 0.076 0.021 121.673 HSFBK 0.150 mw 0.075 0.011 108.572 0.124 mw 0.043 0.005 106.98 TABLE V: simulation results of AND-2 (p) (µm 2) SKP 0.115 mw 0.058 0.006 51.765 CKP 0.250 mw 0.284 0.071 76.324 LCRK 0.123 mw 0.102 0.012 85.120 HSFBK 0.248 mw 0.102 0.025 75.562 0.030 mw 0.037 0.011 54.781 Performance comparisons of Different Keeper Techniques: Consider 8-Bit Multiplexer implemented with : compared to SKP, power dissipation is increased by 4% and critical delay is reduced by 75%. Compared to CKP power dissipation is reduced by 40% and critical delay is reduced by 84%. Compared to LCRK power dissipation is reduced by 90% and critical delay is reduced by 56%.For HSFBK power dissipation is reduced by 52% and critical delay is reduced by 56%. V. CONCLUSIONS In the deep submicron technology, power and delay must be reduced to increase the efficiency of a circuit. The keeper technique Rate Sensing Keeper is employed to reduce the power and critical delay in dynamic domino logic circuits. The parameter of power,delay and area are calculated for 16-bit, 8-bit Multiplexer and 8-bit,4-bit,2-bit OR Gates and 2-bit and Gate for different techniques using 65nm technology. From the results it can be concluded that the proposed keeper technique which is Rate Sensing Keeper shows good performance when compared to existing keeper techniques. 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