SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

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2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25 C Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 ma Per JESD 7 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A4-A) 200-V Machine Model (A5-A) 000-V Charged-Device Model (C0) description The LV74A devices are hex D-type flip-flops designed for 2-V to 5.5-V V CC operation. These devices are monolithic positive-edgetriggered flip-flops with a direct clear () input. Information at the data (D) inputs meeting the setup time requirements is traferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the traition time of the positive-going edge of the clock pulse. When the clock () input is at either the high or low level, the D-input signal has no effect at the output. SN54LV74A, SN74LV74A SCLS40D APRIL 998 REVISED JANUARY 200 SN54LV74A...J OR W PACKAGE SN74LV74A... D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) D 2D NC 2Q 3D Q D 2D 2Q 3D 3Q GND 2 3 4 5 6 7 8 SN54LV74A... FK PACKAGE (TOP VIEW) Q NC 4Q 6Q 3 2 20 9 4 5 6 7 8 8 7 6 5 4 9 0 2 3 3Q GND NC 6 5 4 3 2 0 9 V CC V CC 6Q 6D 5D 5Q 4D 4Q NC No internal connection 6D 5D NC 5Q 4D TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER SN74LV74AD SN74LV74ADR TOP-SIDE MARKING SOIC D Tube Tape and reel LV74A 40 C to85 C SOP NS Tape and reel SN74LV74ANSR 74LV74A SSOP DB Tape and reel SN74LV74ADBR LV74A TSSOP PW Tape and reel SN74LV74APWR LV74A TVSOP DGV Tape and reel SN74LV74ADGVR LV74A CDIP J Tube SNJ54LV74AJ SNJ54LV74AJ 55 C to 25 C CFP W Tube SNJ54LV74AW SNJ54LV74AW LCCC - FK Tube SNJ54LV74AFK SNJ54LV74AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contai PRODUCTION DATA information current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 200, Texas Itruments Incorporated

SN54LV74A, SN74LV74A SCLS40D APRIL 998 REVISED JANUARY 200 FUNCTION TABLE INPUTS OUTPUT D Q L X X L H H H H L L H L X Q0 logic symbol 9 R C D 2D 3D 4D 5D 6D 3 4 6 3 4 D 2 5 7 0 2 5 Q 2Q 3Q 4Q 5Q 6Q This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-2. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. logic diagram (positive logic) 9 D 3 D C 2 Q R To Five Other Channels Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. 2

SN54LV74A, SN74LV74A SCLS40D APRIL 998 REVISED JANUARY 200 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC.......................................................... 0.5 V to 7 V Input voltage range, V I (see Note ).................................................. 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, V O (see Note )................................................ 0.5 V to 7 V Output voltage range, V O (see Notes and 2).................................. 0.5 V to V CC + 0.5 V Input clamp current, I IK (V I < 0)........................................................... 20 ma Output clamp current, I OK (V O < 0 or V O > V CC )............................................ ±50 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±25 ma Continuous current through V CC or GND................................................... ±50 ma Package thermal impedance, θ JA (see Note 3): D package................................... 73 C/W DB package................................. 82 C/W DGV package............................... 20 C/W NS package................................. 64 C/W PW package................................ 08 C/W Storage temperature range, T stg................................................... 65 C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 5-7. 3

SN54LV74A, SN74LV74A SCLS40D APRIL 998 REVISED JANUARY 200 recommended operating conditio (see Note 4) SN54LV74A SN74LV74A MIN MAX MIN MAX Supply voltage 2 5.5 2 5.5 V VIH VIL High-level input voltage Low-level input voltage = 2 V.5.5 = 2.3 V to 2.7 V 0.7 0.7 = 3 V to 3.6 V 0.7 0.7 = 4.5 V to 5.5 V 0.7 0.7 = 2 V 0.5 0.5 = 2.3 V to 2.7 V 0.3 0.3 = 3 V to 3.6 V 0.3 0.3 = 4.5 V to 5.5 V 0.3 0.3 VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 0 V IOH IOL High-level output current Low-level output current = 2 V 50 50 µa = 2.3 V to 2.7 V 2 2 = 3 V to 3.6 V 6 6 ma = 4.5 V to 5.5 V 2 2 = 2 V 50 50 µa = 2.3 V to 2.7 V 2 2 = 3 V to 3.6 V 6 6 ma = 4.5 V to 5.5 V 2 2 = 2.3 V to 2.7 V 0 200 0 200 t/ v Input traition rise or fall rate = 3 V to 3.6 V 0 00 0 00 /V = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature 55 25 40 85 C NOTE 4: All unused inputs of the device must be held at or GND to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL SN54LV74A SN74LV74A MIN TYP MAX MIN TYP MAX IOH = 50 µa 2 V to 5.5 V 0. 0. IOH = 2 ma 2.3 V 2 2 IOH = 6 ma 3 V 2.48 2.48 IOH = 2 ma 4.5 V 3.8 3.8 IOL = 50 µa 2 V to 5.5 V 0. 0. IOL = 2 ma 2.3 V 0.4 0.4 IOL = 6 ma 3 V 0.44 0.44 IOL = 2 ma 4.5 V 0.55 0.55 II VI = 5.5 V or GND 0 to 5.5 V ± ± µa ICC VI = or GND, IO = 0 5.5 V 20 20 µa Ioff VI or VO = 0 to 5.5 V 0 5 5 µa Ci VI = or GND 3.3 V.7.7 pf V V V V PRODUCT PREVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. 4

SN54LV74A, SN74LV74A SCLS40D APRIL 998 REVISED JANUARY 200 timing requirements over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure ) tw tsu Pulse duration Setup time before TA = 25 C SN54LV74A SN74LV74A MIN TYP MAX MIN MAX MIN MAX low 6 6.5 6.5 high or low 7 7 7 Data 8.5 9.5 9.5 inactive 4 4 4 th Hold time, data after 0.5 0 0 timing requirements over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure ) tw Pulse duration tsu Setup time before TA = 25 C SN54LV74A SN74LV74A MIN TYP MAX MIN MAX MIN MAX low 5 5 5 high or low 5 5 5 Data 5 6 6 inactive 3 3 3 th Hold time, data after 0 0 0 timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) tw Pulse duration tsu Setup time before TA = 25 C SN54LV74A SN74LV74A MIN TYP MAX MIN MAX MIN MAX low 5 5 5 high or low 5 5 5 Data 4.5 4.5 4.5 inactive 2.5 2.5 2.5 th Hold time, data after 0.5 0.5 0.5 switching characteristics over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure ) PARAMETER fmax tpd tpd FROM TO LOAD TA = 25 C SN54LV74A SN74LV74A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX Q Q CL = 5 pf 55* 5* 50* 50 CL = 50 pf 45 90 40 40 CL =5pF 6.3* 7.3* * 9.5* 9.5 8.4* 7.* * 9* 9 8.2 2.9 23.5 23.5 MHz CL = 50 pf 0.8 20.6 23 23 tsk(o) 2 2 * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. 5

SN54LV74A, SN74LV74A SCLS40D APRIL 998 REVISED JANUARY 200 switching characteristics over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure ) PARAMETER fmax tpd tpd FROM TO LOAD TA = 25 C SN54LV74A SN74LV74A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX Q Q CL = 5 pf 95* 70* 80* 80 CL = 50 pf 55 30 50 50 CL =5pF 4.5*.4* * 3.5* 3.5 5.8* * * 3* 3 6 4.9 7 7 MHz CL = 50 pf 7.5 4.5 6.5 6.5 tsk(o).5.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) PARAMETER fmax tpd tpd FROM TO LOAD TA = 25 C SN54LV74A SN74LV74A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX Q Q CL = 5 pf 30* 240* 0* 0 CL = 50 pf 90 80 80 80 CL =5pF 3* 7.6* * 9* 9 4.* 7.2* * 8.5* 8.5 4.2 9.6 MHz CL = 50 pf 5.5 9.2 0.5 0.5 tsk(o) * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, V CC = 3.3 V, C L = 50 pf, T A = 25 C (see Note 5) PARAMETER SN74LV74A MIN TYP MAX VOL(P) Quiet output, maximum dynamic VOL 0.34 0.8 V VOL(V) Quiet output, minimum dynamic VOL 0.3 0.8 V VOH(V) Quiet output, minimum dynamic VOH 3.02 V VIH(D) High-level dynamic input voltage 2.3 V VIL(D) Low-level dynamic input voltage 0.99 V NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance acitance CL =50pF F, f=0mhz 3.3 V 4 5 V 5. pf PRODUCT PREVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. 6

PARAMETER MEASUREMENT INFORMATION SN54LV74A, SN74LV74A SCLS40D APRIL 998 REVISED JANUARY 200 From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) RL = kω S Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh Open Drain S Open GND LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS Input tw VOLTAGE WAVEFORMS PULSE DURATION 0 V Timing Input Data Input tsu th VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 0 V 0 V Input 0 V Output Control 0 V In-Phase Output Out-of-Phase Output tplh tphl tphl VOH VOL tplh VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform S at (see Note B) Output Waveform 2 S at GND (see Note B) tpzl tpzh tplz VOL + 0.3 V VOL tphz VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOH VOH 0.3 V 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr 3, tf 3. D. The outputs are measured one at a time with one input traition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tphl and tplh are the same as tpd. Figure. Load Circuit and Voltage Waveforms 7

MECHANICAL DATA MPDS006C FEBRUARY 996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,3 0,07 M 24 3 0,6 NOM 4,50 4,30 6,60 6,20 Gage Plane 2 A 0 8 0,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,08 DIM PINS ** 4 6 20 24 38 48 56 A MAX 3,70 3,70 5,0 5,0 7,90 9,80,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60,20 407325/E 08/00 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion, not to exceed 0,5 per side. D. Falls within JEDEC: 24/48 Pi MO-53 4/6/20/56 Pi MO-94

MECHANICAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.050 (,27) 0.020 (0,5) 0.04 (0,35) 0.00 (0,25) 8 5 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.57 (4,00) 0.50 (3,8) Gage Plane 4 A 0 8 0.00 (0,25) 0.044 (,2) 0.06 (0,40) Seating Plane 0.069 (,75) MAX 0.00 (0,25) 0.004 (0,0) 0.004 (0,0) DIM PINS ** 8 4 6 A MAX 0.97 (5,00) 0.344 (8,75) 0.394 (0,00) A MIN 0.89 0.337 (4,80) (8,55) 0.386 (9,80) 4040047/E 09/0 NOTES: A. All linear dimeio are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion, not to exceed 0.006 (0,5). D. Falls within JEDEC MS-02

MECHANICAL DATA MSSO002E JANUARY 995 REVISED DECEMBER 200 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,5 M 28 5 5,60 5,00 8,20 7,40 0,25 0,09 Gage Plane 4 0,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,0 DIM PINS ** 4 6 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 0,50 0,50 2,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 2,30 4040065 /E 2/0 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-50

MECHANICAL DATA MTSS00C JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0,9 4 8 4,50 4,30 6,60 6,20 0,5 NOM Gage Plane A 7 0 8 0,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,0 DIM PINS ** 8 4 6 20 24 28 A MAX 3,0 5,0 5,0 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 0/97 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53

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