A Types Feature.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA Output Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process and ircuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 305 D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 D54A74...F PAKAGE D74A74...E OR M PAKAGE (TOP VIEW) LR D LK PRE Q Q GND 2 3 4 5 6 7 4 3 2 0 9 8 V 2LR 2D 2LK 2PRE 2Q 2Q description/ordering information The A74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements is traferred to the outputs on the positive-going edge of the clock pulse. lock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP E Tube D74A74E D74A74E Tube D74A74M 55 to25 SOI M A74M Tape and reel D74A74M96 DIP F Tube D54A74F3A D54A74F3A Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at www.ti.com/sc/package. FUNTION TABLE (each flip-flop) INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is notable; that is, it does not persist when PRE or LR retur to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2002, Texas Itruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFIE BOX 655303 DALLAS, TEXAS 75265
D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 logic diagram, each flip-flop (positive logic) PRE LK TG Q D TG TG TG Q LR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V.......................................................... 0.5 V to 6 V Input clamp current, I IK (V I < 0 or V I > V ) (see Note )..................................... ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note )................................ ±50 ma ontinuous output current, I O (V O = 0 to V ).............................................. ±50 ma ontinuous current through V or GND.................................................. ±00 ma Package thermal impedance, θ JA (see Note 2): E package................................... 80 /W M package.................................. 86 /W Storage temperature range, T stg................................................... 65 to 50 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 5-7. 2 POST OFFIE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditio (see Note 3) D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 TA = 25 55 to 25 40 to 85 UNIT MIN MAX V Supply voltage.5 5.5.5 5.5.5 5.5 V V =.5 V.2.2.2 VIH High-level input voltage V = 3 V 2. 2. 2. V V = 5.5 V 3.85 3.85 3.85 V =.5 V 0.3 0.3 0.3 VIL Low-level input voltage V = 3 V 0.9 0.9 0.9 V V = 5.5 V.65.65.65 VI Input voltage V VO Output voltage V IOH High-level output current V = 4.5 V to 5.5 V 24 24 24 ma IOL Low-level output current V = 4.5 V to 5.5 V 24 24 24 ma t/ v NOTE 3: Input traition rise or fall rate V =.5 V to 3 V 50 50 50 V = 3.6 V to 5.5 V 20 20 20 All unused inputs of the device must be held at V or GND to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating MOS Inputs, literature number SBA004. /V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V TA = 25 55 to 25 40 to 85 UNIT MIN MAX.5 V.4.4.4 IOH = 50 µa 3 V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 VOH VI = VIH or VIL IOH = 4 ma 3 V 2.58 2.4 2.48 V IOH = 24 ma 4.5 V 3.94 3.7 3.8 IOH = 50 ma 5.5 V 3.85 IOH = 75 ma 5.5 V 3.85.5 V 0. 0. 0. IOL = 50 µa 3 V 0. 0. 0. 4.5 V 0. 0. 0. VOL VI = VIH or VIL IOL = 2 ma 3 V 0.36 0.5 0.44 V IOL = 24 ma 4.5 V 0.36 0.5 0.44 IOL = 50 ma 5.5 V.65 IOL = 75 ma 5.5 V.65 II VI = V or GND 5.5 V ±0. ± ± µa I VI = V or GND, IO = 0 5.5 V 4 80 40 µa i 0 0 0 pf Test one output at a time, not exceeding -second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω tramission-line drive capability at 85 and 75-Ω tramission-line drive capability at 25. POST OFFIE BOX 655303 DALLAS, TEXAS 75265 3
D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 timing requirements over recommended operating free-air temperature range, V =.5 V (unless otherwise noted) 55 to 25 40 to 85 UNIT fclock lock frequency 9 0 MHz tw Pulse duration PRE or LR low 50 44 LK 56 49 tsu Setup time Data 44 39 PRE or LR inactive th Hold time Data after LK 0 0 trec Recovery time, before LK LR or PRE 34 30 timing requirements over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure ) 55 to 25 40 to 85 UNIT fclock lock frequency 79 90 MHz tw Pulse duration PRE or LR low 5.6 4.9 LK 6.3 5.5 tsu Setup time Data 4.9 4.3 PRE or LR inactive th Hold time Data after LK 0 0 trec Recovery time, before LK LR or PRE 4.7 4. timing requirements over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) 55 to 25 40 to 85 UNIT fclock lock frequency 0 25 MHz tw Pulse duration PRE or LR low 4 3.5 LK 4.5 3.9 tsu Setup time Data 3.5 3. PRE or LR inactive th Hold time Data after LK 0 0 trec Recovery time, before LK LR or PRE 2.7 2.4 4 POST OFFIE BOX 655303 DALLAS, TEXAS 75265
D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 switching characteristics over recommended operating free-air temperature range, V =.5 V, L = 50 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to 25 40 to 85 UNIT fmax 9 0 MHz LK Q or Q PRE or LR QorQ Q 25 4 25 4 32 20 44 3 switching characteristics over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to 25 40 to 85 UNIT fmax 79 90 MHz LK Q or Q PRE or LR QorQ Q 3.5 4 3.6 2.7 3.5 4 3.6 2.7 3.7 4.7 3.8 3.4 4 6. 4. 4.6 switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to 25 40 to 85 UNIT fmax 0 25 MHz LK Q or Q PRE or LR QorQ Q 2.5 0 2.6 9. 2.5 0 2.6 9. 2.6 0.5 2.7 9.5 2.9.5 3 0.4 operating characteristics, T A = 25 PARAMETER TYP UNIT pd Power dissipation capacitance 55 pf POST OFFIE BOX 655303 DALLAS, TEXAS 75265 5
D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test L = 50 pf (see Note A) R = 500 Ω R2 = 500 Ω S 2 V GND Open TEST / tplz/tpzl tphz/tpzh S Open 2 V GND When V =.5 V, R = R2 = kω LOAD IRUIT Input 50% V tw VOLTAGE WAVEFORMS PULSE DURATION V 50% V LR Input LK 50% V trec 50% V V V Reference Input Data Input 50% 0% 50% V tsu th 90% 90% tr V V 50% V 0% tf VOLTAGE WAVEFORMS REOVERY TIME VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES Input In-Phase Output Out-of-Phase Output 50% V 50% 0% 90% 90% 90% VOH 50% V 0% VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr 50% V 50% V 50% 0% 0% tf V 90% VOH VOL tr Output ontrol Output Waveform S at 2 V (see Note B) Output Waveform 2 S at GND (see Note B) tpzl tpzh 50% V 50% V tplz 50% V 20% V VOL 50% V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES tphz V V VOH 80% V NOTES: A. L includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control.. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 3, tf = 3. Phase relatiohips between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input traition per measurement. F. and are the same as tpd. G. tpzl and tpzh are the same as ten. H. tplz and tphz are the same as tdis. Figure. Load ircuit and Voltage Waveforms 6 POST OFFIE BOX 655303 DALLAS, TEXAS 75265
MEHANIAL DATA MER002 JANUARY 995 REVISED JUNE 999 J (R-GDIP-T**) 4 LEADS SHOWN ERAMI DUAL-IN-LINE DIM PINS ** 4 6 20 4 B 8 A MAX A MIN 0.30 (7,87) 0.290 (7,37) 0.30 (7,87) 0.290 (7,37) 0.30 (7,87) 0.290 (7,37) B MAX B MIN 0.785 (9,94) 0.755 (9,8) 0.785 (9,94) 0.755 (9,8) 0.975 (24,77) 0.930 (23,62) 0.065 (,65) 0.045 (,4) 7 MAX MIN 0.300 (7,62) 0.245 (6,22) 0.300 (7,62) 0.245 (6,22) 0.300 (7,62) 0.245 (6,22) 0.00 (2,54) 0.070 (,78) 0.020 (0,5) MIN A 0.200 (5,08) MAX Seating Plane 0.30 (3,30) MIN 0.023 (0,58) 0.05 (0,38) 0 5 0.00 (2,54) 0.04 (0,36) 0.008 (0,20) 4040083/E 03/99 NOTES: A. All linear dimeio are in inches (millimeters). B. This drawing is subject to change without notice.. This package is hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 835 GDIP-T4, GDIP-T6, and GDIP-T20 POST OFFIE BOX 655303 DALLAS, TEXAS 75265
MEHANIAL MPDI002 JANUARY 995 REVISED DEEMBER 20002 N (R-PDIP-T**) 6 PINS SHOWN PLASTI DUAL-IN-LINE PAKAGE DIM PINS ** 4 6 8 20 A A MAX 0.775 (9,69) 0.775 (9,69) 0.920 (23,37).060 (26,92) 6 9 A MIN 0.745 (8,92) 0.745 (8,92) 0.850 (2,59) 0.940 (23,88) 0.260 (6,60) 0.240 (6,0) MS-00 VARIATION AA BB A AD 0.070 (,78) MAX 8 0.035 (0,89) MAX 0.020 (0,5) MIN 0.325 (8,26) 0.300 (7,62) 0.200 (5,08) MAX 0.05 (0,38) Gauge Plane Seating Plane 0.25 (3,8) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M 0.430 (0,92) MAX 4/8 PIN ONLY 20 pin vendor option D 4040049/E 2/2002 NOTES: A. All linear dimeio are in inches (millimeters). B. This drawing is subject to change without notice.. Falls within JEDE MS-00, except 8 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFIE BOX 655303 DALLAS, TEXAS 75265
MEHANIAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTI SMALL-OUTLINE PAKAGE 8 PINS SHOWN 0.050 (,27) 0.020 (0,5) 0.04 (0,35) 0.00 (0,25) 8 5 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.57 (4,00) 0.50 (3,8) Gage Plane 4 A 0 8 0.00 (0,25) 0.044 (,2) 0.06 (0,40) Seating Plane 0.069 (,75) MAX 0.00 (0,25) 0.004 (0,0) 0.004 (0,0) DIM PINS ** 8 4 6 A MAX 0.97 (5,00) 0.344 (8,75) 0.394 (0,00) A MIN 0.89 0.337 (4,80) (8,55) 0.386 (9,80) 4040047/E 09/0 NOTES: A. All linear dimeio are in inches (millimeters). B. This drawing is subject to change without notice.. Body dimeio do not include mold flash or protrusion, not to exceed 0.006 (0,5). D. Falls within JEDE MS-02 POST OFFIE BOX 655303 DALLAS, TEXAS 75265
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