VMMK-243 2 to 4 GHz GaAs High Linearity LNA in Wafer Level Package Data Sheet Description Avago s VMMK-243 is an easy-to-use, high linearity low noise amplifier in a miniaturized wafer level package (WLP). The low noise and unconditionally stable performance makes this amplifier ideal as a primary or subsequent gain block of an RF receiver in applications from 2 4GHz. A, 38mA power supply is required for optimal performance. This amplifier is fabricated with enhancement E-pHEMT technology and industry leading revolutionary wafer level package. The GaAsCap wafer level sub-miniature leadless package is small and ultra thin yet can be handled and placed with standard 42 pick and place assembly. This product is easy to use since it requires only positive DC voltages for bias and no matching coefficients are required for impedance matching to Ω systems. WLP 42, 1mm x.mm x.2 mm FY Features 1 x. mm Surface Mount Package Ultrathin (.2mm) Unconditionally Stable Ohm and Match RoHS6 + Halogen Free Specifications (Vdd = 3.V, Idd = 37mA) IP3: 28dBm Small-Signal Gain: 16dB Noise Figure: 1.7dB Applications 2.4 GHz, 3.GHz WLAN and WiMax notebook computer, access point and mobile wireless applications 82.16 & 82.2 BWA systems Radar, radio and ECM systems Pin Connections (Top View) FY / Vdd Amp / Vdd Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = V ESD Human Body Model = 67V Refer to Avago Application Note A4R: Electrostatic Discharge, Damage and Control. Note: F = Device Code Y = Month Code
Table 1. Absolute Maximum Ratings [1] Sym Parameters/Condition Unit Absolute Max Vd Supply Voltage (RF ) [2] V Id Device Current [2] ma 6 P in, max CW RF Power (RF ) [3] dbm +2 P diss Total Power Dissipation mw 3 Tch Max channel temperature C 1 θjc Thermal Resistance [4] C/W 16 Notes 1. Operation in excess of any of these conditions may result in permanent damage to this device. 2. Bias is assumed DC quiescent conditions 3. With the DC (typical bias) and RF applied to the device at board temperature Tb = 2 C 4. Thermal resistance is measured from junction to board using IR method Table 2. DC and RF Specifications T A = 2 C, Frequency = 3 GHz, Vd =, Z in = Z out = Ω (unless otherwise specified) Sym Parameters/Condition Unit Minimum Typ. Maximum Id Device Current ma 3 37 4 NF [1,2] Noise Figure db 1.7 2.2 Ga [1,2] Associated Gain db 14 16 17 OIP3 [1,2,3] 3rd Order Intercept dbm +26 +27.8 P-1dB [1,2] Power at 1dB Gain Compression dbm +16. IRL [1,2] Return Loss db -12 ORL [1,2] Return Loss db -12 1. Losses of test systems have been de-embedded from final data 2. Measure Data obtained from wafer-probing 3. OIP3 test condition: F1=3.GHz, F2=3.1GHz, Pin=-2dBm 2
Product Consistency Distribution Charts at 3. GHz, Vd = LSL USL LSL USL.31.33.3.37.39.41.43 Id, LSL=.3 A, Nominal=.37 A, USL=.4 A 1 16 17 Gain @ 3GHz, LSL=14 db, Nominal=16 db, USL=18 db LSL LSL USL 27 28 29 3 OIP3 at 3GHz, LSL=26 dbm, Nominal=27.8 dbm..6.7.8.9 1 1.1 1.2 1.3 1.4 1. 1.6 NF @ 3GHz, Nominal=1.69 db, USL=2.2 db Note: Distribution data based on part sample size from skew lots during initial characterization. Measurements were obtained using 3um G-S production wafer probe. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 3
VMMK-243 Typical Performance (T A = 2 C, Vdd =, Idd = 38mA, Z in = Z out = Ω unless noted) 2 S21 (db) 1 1 NoiseFigure (db) 4 3 2 Figure 1. Small-signal Gain [1] 1 Figure 2. Noise Figure [1] - -1 S11 (db) -1-1 S22 (db) -2-2 Figure 3. Return Loss [1] -3 Figure 4. Return Loss [1] 3 S12 (db) -1-2 IP3 & P1dB (dbm) 2 1-3 Figure. Isolation [1] Figure 6. IP3 & P1dB [1,2] OIP3 OP1dB 1. Data taken on a G-S-G probe substrate fully de-embedded to the reference plane of the package 2. IP3 data taken at Pin=-1dBm 4
VMMK-243 Typical Performance (continue) (T A = 2 C, Vdd =, Idd = 38mA, Z in = Z out = Ω unless noted) 2 8 1 6 S21 (db) 1 Idd (ma) 4 V Figure 7. Gain over Vdd [1] 2 Vdd (V) Figure 8. Total Current [1] S11 (db) -1-2 -3 Figure 9. Return Loss over Vdd [1] V NoiseFigure (db). 4. 3. 2. 1. Figure 1 Noise Figure over Vdd [1] V S22 (db) - -1-1 -2 Figure 11. Return Loss Over Vdd [1] V OP1dB (dbm) 2 1 1 Figure 12. P1dB Over Vdd [1] V 1. Data taken on a G-S-G probe substrate fully de-embedded to the reference plane of the package
VMMK-243 Typical Performance (continue) (T A = 2 C, Vdd =, Idd = 38mA, Z in = Z out = Ω unless noted) 2 3 OP1dB (dbm) 1 1 2C -4C 8C Figure 13. P-1dB over Temp [3] OIP3 (dbm) 3 2 2 1 Figure 14. IP3 Over Vdd [2,3] V S21 (db) 2 1 1 2C 8C -4C Figure 1. Gain over Temp [3] NoiseFigure (db). 4. 3. 2. 1. Figure 16 Noise Figure over Temp [3] -4C 2C 8C S11 (db) -1-2 -3 Figure 17. Return Loss Over Temp [3] 2C -4C 8C S22 (db) -1-2 -3 Figure 18. Return Loss Over Temp [3] 2C 8C -4C 1. Data taken on a G-S-G probe substrate fully de-embedded to the reference plane of the package 2. IP3 data taken at Pin=-1dBm 3. Over temp data taken on a test fixture (Figure 2) without de-embedding 6
VMMK-243 Typical S-parameters T A = 2 C, Vdd =, Idd = 38mA, Z in = Z out = Ω unless noted) Freq GHz S11 S21 S12 S22 Mag db Phase Mag db Phase Mag db Phase Mag db Phase 1.6-3.79 113.2.47 14.76-144.36.4-28.13 87.94.28-11.18-1.64 1..36-8.82 81. 7. 16.97-178.. -24.97 6.7.27-11.46-8.4 2..13-17.4.74 7.16 17.9 1.6.6-24.1 42..24-12.3-87.61 2..3-31.8-133.91 6.71 16.3 134.46.6-23.9 3.73.21-13.69-1.64 3..12-18.13-11. 6.12 1.74 117.9.6-23.97 23.43.2-14.3-1.66 3..2-14. -163.87. 14.88 14..6-24.4 19.19.2-13.96-17.1 4..2-12. -174.32.4 14. 91.92.6-24.14 1.78.22-13.22-16.91 4..29-1.89 17.98 4.8 13.22 81.8.6-24.14 13.3.24-12.42-18.9..31-1.13 167.3 4.19 12.44 71.14.6-24.12 12.4.26-11.8-11.9..33-9.9 19.43 3.84 11.69 61.94.6-24.7 1.81.29-1.73-113.9 6..3-9.16 11.41 3.4 1.97 3.4.6-24.1 9.6.32-9.87-118.4 6..36-8.91 143.69 3.26 1.27 44.7.6-23.89 8.81.3-9.3-123.2 7..37-8.69 136.41 3.2 9.9 36.31.7-23.74 8.13.39-8.27-128.23 7..38-8. 129.27 2.79 8.91 28.19.7-23.8 7.21.42-7.2-133.6 8..38-8.36 122.37 2.8 8.2 2.21.7-23.39 6.48.46-6.81-139.38 8..39-8.21 11.19 2.39 7.6 12.37.7-23.22.74.49-6.17-144.98 9..39-8.12 18.46 2.2 6.8 4.43.7-23.6 4.98.3 -.3-11.26 9..4-7.98 11.84 2.2 6.11-3..7-22.83 4.19.6-4.98-18.1 1..41-7.83 9.4 1.84.3-11.3.7-22.6 3.7.6-4.39-164.68 1..41-7.72 88.39 1.66 4.4-19.19.8-22.34 2.72.64-3.88-172.3 11..42-7.9 82.22 1.48 3.39-26.92.8-22.9 2.6.67-3.42 179.91 11..43-7.42 76.2 1.29 2.22-34.3.8-21.79 1.4.71-2.99 171.62 12..43-7.2 7.1 1.1.82-41.13.8-21.46.4.74-2.67 162.7 7
VMMK-243 Application and Usage (Please always refer to the latest Application Note AN378 in website) Biasing and Operation The VMMK-243 is normally biased with a positive drain supply connected to the output pin through an external bias-tee and with bypass capacitors as shown in Figure 19. The recommended drain supply voltage is 3 V and the corresponding drain current is approximately 38mA. Aspects of the amplifier performance may be improved over a narrower bandwidth by application of additional conjugate, linearity, or low noise (τopt) matching. Size: 1.1 mm x.6 mm (42 component) Amp Figure 19. Usage of the VMMK-243 Ground Vdd Ohm line Ohm line.1 uf 1 pf Bias-Tee Biasing the device at results in slightly lower noise figure. In a typical application, the bias-tee can be constructed using lumped elements. The value of the output inductor can have a major effect on both low and high frequency operation. The demo board uses a 1 nh inductor which provides an optimum value for 2 to 4 GH operation. If operation is desired at frequencies higher than 4 GHz then a smaller value such as 8.2 nh may be required to keep the self resonant frequency higher than the maximum desired frequency of operation. Another approach for broadbanding the VMMK-243 is to series two different value inductors with the smaller value inductor placed closest to the device and favoring the higher frequencies. The larger value inductor will then offer better low frequency performance by not loading the output of the device. The parallel combination of the 1pF and.1uf capacitors provide a low impedance in the band of operation and at lower frequencies and should be placed as close as possible to the inductor. The low frequency bypass provides good rejection of power supply noise and also provides a low impedance termination for third order low frequency mixing products that will be generated when multiple in-band signals are injected into any amplifier. Refer the Absolute Maximum Ratings table for allowed DC and thermal conditions. Figure 2. Evaluation/Test Board (available to qualified customer request) 1 pf Size: 1.1 mm x.6 mm (42 component) Amp Ground Figure 21. Example application of VMMK-243 at 3.GHz Vdd Ohm line Ohm line S Parameter Measurements.1 uf 1 pf 1 nh 1 pf The S-parameters are measured on a.16 inch thick RO43 printed circuit test board, using G-S-G (ground signal ground) probes. Coplanar waveguide is used to provide a smooth transition from the probes to the device under test. The presence of the ground plane on top of the test board results in excellent grounding at the device under test. A combination of SOLT (Short - Open - Load - Thru) and TRL (Thru - Reflect - Line) calibration techniques are used to correct for the effects of the test board, resulting in accurate device S-parameters. The reference plane for the S Parameters is at the edge of the package. The product consistency distribution charts shown on page 2 represent data taken by the production wafer probe station using a 3um G-S wafer probe. The ground-signal probing that is used in production allows the device to be probed directly at the device with minimal common lead inductance to ground. Therefore there will be a slight difference in the nominal gain obtained at the test frequency using the 3um G-S wafer probe versus the 3um G-S-G printed circuit board substrate method. 8
Outline Drawing 1.4 MIN, 1.8 MAX PIN ONE INDICATOR.12.12. MIN,.8 MAX GROUND PAD.47.16 INPUT PAD.39.16 OUTPUT PAD Solderable area of the device shown in yellow. Dimensions in mm. Tolerance ±.1 mm Suggested PCB Material and Land Pattern.1 (.4). (.2) Part of Circuit.76 max (.3) 2pl - see discussion.381 (.1) 2pl 1..1 Rogers RO43 1.2 (.48).2 (.8).2 (.8).4 (.16).1 (.4). (.2).24 dia PTH (.1) 4pl Solder Mask.4 dia (.16) 4pl Part of Circuit.7 (.28) Recommended SMT Attachment The VMMK Packaged Devices are compatible with high volume surface mount PCB assembly processes. Manual Assembly for Prototypes 1. Follow ESD precautions while handling packages. 2. Handling should be along the edges with tweezers or from topside if using a vacuum collet. 3. Recommended attachment is solder paste. Please see recommended solder reflow profile. Conductive epoxy is not recommended. Hand soldering is not recommended. 4. Apply solder paste using either a stencil printer or dot placement. The volume of solder paste will be dependent on PCB and component layout and should be controlled to ensure consistent mechanical and electrical performance. Excessive solder will degrade RF performance.. Follow solder paste and vendor s recommendations when developing a solder reflow profile. A standard profile will have a steady ramp up from room temperature to the pre-heat temp to avoid damage due to thermal shock. 6. Packages have been qualified to withstand a peak temperature of 26 C for 2 to 4 sec. Verify that the profile will not expose device beyond these limits. 7. Clean off flux per vendor s recommendations. 8. Clean the module with Acetone. Rinse with alcohol. Allow the module to dry before testing. 9
Ordering Information Part Number Devices Per Container Container VMMK-243-BLKG 1 Antistatic Bag VMMK-243-TR1G 7 Reel Package Dimension Outline D Die dimension: E A Dim Range Unit D 1.4-1.8 mm E. -.8 mm A.22 -.27 mm Note: All dimensions are in mm Reel Orientation REEL Device Orientation USER FEED DIRECTION 4 mm FY FY FY FY 8 mm USER FEED DIRECTION CARRIER TAPE Note: F = Device Code Y = Month Code TOP VIEW END VIEW 1
Tape Dimensions Note: 2 P2 Do Note: 1 Po B B E T (Max) A A P1 D1 F Note: 2 W Bo Scale :1 B B SECTION Ao R.1 (Max) Ko Scale :1 A A SECTION Ao =.73±. mm Bo = 1.26±. mm Ko =.3 +. mm + Unit: mm Symbol Spec. K1 Po 4.±.1 P1 4.±.1 P2 2.±. Do 1.±. D1.±. E 1.7±.1 F 3.±. 1Po 4.±.1 W 8.±.2 T.2±.2 Notice: 1. 1 Sprocket hole pitch cumulative tolerance is ±.1mm. 2. Pocket position relative to sprocket hole measured as true position of pocket not pocket hole. 3. Ao & Bo measured on a place.3mm above the bottom of the pocket to top surface of the carrier. 4. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier.. Carrier camber shall be not than 1m per 1mm through a length of 2mm. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2-21 Avago Technologies. All rights reserved. AV2-23EN - January 2, 21