INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 6464(Print) ISSN 0976 6472(Online) Volume 4, Issue 3, May June, 2013, pp. 24-32 IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2013): 5.8896 (Calculated by GISI) www.jifactor.com IJECET I A E M E DESIGN & CHARACTERIZATION OF HIGH SPEED POWER EFFICIENT CMOS COMPARATOR Priyesh P. Gandhi 1, Dhanisha N. Kapadia 2, N. M. Devashrayee 3 1 (EC Dept., Institute of Technology, Nirma University, Ahmedabad, India) 2 (EC Dept., L. C. Institute of Technology, Bhandu, Gujarat Technological University Ahmedabad, India) 3 (EC Dept., Institute of Technology, Nirma University, Ahmedabad, India) ABSTRACT In this paper authors have design the High Speed Power Efficient CMOS Voltage Comparator which can be realized in A/D Converters. The simulation is carried out in 130nm and 90nm technologies. The supply voltage for this comparator is 1v and 0.9v for 130nm and 90nm respectively. The Characterization of comparator is done in terms of offset, ICMR, propagation delay, power dissipation in both the technologies and the result has been compared for both the technologies. The simulation results shows that the speed of 1.92GHz and 2.44GHz with the power dissipation of 9.19µW and 7.45µW was achieved in 130nm and 90nm technologies respectively. Index Terms: Buffer stage, Current Sensing Comparator, Latch Comparator. I. INTRODUCTION A Comparator is a circuit which compares the two analog signal and depending on the comparison gives the output either logic 1 or logic 0. The comparators are widely used in ADC. In fact, comparator is also called as 1 bit ADC. In conventional design, in order to reduce the input offset voltage preamplifiers were added before the comparator, but ultimately this increases the power consumption. Therefore, a latched comparator is a good alternative for low power consumption and high-speed operation. There are three types of comparator which can provide high speed, such as multistage open loop comparator, the dynamic latch comparator, and the preamplifier-latch comparator. The multistage open loop 24
comparator can meet high-speed and high-precision, but cannot provide the speed more than 1Gbps, so the dynamic latch comparator is widely utilized to satisfy the need for high-speed. The paper is being divided into six sections. In section 2, current sensing comparator topology and the buffer stage have been discussed. In section 3, authors have discussed about proposed architecture of comparator. In section 4, simulation results are presented. Section 5 includes the comparison of the simulation results in both the technologies. Finally in section 6, conclusion has been discussed. II. DIFFERENTIAL CURRENT SENSING COMPARATOR AND BUFFER STAGE A. Differential Current Sensing Comparator Fig. 1. Differential current sensing comparator[3] Figure-1 shows the schematic of the differential current sensing comparator. Whenever the Clk signal goes low, circuit enters in regenerative mode. Transistor M12 is on and M7 is off. Both nmos M5 and M6 will start conducting when values of both the outputs Out+ and Out- increases above threshold voltage of both transistors, which will connect the outputs with comparing circuit at the input side. Unless and until final state is reached both the outputs have to drive common mode currents, hence it consumes more power. When the CLK signal goes high, the circuit enters in reset mode. The comparing circuit used at the input side consisting of transistors M1, M2, M3 and M4 are used to transfer the difference of the input voltage into differential currents. A pass transistor M7 is used to connect both the outputs together. B. Buffer Stage The circuit diagram of output buffer circuit used in the comparator is shown in Figure-2[4]. The output buffer stage is also called post amplifier. This circuit is self biasing differential amplifier which has differential inputs as Vout+ & Vout- and does not have any slew rate limitations. It is also useful in giving the output in proper shape. 25
Fig.2 The Output Buffer Circuit[4] III. PROPOSED CMOS VOLTAGE COMPARATOR The circuit diagram of the proposed high speed CMOS voltage comparator is as shown in Figure-3. Whenever the Clk signal goes high, the circuit enters in regenerative mode. Transistor M11 and M7 are off and M14 is on. When values of both the outputs Out + and Out - increases above threshold voltage of nmos M5 and M6, both will start conducting which will connect the outputs with comparing circuit at the input side. The comparing circuit used at the input side consisting of transistors M1, M2, M3 and M4 are used to transfer the difference of the input voltage into differential currents. During reset interval, a pass transistor M11 is used to connect both the outputs together. Whenever the Clk signal goes low, transistor M7 and M8 are on. The two nodes which are connected with the drains of M7 and M8 will get reset to V dd. These internal nodes are reset to V dd during the phase when the comparator is not making a decision. This will ensure that all the internal nodes are reset before the comparator goes into decision mode. So the problem associated with previous code dependent biased decision which occurs due to the charge imbalance left from previous decision at one of the nodes of the comparator which affects next decision is thus removed. The two outputs Out+ and Out- of the comparator are being converted into single output with the output buffer circuit so that various analysis can be carried out. Table-I given below shows different widths of the transistor to be used according to the chosen technology. The length for the transistor is 0.13um and 0.1um respectively for 130nm and 90nm technology. TABLE-1. CMOS TRANSISTOR WIDTHS FOR DIFFERENT TECHNOLOGIES Technology Wp(um) Wn(um) 130nm 0.15 0.15 90nm 0.12 0.12 26
Fig.3 Proposed Design of Comparator IV. SIMULATION RESULTS OF PROPOSED COMPARATOR The simulated results are obtained for two different technologies 130nm and 90nm. In Table-II, different voltage values are given for supply voltage VDD and VSS, reference voltage Vref+ and Vref-, input voltage Vin+ and Vin- and Clkb TABLE-II DIFFERENT VOLTAGE VALUES FOR DIFFERENT TECHNOLOGIES Voltage Technology Terminals 130nm 90nm VDD 1v 0.9v VSS -1v -0.9v Clkb -1v -0.9v Vin+ 1v 0.9v Vin- -1v -0.9v Vref+ 0.43v 0.34v Vref- -0.43v -0.34v When sine wave is applied to the comparator as an input, the output will be the square wave as shown in Figure-5 and Figure-9. 27
A. Simulated waveforms in 130nm technology Fig. 5 Sine Wave as an Input Fig. 6 Transient Response 28
Fig. 7 Input Common Mode Range Fig 8 Output Offset voltage 29
B. Simulated waveforms in 90nm technology Fig. 9 Sine Wave as an Input Fig. 10 Transient Response 30
Fig. 11 Input Common Mode Range Fig.12 Output Offset Voltage V. COMPARISON OF DIFFERENT CHARACTERISTICS IN 130NM AND 90NM TECHNOLOGIES In this paper, simulated results are presented for the comparator for two different technologies, 130nm and 90nm. The summary of the comparison for the comparator in both the technologies is given in the Table III. 31
TABLE III SIMULATED RESULTS OF CURRENT SENSING COMPARATOR WITH BUFFER CIRCUIT FOR DIFFERENT TECHNOLOGIES VI. CONCLUSION Parameters Technology 130nm 90nm Propagation Delay(ns) 0.46 0.34 Speed(GHz) 2.17 2.94 ICMR(V) -0.2 to 0.61-0.2 to 0.5 Offset 69mV 0.16 Power Dissipation(uW) 21 10.22 Speed of the comparator which is implemented in 90nm is more than speed of comparator in 130nm. The input common mode range is almost remaining same for both the technologies. With the reduction in technology, the offset voltage is getting increased due to increase in the non-idealities of the transistors and the power dissipation is also reduced with the reduction in the technology. Proposed Comparator has high speed which can be realized in A/D Converters. REFERENCES [1] P. Uthaichana and E. Leelarasmee, "Low Power CMOS Dynamic Latch Comparators," IEEE, pp. 605-608, 2003. [2] Z. Huang and P. Zhong, "An Adaptive Analog-to-Digital Converter Based on Low-Power Dynamic Latch Comparator," IEEE conference, p. 6pp, 2005. [3] Christopher J. Lindsley A Nano-Power Wake-Up Circuit for RF Energy Harvesting Wireless Sensor Networks, M.S. thesis, Dept. Electrical & computer. Eng., Oregon State University 2008. [4] Priyesh P. Gandhi Design & Simulation of Low Power High Speed CMOS Comparator in Deep Sub-micron Technology, M.Tech thesis, Dept. of electronics & communication Eng. Nirma University, 2010. [5] Philip E. Allen and Douglas R. Hallberg. CMOS Analog Circuit Design. Oxford University Press, Inc USA-2002,pp.259-397, 2002 [6] R. Jacob Baker Harry W. Li David E. Boyce. CMOS Circuit Design, Layout and Simulation. IEEE Press Series on Microelectronics Systems, 2005. [7] Dhanisha N. Kapadia and Priyesh P. Gandhi, Design and Simulation of High Speed CMOS Differential Current Sensing Comparator in 0.35 µm and 0.25µm 1 Technologies, International journal of Electronics and Communication Engineering &Technology (IJECET), Volume 3, Issue 3, 2012, pp. 147-152, ISSN Print: 0976-6464, ISSN Online: 0976 6472. [8] Rajinder Tiwari and R K Singh, An Optimized High Speed Dual Mode CMOS Differential Amplifier for Analog VLSI applications, International Journal of Electrical Engineering & Technology (IJEET), Volume 3, Issue 1, 2012, pp. 180-187, ISSN Print : 0976-6545, ISSN Online: 0976-6553. 32