Preliminary Datasheet

BVA4B -4 MHz Product Description Figure. Package Type The BVA4B is a digitally controlled variable gain amplifier (DVGA) is featuring high linearity using the voltage.v supply with a broadband frequency range of to 4 MHz. The BVA4B integrates a high performance digital step attenuator and a high linearity, broadband gain block. using the small package(4x4mm QFN package) and operating VDD.V voltage. and designed for use in G/4G wireless infrastructure and other high performance RF applications. Both stages are internally matched to Ohms and It is easy to use with no external matching components required. A serial output port enables cascading with other serial controlled devices. An integrated digital control interface supports both serial and parallel programming of the attenuation, including the capability to program an initial attenuation state at power-up. Covering a. db attenuation range in. db steps. The BVA4B is targeted for use in wireless infrastructure, point-topoint, or can be used for any general purpose wireless application. Figure. Functional Block Diagram D 4 D D4 RF P/S VSS/ 9 8 Device Features 4-lead 4x4 mm QFN Small 4-Pin 4 x 4 mm QFN Package Integrate DSA to Amp Functionality Wide Power supply range of +.7 to +.V(DSA) Single Fixed +.V supply(amp) -4MHz Broadband Performance. Gain at.4ghz.db Noise Figure at max gain setting at.4ghz 9.dBm PdB at.4ghz.dbm OIP at.4ghz No matching circuit needed Attenuation:. db steps to. db Safe attenuation state transitions Monotonicity:. db up to 4 GHz High attenuation accuracy(dsa to Amp) ±(. + % x Atten) @.4 GHz.8V control logic compatible Programming modes - Direct Parallel - Latched Parallel - Serial Unique power-up state selection D 7 D 6-Bit Digital Step Attenuator 6 VDD D 4 PUP AMPOUT 6 Gain Block AMPLIFIER 4 PUP LE Application 7 8 9 AMPIN RF SERIN CLOCK G/4G Wireless infrastructure and other high performance RF application Microwave and Satellite Radio General purpose Wireless All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Table. Electrical Specifications Parameter Condition Min Typ Max Unit Operational Frequency Range 4 MHz Gain Attenuation = db, at 9MHz.. 4. db Attenuation Control range.db Step. db Attenuation Step. db MHz GHz ±(. + % of atten setting) Attenuation Accuracy >GHz.GHz >.GHz GHz Any bit or bit combination ±(. + % of atten setting) ±(. + 8% of atten setting) db >GHz 4GHz ±(. + % of atten setting) Return loss GHz.GHz 7 Attenuation = db (input or output port) >.GHz 4GHz 8 db Output Power for db Compression Attenuation = db, at 9MHz 9.4 dbm Output Third Order Intercept Point Attenuation = db, at 9MHz two tones at an output of dbm per tone separated by MHz.. dbm Noise Figure Attenuation = db, at 9MHz.4 db Switching time % CTRL to 9% or % RF 8 ns Supply voltage DSA.7. V AMP. V Supply Current 6 ma Control Interface Serial / parallel mode 6 Bit Control Voltage Digital input high.7.6 V Digital input low -..6 V Impedance Ω Device performance _ measured on a BeRex Evaluation board at C, Ω system, VDD=+.V, measure on Evaluation Board (DSA to AMP) Gain data has PCB & Connectors insertion loss de-embedded OIP _ measured with two tones at an output of dbm per tone separated by MHz. All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Table. Typical RF Performance Parameter Frequency Unit 7 9 9 4 6 MHz Gain 4.7 8...8. db S -7.8-8. -.7 -.9 -. db S -.6 -.8-4.8-9.4-8.8 db OIP. 8.7...8 dbm PdB. 9.8 9.4 9. 9. dbm Noise Figure..4..4 4. db Device performance _ measured on a BeRex evaluation board at C, VDD=+.V, Ω system. measure on Evaluation Board (DSA to AMP) 7MHz measured with application circuit refer to table. 9MHz measured with application circuit refer to table 4 9MHz,4MHz,6MHz measured with application circuit refer to table 7 Gain data has PCB & Connectors insertion loss de-embedded 6 OIP _ measured with two tones at an output of - dbm per tone separated by MHz. Table. Absolute Maximum Ratings Parameter Condition Min Typ Max Unit Supply Voltage(VDD) Amp/DSA./. V Supply Current Amp ma Digital input voltage -..6 V Maximum input power Amp/DSA +4/+ dbm Operating Temperature Amp/DSA -4 8/ Storage Temperature - Junction Temperature Operation of this device above any of these parameters may result in permanent damage. All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Figure. Pin Configuration(Top View) D D D 4 Exposed Pad AMPOUT 6 AMPIN RF SERIN Clock 7 8 9 4 D D D4 RF P/S 9 VSS/ 8 7 6 VDD PUP 4 PUP LE Table 4. Pin Description Pin Pin name Description,,7,9,7,8 Ground, These pins must be connected to ground D Parallel Control Voltage Inputs, Attenuation control bit db D Parallel Control Voltage Inputs, Attenuation control bit.db 4 D Parallel Control Voltage Inputs, Attenuation control bit 6dB 6 AMPOUT RF Gain block Amplifier output Port 8 AMPIN RF Gain block Amplifier input Port RF This pin can also be used as an output because the design is bidirectional. RF is dc-coupled and matched to Ω RF port (Digital Step Attenuator RF Input) SERIN Serial interface data input Clock Serial interface clock input LE Latch Enable input 4 PUP Power-Up State Selection Bits. These pins set the attenuation value at power-up (see Table ). There is no internal pull-up or pull- down PUP resistor on these pins; therefore, they must always be kept at a valid logic level (VCTLH or VCTLL) and not be left floating 6 VDD DSA Power Supply (nominal.v) 9 VSS/ External V SS negative voltage control or ground Do not want to use negative voltage supply, These pins must be connected to ground (, Default setting is ) P/S Parallel/Serial Mode Select. For parallel mode operation, set this pin to low. For serial mode operation, set this pin to High. RF This pin can also be used as an input because the design is bidirectional. RF is dc-coupled and matched to Ω. RF port (Attenuator RF Output.) D4 Parallel Control Voltage Inputs, Attenuation control bit D Parallel Control Voltage Inputs, Attenuation control bit 4 D Parallel Control Voltage Inputs, Attenuation control bit db EXPOSE PAD Exposed pad: The exposed pad must be connected to ground for proper operation Note:. RF pins and must be at V DC. The RF pins do not require DC blocking capacitors for proper Operation if the V DC requirement is met. Connect VssEXT (pin 9, VssEXT = ) to enable internal negative voltage generator 4 All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Programming Options Table. 6-Bit Serial Word Sequence BVA4B can be programmed using either the parallel or serial interface, which is selectable via P/S pin(pin). Serial mode is selected by floating P/S or pulling it to a voltage logic LOW and parallel mode is selected by setting P/S to logic low Serial Control Mode The serial interface is a 6 bit shift register to shift in the data MSB (D) first. When serial programming is used, all the parallel control input pins (,,4,,,4) must be grounded. It is controlled by three CMOS-compatible signals: SERIN, Clock, and Latch Enable (LE). D D4 D D D D Attenuation 6dB Control Bit Attenuation Control Bit Attenuation Control Bit Attenuation db Control Bit Attenuation db Control Bit Attenuation.dB Control Bit Figure 4. Serial Mode Resister Timing Diagram P/S X LE tles CLK tln tlew SERIAL IN X D D4 D D D D X D[:] NEXT WORD X tsh tss MSB [FIRST IN] tsck LSB [LAST IN] The BVA4B has a -wire serial peripheral interface (SPI): serial data input (Data), clock (CLK), and latch enable (LE). The serial control interface is activated when P/S is set to HIGH. In serial mode, the 6-bit Data is clocked MSB first on the rising CLK edges into the shift register and then LE must be toggled High to latch the new attenuation state into the device. LE must be set to low to clock new 6-bit data into the shift register because CLK is masked to prevent the attenuator value from changing if LE is kept High (see Figure 4 and Table 8). Table 6. Mode Selection Table 8. Truth Table for Serial Control Word P/S LOW HIGH Control Mode Parallel Serial Digital Control Input D D4 D D D D Attenuation (MSB) (LSB) (db) LOW LOW LOW LOW LOW LOW (Reference) Table 7. Serial Interface Timing Specifications Symbol Parameter Min Typ Max Unit fclk Serial data clock frequency MHz t SCK Minimum serial period 7 t SS Serial Data setup time t SH Serial Data hold time t LN LE setup time t LEW Minimum LE pulse width t LES Minimum LE pulse spacing 6 LOW LOW LOW LOW LOW HIGH. LOW LOW LOW LOW HIGH LOW LOW LOW LOW HIGH LOW LOW LOW LOW HIGH LOW LOW LOW 4 LOW HIGH LOW LOW LOW LOW 8 HIGH LOW LOW LOW LOW LOW 6 HIGH HIGH HIGH HIGH HIGH HIGH. All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Parallel Control Mode The BVA4B has six digital control inputs, D (LSB) to D (MSB), to select the desired attenuation state in parallel mode, as shown in Table 9. The parallel control interface is activated when P/S is set to low. There are two modes of parallel operation: direct parallel and latched parallel Direct Parallel Mode The LE pin must be kept LOW. The attenuation state is changed by the control voltage inputs (D to D) directly. This mode is ideal for manual control of the attenuator. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins,, 4,,, 4]. Use direct parallel mode for the fastest settling time. Latched Parallel Mode The LE pin must be kept low when changing the control voltage inputs (D to D) to set the attenuation state. When the desired state is set, LE must be toggled LOW to transfer the 6-bit data to the bypass switches of the attenuator array, and then toggled low to latch the change into the device until the next desired attenuation change (see Figure and Table 9). Power-UP Interface The BVA4B uses the PUP and PUP control voltage inputs to set the attenuation value to a known value at power-up before the initial control data word is provided in either serial or parallel mode. When the attenuator powers up with LE set to low, the state of PUP and PUP determines the power-up state of the device per the truth table shown in Table. The attenuator latches in the desired power-up state approximately ms after power-up. Table. PUP Truth Table Attenuation state P/S LE PUP PUP. db LOW LOW HIGH HIGH 6 db LOW LOW HIGH LOW 8 db LOW LOW LOW HIGH Reference Loss LOW LOW LOW LOW Defined by C.-C6 LOW HIGH Don t Care Don t Care Figure. Latched Parallel Mode Timing Diagram P/S X t PS t PH Parallel IN X D[:] PARALLEL CONTROL X t LEW LE Table 9. Truth Table for the Parallel Control Word D D D D D4 D P/S LE Attenuation State LOW LOW LOW LOW LOW LOW LOW HIGH Reference Loss HIGH LOW LOW LOW LOW LOW LOW HIGH.dB LOW HIGH LOW LOW LOW LOW LOW HIGH db LOW LOW HIGH LOW LOW LOW LOW HIGH db LOW LOW LOW HIGH LOW LOW LOW HIGH LOW LOW LOW LOW HIGH LOW LOW HIGH LOW LOW LOW LOW LOW HIGH LOW HIGH 6dB HIGH HIGH HIGH HIGH HIGH HIGH LOW HIGH.dB Table. Parallel Interface Timing Specifications Symbol Parameter Min Typ Max Unit t LEW Minimum LE pulse width ns t PH Data hold time from LE ns t PS Data setup time to LE ns All other trademarks are the property of their respective owners. 8 BeRex 6 Rev..

Input Return Loss [db] Input Return Loss [db] Preliminary Datasheet Gain [db] Gain [db] BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:~MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table Table. Typical RF Performance(~MHz) Table. ~MHz IF Application Circuit Frequency Unit parameter 7 MHz Gain.7. db L C C C S -7.8 -. db S -.6-8.7 db U_DSA C6 U_Amp C4 OIP. 9.6 dbm PdB..8 dbm N.F..6 db Gain data has PCB & Connectors insertion loss de-embedded OIP _ measured with two tones at an output of - dbm per tone separated by MHz. Application Circuit Values Freq. IF Circuit MHz ~ MHz C6/C4.nF L( Chip Ind) nh Figure 6. Gain vs. Frequency over Temperature Figure 7. Gain vs. Frequency over Major Attenuation States -4 C 4 - db.db db db - 6dB.dB - 4 Figure 8. Input Return Loss vs. Frequency over Major Attenuation States Figure 9. Input Return Loss vs. Frequency over Temperature (Min,Max Gain State) - - - - - - -4 db.db db db - 6dB.dB -6 4 @Max Gain -4 @Min Gain -4 C @Max Gain - -4 C @Min Gain @Max Gain @Min Gain -6 4 All other trademarks are the property of their respective owners. 8 BeRex 7 Rev..

PdB [dbm] NF [db] Preliminary Datasheet OIP [dbm] OIP [dbm] Output Return Loss [db] Output Return Loss [db] BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:~MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table Figure. Output Return Loss vs. Frequency over Major Attenuation States Figure. Output Return Loss vs. Frequency over Temperature (Min, Max Gain State) - - - - - -4 db.db db db - 6dB.dB -6 4 - @Max Gain -4 @Min Gain -4 C @Max Gain -4 C @Min Gain - @Max Gain @Min Gain -6 4 4 Figure. OIP vs. Frequency Over Temperature (Max Gain State) 4 * Min Gain was measured in the state is set with attenuation.db. Figure. OIP vs. Frequency Over Temperature (.db Atteuation State) -4 C 4-4 C 4 Figure 4. PdB vs. Frequency Over Temperature (Max Gain State) Figure. Noise Figure vs. Frequency Over Temperature (Max Gain State) 4 8 6 4 8 6 4-4 C 4 8 7 6 4-4 C 4 All other trademarks are the property of their respective owners. 8 BeRex 8 Rev..

Preliminary Datasheet BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:~MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table Figure 6. Attenuation Error vs Frequency over Major Attenuation Steps Figure 7. Attenuation Error vs Attenuation Setting over Major Frequency (Max Gain State)... -. -.db db -. db - 6dB.dB -. 4... -. - -. - -. MHz 7MHz MHz MHz MHz 4MHz - Figure 8..dB Step Attenuation vs Attenuation Setting over Major Frequency. Figure 9. Attenuation Error at MHz vs Temperature Over All Attenuation States.... -. MHz 7MHz MHz -. MHz MHz 4MHz -. -. - -4 C -. UPPER LIMIT LOWER LIMIT - Figure. Attenuation Error at 7MHz vs Temperature Over All Attenuation States. Figure. Attenuation Error at MHz vs Temperature Over All Attenuation States... -. - -4 C -. UPPER LIMIT LOWER LIMIT - -. - -4 C -. UPPER LIMIT LOWER LIMIT - All other trademarks are the property of their respective owners. 8 BeRex 9 Rev..

Input Return Loss [db] Input Return Loss [db] Preliminary Datasheet Gain [db] Gain [db] BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:~7MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table Table 4. Typical RF Performance(~7MHz) Table. ~7MHz RF Application Circuit Frequency Unit parameter 7 8 9 MHz Gain 9.6 8.9 8. 7.7 7. db L C C C S -. -. -8. -9. -. db S -.9 -. -.8-4. -4.4 db U_DSA C6 U_Amp C4 OIP 9.6 9. 8.7 8. 8.9 dbm PdB.. 9.8 9.7 9.7 dbm N.F..... db Gain data has PCB & Connectors insertion loss de-embedded OIP _ measured with two tones at an output of - dbm per tone separated by MHz. Application Circuit Values Freq. RF Circuit MHz ~ 7MHz C6/C4 6pF L( Chip Ind) nh Figure. Gain vs. Frequency over Temperature (Max Gain State) Figure. Gain vs. Frequency over Major Attenuation States - -4 C 7 9,,,,7 - db.db - db db 6dB.dB -4 7 9,,,,7 Figure 4. Input Return Loss vs. Frequency over Major Attenuation States Figure. Input Return Loss vs. Frequency over Temperature (Min,Max Gain State) - - - - - - -4 db.db - db db 6dB.dB -6 7 9,,,,7 @Max Gain -4 @Min Gain -4 C @Max Gain - -4 C @Min Gain @Max Gain @Min Gain -6 7 9,,,,7 * Min Gain was measured in the state is set with attenuation.db. All other trademarks are the property of their respective owners. 8 BeRex Rev..

PdB [dbm] NF [db] Preliminary Datasheet OIP [dbm] OIP [dbm] Output Return Loss [db] Output Return Loss [db] BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:~7MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table Figure 6. Output Return Loss vs. Frequency over Major Attenuation States Figure 7. Output Return Loss vs. Frequency over Temperature (Min, Max Gain State) - - - - - db.db -4 db db 6dB.dB - 7 9,,,,7 - -4-7 9,,,,7 @Max Gain @Min Gain -4 C @Max Gain -4 C @Min Gain @Max Gain @Min Gain Figure 8. OIP vs. Frequency Over Temperature (Max Gain State) * Min Gain was measured in the state is set with attenuation.db. Figure 9. OIP vs. Frequency Over Temperature (.db Atteuation State) -4 C 7 9,,,,7-4 C 7 9,,,,7 Figure. PdB vs. Frequency Over Temperature (Max Gain State) Figure. Noise Figure vs. Frequency Over Temperature (Max Gain State) 4 8 6 4 8 6 4-4 C 7 9,,,,7 8 7 6 4-4 C 7 9,,,,7 All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:~7MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table Figure. Attenuation Error vs Frequency over Major Attenuation Steps Figure. Attenuation Error vs Attenuation Setting over Major Frequency (Max Gain State).8.6.4.dB db.db db 6dB..4.... -. -. -.4 -. -.6 -. 7MHz -.8 -.4 9MHz - 7 9,,,,7 -. Figure 4..dB Step Attenuation vs Attenuation Setting over Major Frequency (Max Gain State). Figure. Attenuation Error at 9MHz vs Temperature Over All Attenuation States.. -. 7MHz -. 9MHz -. - -4 C - UPPER LIMIT LOWER LIMIT - All other trademarks are the property of their respective owners. 8 BeRex Rev..

Input Return Loss [db] Input Return Loss [db] Preliminary Datasheet Gain [db] Gain [db] BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:7~4MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table 7 Table 6. Typical RF Performance(7~4MHz) Table 7. 7~4MHz RF Application Circuit Frequency Unit parameter 7 9 4 6 MHz Gain 4...8. 7. db L C C C S -7.6 -.7 -.9 -. -8.7 db S -.7-4.8-9.4-8.8 -.6 db U_DSA C6 U_Amp C4 OIP.4...8.8 dbm PdB 9.4 9.4 9. 9. 8.4 dbm N.F..4. 4.. db Gain data has PCB & Connectors insertion loss de-embedded OIP _ measured with two tones at an output of - dbm per tone separated by MHz. Application Circuit Values Freq. RF Circuit 7MHz ~ 4MHz C6/C4 pf L( Chip Ind) 7.nH Figure 6. Gain vs. Frequency over Temperature (Max Gain State) Figure 7. Gain vs. Frequency over Major Attenuation States - -4 C,7,,7,,7 - db.db - db db 6dB.dB -4,7,,7,,7 Figure 8. Input Return Loss vs. Frequency over Major Attenuation States Figure 9. Input Return Loss vs. Frequency over Temperature (Min,Max Gain State) - - - - - - -4 db.db - db db 6dB.dB -6,7,,7,,7 @Max Gain -4 @Min Gain -4 C @Max Gain - -4 C @Min Gain @Max Gain @Min Gain -6,7,,7,,7 * Min Gain was measured in the state is set with attenuation.db. All other trademarks are the property of their respective owners. 8 BeRex Rev..

PdB [dbm] NF [db] Preliminary Datasheet OIP [dbm] OIP [dbm] Output Return Loss [db] Output Return Loss [db] BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:7~4MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table 7 Figure 4. Output Return Loss vs. Frequency over Major Attenuation States Figure 4. Output Return Loss vs. Frequency over Temperature (Min, Max Gain State) - - - - - db.db -4 db db 6dB.dB -,7,,7,,7 - -4 -,7,,7,,7 @Max Gain @Min Gain -4 C @Max Gain -4 C @Min Gain @Max Gain @Min Gain Figure 4. OIP vs. Frequency Over Temperature (Max Gain State) * Min Gain was measured in the state is set with attenuation.db. Figure 4. OIP vs. Frequency Over Temperature (.db Atteuation State) -4 C,7,,7,,7-4 C,7,,7,,7 Figure 44. PdB vs. Frequency Over Temperature (Max Gain State) Figure 4. Noise Figure vs. Frequency Over Temperature (Max Gain State) 4 8 6 4 8 6 4-4 C,7,,7,,7 8 7 6 4-4 C,7,,7,,7 All other trademarks are the property of their respective owners. 8 BeRex 4 Rev..

Preliminary Datasheet BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:7~4MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table 7 Figure 46. Attenuation Error vs Frequency over Major Attenuation Steps Figure 47. Attenuation Error vs Attenuation Setting over Major Frequency (Max Gain State).. -. -. -. - -..db db db - 6dB -..db -4,7,,7,,7 -..9GHz -.4GHz.6GHz -. Figure 48..dB Step Attenuation vs Attenuation Setting over Major Frequency (Max Gain State) Figure 49. Attenuation Error at.9ghz vs Temperature Over All Attenuation States... -. -. -..9GHz.4GHz.6GHz - - - -4 C UPPER LIMIT LOWER LIMIT Figure. Attenuation Error at.4ghz vs Temperature Over All Attenuation States Figure. Attenuation Error at.6ghz vs Temperature Over All Attenuation States - -4 C - UPPER LIMIT LOWER LIMIT - - -4 C - UPPER LIMIT LOWER LIMIT - All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Typical RF Performance Plot - BVA4B EVK - PCB (Application Circuit:7~4MHz) Typical Performance Data @ and VDD =.V unless otherwise noted and Application Circuit refer to Table 7 Figure. Attenuation Error at.9ghz vs Temperature Over All Attenuation States 4 - - -4 C - UPPER LIMIT LOWER LIMIT -4 All other trademarks are the property of their respective owners. 8 BeRex 6 Rev..

BVA4B -4 MHz Figure. Evaluation Board Schematic Figure 4. Evaluation Board PCB Table 8. Application Circuit Freq. Application Circuit Values Example IF Circuit ~MHz RF Circuit MHz ~.7GHz RF Circuit.7GHz ~ 4GHz C6/C4 nf 6pF pf L( Chip Ind) 8nH nh 7.nH Table 9. Bill of Material - Evaluation Board No. Ref Des Part Part Number REMARK C4,C6 CAP 4 pf J V Another circuit refer to table 8 C CAP 4 pf J V C TANTAL 6 UF 6V 4 C TANTAL 6.uF V L IND 68 7.nH Another circuit refer to table 8 6 C CAP 4 pf J V 7 R,R RES J K 8 R,R4,R,R7 RES 68 J ohm 9 J Receptacle connector U QFN4X4_4L_BVA4B J,J SMA_END_LAUNCH Notice: Evaluation Board for Marketing Release was set to.7ghz to 4GHz application circuit (Refer to Table 7) 7 All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Figure. Application Circuit schematic* (Use only Serial mode) * notice. The serial mode PUP state of this Figure. is setting in Reference Loss (Refer to Table.) and each combinations of C.-C6 are shown in the Table 8. Truth Table. 8 All other trademarks are the property of their respective owners. 8 BeRex Rev..

BVA4B -4 MHz Figure. Package Outline Dimension Figure 6. Evaluation Board PCB Layer Information Figure 7. Recommend Land Pattern COPPER :oz +.oz (plating), Top Layer EM8B ER: 4.6~4.8 P.P : (.+.6+.6) TOTAL =.mm COPPER :oz (), Inner Layer MTC Er:4.6 CORE :.7mm COPPER :oz, Inner Layer FINISH TICKNESS :.T EM8B Er:4.6~4.8 P.P : (.+.6+.6) TOTAL =.mm COPPER :oz +.oz (plating), Bottom Layer All other trademarks are the property of their respective owners. 8 BeRex 9 Rev..

BVA4B -4 MHz Figure 8. Tape & Reel Figure 9. Package Marking Marking information: Packaging information: Tape Width mm Reel Size 7 Device Cavity Pitch 8mm Devices Per Reel K BVA4B YYWWXX Lead plating finish BVA4B YY WW XX Device Name Year Work Week LOT Number % Tin Matte finish MSL / ESD Rating ESD Rating: Value: Test: Standard: Class C Passes V Human Body Model(HBM) JEDEC Standard JESD-A4B MSL Rating: Standard: Level at +6 C convection reflow JEDEC Standard J-STD- C a u t i o n : ESD Sensitive Appropriate precautions in handling, packaging and testing devices must be observed. Proper ESD procedures should be followed when handling this device. NATO CAGE code: N 9 6 F All other trademarks are the property of their respective owners. 8 BeRex Rev..