IMPLEMANTATION OF D FLIP FLOP BASED ON DIFFERENT XOR /XNOR GATE DESIGNS

IMPLEMANTATION OF D FLIP FLOP BASED ON DIFFERENT XOR /XNOR GATE DESIGNS 1 MADHUR KULSHRESTHA, 2 VIPIN KUMAR GUPTA 1 M. Tech. Scholar, Department of Electronics & Communication Engineering, Suresh Gyan Vihar University, Jaipur 2 Assistant Professor, Department of Electronics & Communication Engineering, Suresh Gyan Vihar University, Jaipur ABSTRACT Rapid growth in electronics market in last three decades has increased pressure on the VLSI industry to continuously upgrade its technology, in terms of chip design systems, very high integration density and increasing operating frequencies beyond few GHz, along with their benefits some critical concerns has arisen i.e. increase in power consumption of the devices and another to reduce it as much as possible. Due to the drastically changing market, increasing demand and great popularity of portable electronic devices, designers are optimizing their system designs in order to get greater speeds, higher packing density, and good battery life with more reliability. Power consumption is the figure of merit in electronic goods. So power is the primary concern any designer to save it while system designing. The circuits, XOR XNOR are the basic building blocks in many electronic circuits such as combinational circuits (Full adder, multipliers, parity checkers, comparators, error detecting codes, phase detectors circuit in PLL, code converters) etc. Since the permance of the individual circuit i.e. XOR XNOR directly affects the complex logic circuits. Theree, very careful designing and analysis has to be done using XOR XNOR circuits. The XOR XNOR circuits should give less power consumption, less power dissipation, complete output voltage swing and optimized delay in propagation or in critical path. In addition to that, lesser number of transistors has to be used designing purpose of XOR XNOR circuits and simultaneous generation of two non skewed outputs. The amazing improvement in microelectronics industry have taken place in last 30 years and it is steadily moving and upgrading ward to achieve a prime position in the system design of modern electronics. It has penetrated its roots all over the world so largely in such a short period of time because of its continuous advancements in the permance of the device while being pocket friendly to each level of customer. The entire some efts of the designers have enabled them to make devices having the desired features like fewer delays, less power consumption and high packing density. The continuation of Moore s law has been proved due to increased clock speeds and small features size. The Moore s law states that the transistor density on integrated circuits doubles every 18 months. Different designs of XOR/XNOR gate has been designed using different components like Transmission Gates, NMOS switches, Pass Transistors & GDI (Gate Diffusion Input) cell that can be operated at higher frequencies. All designs have been designed using 32nm UMC CMOS technology and compared the supply voltage range from 0.9V to 1.5V. These designs are simulated in HSPICE tool the successful function. Best optimized design of XOR/XNOR gate is found out. It is being widely used in a high speed microprocessors like adders, comparators etc perming different arithmetic operations. Improved features of XOR/XNOR circuit increases the permance of full adder and other circuits. 1. INTRODUCTION Rapid growth in electronics market in last three decades has increased pressure on the VLSI industry to continuously upgrade its technology, in terms of chip design systems, very high integration density and increasing operating frequencies beyond few GHz, along with their benefits some critical concerns has arisen i.e. increase in power consumption of the devices and another to reduce it as much as possible. Due to the drastically changing market, increasing demand and great popularity of portable electronic devices, designers are optimizing their system designs in order to get greater speeds, higher packing density, and good battery life with more reliability. Power consumption is the figure of merit in electronic goods. So power is the primary concern any designer to save it while system designing. The circuits, XOR XNOR are the basic building blocks in many electronic circuits such as combinational circuits (Full adder, multipliers, parity checkers, comparators, error detecting codes, phase detectors circuit in PLL, code converters) etc. Since the permance of the individual circuit i.e. XOR XNOR directly affects the complex logic circuits. Theree, very careful designing and analysis has to be done using XOR XNOR circuits. The XOR XNOR circuits should give less power consumption, less power dissipation, complete output voltage swing and optimized delay in propagation or in critical path. In addition to that, lesser number of transistors has to be used designing purpose of XOR XNOR circuits and simultaneous generation of two nonskewed outputs. The amazing improvement in microelectronics industry have taken place in last 30 years and it is steadily moving and upgrading ward to achieve a prime position in the system design of modern electronics. It has penetrated its roots all over the world so largely in such a short period of time because of its continuous advancements in the permance of the device while being pocket friendly to each level of customer. The entiresome efts of the designers have enabled them to make devices having the desired features like fewer INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 39

delays, less power consumption and high packing density. The continuation of Moore s law has been proved due to increased clock speeds and small features size. The Moore s law states that The transistor density on integrated circuits doubles every 18 months. CMOS Technology has been successful due to the fact that it has compact designs and the scaling factor is much smaller the CMOS transistor when compared to other technologies. In VLSI i.e. (Very Large Scale Integration) circuits CMOS technology is dominating because of its improved permance at power consumption. involves modelling of circuit, then synthesis of the circuit and verification will be required at the each and every level of abstraction. Manual design techniques are not that much efficient and it cannot keep pace with every level of design cycle of product and hence the manual design techniques are replaced with automated design techniques. Figure 2: MOSFET Gate length versus year Figure 1: CPU clock speed versus year The ITRS (International Technology Roadmap Semiconductor) was established by an expert group serving various purposes in the field of its main objective has been the specification of design parameter values of device so as to cope up with device technology in near future. Secondly, it highlights those challenges that coming generations might face in the field of device scaling. The ITRS s main projection in the front end process areas and MOSFET has been greater permance with very low power logic. Memory IC s and digital logic IC s serve as the major element in the production of semiconductor devices. The main feature of the devices is high speed at low power consumption. There may be different approaches to reach the goal better permance logic such as computer s microprocessors etc. TCAD (Technology Computer Aided Design) is a powerful tool. TCAD helps a designer to reduce design cost, improve productivity of device design and to obtain better due to the increasing demand of customers price reduction of high quality electronic goods; computation power has become cheap compared to earlier times. Another reason price reduction is Moore s law and the resulting improvements seen in the latest designs at relatively low expenditure. The development of IT infrastructure has drastically transmed lives of people and society. development in inmation technology has brought up by the (EDA) electronic design automation technology which is a computer aided design of VLSI circuits. EDA has many distinct features like unique collection of methodologies, tools algorithms which helps in assisting and automating designs, then in verifying and conducting various tests of electronic systems a successful design. A lower level detailed logical and physical implementation of any electronic circuit can be obtained from a high level description of an electronic circuit using EDA. process Computer simulation is cheap and time saving fabrication process. It can be used study and predict the various electrical characteristics of a designed circuit of a device. The various steps of fabrication process like modelling and simulation can be predicted and studied so as to study the electronic as well as physical characteristics of the device that is designed. Some of its physical characteristics are thickness of oxide and doping distribution. As TCAD is providing numerous advantages to its users gradually it has been accepted as main tool modelling as well as simulation of device designs. To obtainaccurate computer simulations and service modelling designer must give proper input and use calibrated physical models. 1.1 Motive of the Research The main aim of this research work is to study, examine and note all the similarities and differences of various designs of D flip flop based on XOR/XNOR circuits that have appropriate transistor characteristics by applying it to UMC 32nm CMOS technology supply voltage ranging from 0.9V to 1.5V and also to find out the finest optimized design of D flip flop circuits that is providing with all good characteristics like less power consumption, higher duty cycle and less time delay. The optimized design must be such that it can be easily implemented in combinational circuits such as adders, subtractors, comparators, parity checkers, multipliers etc. 2. PROPOSED WORK Today CMOS XOR/XNOR gates and D flip flop are being frequently used in high speed microprocessor like adder, multiplier etc to perm various arithmetic operations. These gates are crucial part of the circuit and affects overall permance of the device. PMOS circuit (pull up network) is a complex network theree the CMOS circuits consisting of PMOS network consumes high power and gives less speed. Today the main concern issues designing any CMOS circuit are power, delay and silicon area of the chip. Transmission gate is also used in INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 40

designing of D flip flop based on XOR/XNOR circuit because transmission gate has high switching speed, requires less power and gives less delay. Delay can be easily predicted by Spice simulations. These simulations help in minimizing chip area, power consumption, time delay and maximizing reliability. All internal capacitances are ignored. The maximum number of loading circuits that can be connected to the output of D flip flop based on XOR/XNOR circuit is called fan out of a circuit which helps to drive the output signal. 0. When AB=11, M3, M4, M7, M8 gets on, at this stage M3 & M4 gives output 0 and M7 & M8 gives output 1. circuit works as a D flip flop based on Table 2 shows the transistors characteristics at 32nm design I. Table2: Transistors Characteristics Design I In this chapter I have explained and designed five CMOS structures of D flip flop based on XOR/XNOR circuits using different design styles and compared the main factors all the designs. All circuits are designed technology. using 32nm UMC CMOS Many papers are published in this area but I have designed D flip flop using different XOR/XNOR gate circuits. Table 1 mentions the initial parameters that are taken to make the pulse A & B. Table 1: Initial Parameters V dd = 0.9V, L = 32nm Input Delay (sec) Rise Time (sec) Fall Time (sec) A & B 0.025F 0.3P 0.3P 2.1 D Flip Flop Design I Figure 4: Output Design I 2.2 D Flip Flop Design II Figure 3: D flip flop design I When AB=00, M1, M2, M5, M6 gets ON. At this stage M1 & M2 gives XOR output 0 and M5 & M6 gives XNOR output Vdd as 1. Since B (Clock) is off so Q will be previous value of output. When AB=01, M2, M3, M5, M8 gets ON. At this stage M2 gives XOR output B as 1 and M8 gives XNOR output A as 0. Since B (Clock) is high so Q will be value of A. When AB=10, M1, M4, M6, M7 gets on, at this stage M1 gives XOR outpu A as 1 and M7 gives XNOR output B as Figure 5: D flip flop design II INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 41

When AB=00, M1, M3, M5 gets ON. At this stage I1 produces output B and I2 produces outpu A. Output of I2 switches M9 & M10 on and output of M10 switches M7 on making XOR output 0 and XNOR output Vdd as 1. Since B (Clock) is off so Q will be previous value of output. When AB= 01, M1, M4, M6 gets ON. At this stage I1 & I2 produces output B and I3 produces output A making XNOR output 0. Output of I3 switches M8making XOR output 1. Since B (Clock) is high so Q will be value of A. When AB=10, M2, M3, M5 gets on, at this stage I1 & I3 produces outpu 0 making XNOR output 0. I2 produces output A making XOR output 1. When AB=11, M2, M4, M6 gets ON. At this stage I1& I2 produces output 0 making XOR output 0 and I3 produces output A. Output of I2 switches M9 & M10 on and output of M10 switches M7 on making XNOR output Vdd as 1. 2.3 D Flip Flop Design III circuit works as a D flip flop based on Figure 7: D flip flop design III Table 3 shows the transistors characteristics at 32nm design II. Table 3: Transistors Characteristics Design II When AB=00, M1, M3, M9 gets ON. At this stage M3 produces output B (0) as an XOR output& M1 produces output 1 and provides it to M9 making XNOR outpu 1. Since B (Clock) is off so Q will be previous value of output. When AB=01, M2, M3, M9 gets ON. At this stage M3 produces outpu B (1) as XOR output &M2 produces output 0 and provides it to M9 making XNOR outpu 0. Since B (Clock) is high so Q will be the value of A. When AB= =10, M1, M4, M10 gets on, at this stage M1 produces output 1 whichh flows through M4 making XOR outpu 1. XOR output switches M8 on and produces output 0 & M10 also produces output 0 as XNOR output. When AB=11, M2, M4, M10 gets ON. At this stage M2 produces output 0 which flows through M4 and makes XOR output 0. XOR output switches M5 on and produces output 1 & M10 also produces outputt 1 making XNOR output 1. circuit works as a D flip flop based on Table 4 shows the transistors characteristics at 32nm design III. Table 4: Transistors Characteristics Design IIII Figure 6: Outpu Design II INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 42

Figure 8 shows the output wavem design III Table5: Transistors Characteristics Design IV Figure 10 showss the output wavem design IV Figure 8: Outpu Design III 2.4 D Flip Flop Design IV Figure 9: D flip flop design IV When AB=00, M1, M2, M5 gets ON. At this stage M1 produces outputt 1 which transfers M5 & M10 in ON condition and produces output B(0) as XOR output. XOR output is passed through inverter making XNOR outpu 1. Since B (Clock) is off so Q will be previous value of output. When AB=01, M1, M7, M5 gets ON. At this stage M1 produces outputt 1 which transfers M5 & M10 in ON condition and produces output B(1) as XOR output. XOR output is passed through inverter making XNOR outpu 0. Since B (Clock) is high so Q will be the value of A. When AB= 10, M2, M6, M9 gets on, at this stage M6 produces output 0 which transfers M4 in ON condition. M2 produces output 1 which flows through M4 & M9 making XOR output 1. XOR outputt is passed through inverter making XNOR output 0. When AB=11, M6, M7, M9 gets on, at this stage M6 produces output 0 whichh transfers M4 in ON condition. M7 produces output 0 which flows through M4 & M9 making XOR output 0. XOR output is passed through inverter making XNOR output 1. Figure 10: Output Design IV 2.5 D Flip Flop Design V circuit works as a D flip flop based on Table 5 shows the transistors characteristics at 32nm design IV. Figure 11: D flip flop design V INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 43

When AB=00, M1, M3, M5 gets ON. At this stage M1 gives output B which flows upto XOR node making XOR output 0. M3gives output 1 & XOR output switches M8 on which makes XNOR output 1. Since B (Clock) is off so Q will be previous value of output. When AB=01, M1, M3, M6 gets ON. At this stage M1 gives XOR output B as 1.M3 gives output 1 but due to M6 XNOR output becomes 0. Since B (Clock) is high so Q will be the value of A. When AB=10, M2, M4, M5 gets on, at this stage M5 gives XOR output A as 1. M4 gives output B(0) as XNOR output. When AB=11, M2, M4, M6 gets on, at this stage M2 gives output 0 as XOR output which switches M8 on and M6 also gives output 1 as XNOR output. 3. RESULTS & SIMULATION All designs are simulated using 32nm UMC CMOS technology different values of Vdd. Comparison table each design is mentioned below: Table 7: Comparison table design I different Vdd circuit works as a D flip flop based on Table6 shows the transistors characteristics at 32nm design V. Table 8: Comparison table design II different Vdd Table 6: Transistors Characteristics Design V Table 9: Comparison table design III different Vdd Table 10: Comparison table design IV different Vdd Figure 12 shows the output wavem design V Table 11: Comparison table design V different Vdd Figure 12: Output Design V INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 44

These simulation results show that as we increase the power supply (Vdd), propagation time delay and power delay product increases. Through these tables I have shown the different parameters of each D flip flop design based on XOR/XNOR circuit. 4. CONCLUSIONS & FUTURE SCOPE In this thesis, I have designed different circuits of D flip flop based on XOR/XNOR gate using CMOS inverters, NMOS digital switches, pass transistors and GDI cell. Each circuit structure has been designed using 32nm UMC CMOS technology. All the designs have been simulated in HSPICE and the results are checked the voltage range from 0.9V to 1.5V and 25 degree centigrade. Design I is considered to be the best optimized design of D flip flop based on XOR/XNOR gate with average power = 0.38µW and power delay product (PDP) = 0.078fJ at Vdd = 0.9V. I have studied the comparison between different designs of D flip flop based on XOR/XNOR gate circuits in detail. Thus high speed microprocessors this best optimized design can be used to perm various arithmetic operations. In future D flip flop based on XOR/XNOR circuits can be designed more efficiently. As technology is getting advanced, power consumption, delay time, chip area are the main concern issues which we have to improve, theree these circuits can be designed to solve these issues more efficiently to reduce the total cost of the system by optimizing transistors sizes. REFERENCES 5. Frank Schwierz, Hei Wong, Juin J. Liou, Nanometer CMOS, Pan Stand Publishing, 2010. 6. Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2002. 7. Wayne Wolf, Modern VLSI Design, Pearson Education 2 nd Edition, 2007. 8. HSPICE User's Manual Meta Software, 1996. 9. Hamed Sadeghi, Hamed Mohammadi Jirandeh, Ali Zakeri, Improvement in Sub circuit of Full Adder Cell (XOR and XNOR) by GDI and Fin FET Structure, International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May, 2014. 10. Nabihah Ahmad, Rezaul Hasan, A New Design of XOR XNOR gates low power application, International Conference on Electronic Devices, Systems & Applications, 2011. BIOGRAPHY Madhur Kulshrestha, is a final year student of M. Tech(Dual Degree) EC+VLSI from Gyan Vihar School of Engineering and Technology Jaipur, Rajasthan, India. 1. J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital integrated circuits: a design perspective, Prentice Hall, 2002. 2. Sung Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 2003. 3. Neil H.E. Weste, David F. Harris, CmosVlsi Design: A Circuits and Systems Perspective, 2005. 4. K. Roy and S. Prasad, Low Power CMOS VLSI Circuit Design. Vipin Kumar Gupta received the B.E. Degree in Electronics and Communication from Sri Balaji College of Engineering and Technology Jaipur in 2008 and M.Tech in VLSI Design from MNIT Jaipur in 2011.Currently Assistant Professor at Suresh Gyan Vihar University in EC Deparment. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 45