NChannel Enhancement Mode Field Effect Transistor General Description The AOD44 uses advanced trench technology to provide excellent R DS(ON), shootthrough immunity and body diode characteristics. This device is ideally suited for use as a low side switch in CPU core power conversion. RoHS Compliant Halogen Free* Features V DS (V) = 3V I D = 85A (V GS = V) R DS(ON) < 5.2mΩ (V GS = V) R DS(ON) < 7.mΩ (V GS = 4.5V) % UIS Tested! % Rg Tested! Top View D TO252 DPAK Bottom View D G S S G G S Absolute Maximum Ratings unless otherwise noted Parameter DrainSource Voltage GateSource Voltage Continuous Drain Current B,G Pulsed Drain Current Symbol V DS Repetitive avalanche energy L=.mH C 4 Power Dissipation A T C =25 C G T C = C B Junction and Storage Temperature Range T J, T STG 55 to 75 V GS I D I DM Avalanche Current C 3 A Power Dissipation B T C =25 C T C = C I AR E AR Maximum 3 P D 5 Thermal Characteristics Parameter Symbol Typ Max Units Maximum JunctiontoAmbient A t s 4.2 2 C/W Maximum JunctiontoAmbient A R θja SteadyState 4 5 C/W Maximum JunctiontoCase C SteadyState R θjc.56.5 C/W ±2 85 66 2 2.5 P DSM T A =7 C.6 Units V V A mj W W C
Electrical Characteristics (T J =25 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage I D =25µA, V GS =V 3 V V DS =3V, V GS =V I DSS Zero Gate Voltage Drain Current µa T J =55 C 5 I GSS GateBody leakage current V DS =V, V GS = ±2V na V GS(th) Gate Threshold Voltage V DS =V GS I D =25µA.2.8 2.4 V I D(ON) On state drain current V GS =4.5V, V DS =5V A R DS(ON) Static DrainSource OnResistance V GS =V, I D =2A V GS =4.5V, I D =2A 4.2 5.2 T J =25 C 6 7.5 5.6 7 mω g FS Forward Transconductance V DS =5V, I D =2A 85 S V SD Diode Forward Voltage I S =A,V GS =V.7 V I S Maximum BodyDiode Continuous Current 85 A DYNAMIC PARAMETERS C iss Input Capacitance 66 7 pf C oss Output Capacitance V GS =V, V DS =5V, f=mhz 638 pf C rss Reverse Transfer Capacitance 355 497 pf R g Gate resistance V GS =V, V DS =V, f=mhz.2.45.6 Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge 96.4 5 nc Q g (4.5V) Total Gate Charge 46.4 55 nc V GS =4.5V, V DS =5V, I D =2A Q gs Gate Source Charge 3.6 nc Q gd Gate Drain Charge 5.6 nc t D(on) TurnOn DelayTime 5.7 2 ns t r TurnOn Rise Time V GS =V, V DS =5V, R L =.75Ω, 4.2 2 ns t D(off) TurnOff DelayTime R GEN =3Ω 55.5 75 ns t f TurnOff Fall Time 4 2 ns t rr Body Diode Reverse Recovery Time I F =2A, di/dt=a/µs 3 38 ns Q rr Body Diode Reverse Recovery Charge I F =2A, di/dt=a/µs 24 29 nc A: The value of R θja is measured with the device mounted on in 2 FR4 board with 2oz. Copper, in a still air environment with. The Power dissipation P DSM is based on steadystate R θja and the maximum allowed junction temperature of 5 C. The value in any given application depends on the user's specific board design, and the maximum temperature fo 75 C may be u sed if the PCB or heatsink allows it. B. The power dissipation P D is based on T J(MAX) =75 C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. C: Repetitive rating, pulse width limited by junction temperature T J(MAX) =75 C. D. The R θja is the sum of the thermal impedence from junction to case R θjc and case to ambient. E. The static characteristics in Figures to 6 are obtained using <3 µs pulses, duty cycle.5% max. F. These tests are performed with the device mounted on in T C = C 2 FR4 board with 2oz. Copper, in a still air environment with T A=25 C. The SOA curve provides a single pulse rating. G. The maximum current rating is limited by the package current capability. *This device is guaranteed green after data code 8X (Sep ST 28). Rev 8 : Sep 28 mω THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 6 6 5 V 4.5V 5 V DS =5V I D (A) 4 3 3.5V V GS =3V I D (A) 4 3 25 C 2 2 25 C 2 3 4 5 V DS (Volts) Figure : OnRegion Characteristics.5 2 2.5 3 3.5 4 V GS (Volts) Figure 2: Transfer Characteristics R DS(ON) (mω) 7. 6.5 6. 5.5 5. 4.5 4. 3.5 V GS =4.5V V GS =V Normalized OnResistance.8.6.4.2 I D =2A 497 V GS =4.5V V GS =V 3. 2 2 4 6 8 I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage.8 25 5 75 25 5 75.E2 Temperature ( C) Figure 4: OnResistance vs. Junction Temperature I D =2A.E.E R DS(ON) (mω) 8 6 4 T C = C 25 C 25 C I S (A).E.E2.E3 55 to 75.E4 25 C 25 C 2 2 4 6 8 V GS (Volts) Figure 5: OnResistance vs. GateSource Voltage.E5..2.4.6.8..2 V SD (Volts) Figure 6: BodyDiode Characteristics
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS V GS (Volts) 8 6 4 2 V DS =5V I D =2A 2 4 6 8 Q g (nc) Figure 7: GateCharge Characteristics Capacitance (pf) 8 7 6 5 4 3 2 C oss C iss C rss 5 5 2 25 3 V DS (Volts) Figure 8: Capacitance Characteristics I D (Amps) R DS(ON) limited T J(Max) =5 C ms ms.s s s DC µs Power (W) 8 6 4 2 497 T J(Max) =5 C.. V DS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note F)... Pulse Width (s) Figure : Single Pulse Power Rating Junctionto Ambient (Note F) Z θja Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T A P DM.Z θja.r θja R θja =5 C/W T C = C Single Pulse In descending order D=.5,.3,.,.5,.2,., single pulse 55 to 75 P D T on T...... Pulse Width (s) Figure : Normalized Maximum Transient Thermal Impedance (Note F)
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 2 I D (A), Peak Avalanche Current 8 6 4 2 t A = L I D BV V DD Power Dissipation (W) 8 6 4 2.... Time in avalanche, t A (s) Figure 2: Single Pulse Avalanche capability 25 5 75 25 5 75 T CASE ( C) Figure 3: Power Derating (Note B) 497 8 Current rating I D (A) 6 4 2 25 5 75 25 5 75 T CASE ( C) Figure 4: Current Derating (Note B)
Gate Charge Test Circuit & Waveform Qg V Qgs Qgd Ig Charge Resistive Switching Test Circuit & Waveforms RL Rg 9% % td(on) t r t d(off) t f t on t off Unclamped Inductive Switching (UIS) Test Circuit & Waveforms L 2 E = /2 LI AR AR BV DSS Id Rg Id I AR Diode Recovery Test Circuit & Waveforms Q = Idt rr Ig Isd L Isd I F di/dt I RM t rr