Chapter 6 High Gain Low Noise Amplifier Design Using Active Feedback In the previous two chapters, we have used passive feedback such as capacitor and inductor as feedback. This chapter deals with the active feedback for the design of low noise amplifier. Active devices are very much useful for achieving enhanced circuit performance without any significant impact on size or cost. Active feedback acts as regenerative feedback, by enhancing the gain of the amplifier. It suppresses the intermodulation distortion and improves the linearity of the amplifier. This feedback is very much useful for improving linearity without significant effect on the noise figure. 6.1 INTRODUCTION Various LNA designs with active feedback have been reported with good performance in achieving lower power consumption, less area and reasonable noise figure using complex and multistage circuits[borremans et al (2008)][Chang et al (2008)]. There are few feedback circuits with marginal performance in obtaining high gain, low NF and high linearity [Ostman et al (2014)][Han et al (2015)] simultaneously with compact low cost designs, since the feedback circuit will have effect on the performance of the entire LNA. In this work a narrow band LNA is designed to have a sub decibel NF less than 0.5 db with improvement in linearity using active feedback technique and simultaneous trade off between low NF and maximum gain is also achieved by using source degenerated inductance methodology. For the design of LNA, pseudomorphic high electron mobility transistor (phemt) technology is used, since phemt technology provides low noise performance as compared to the CMOS technology. 94
6.2 LNA DESIGN The schematic of the proposed active feedback LNA is shown in Figure 6.1. The LC sections L 1 & C 2 and L 7 & C 5 are used as input and output matching sections to have minimum reflections. The C 6 and C 1 are the DC blocking capacitors at the load and source of the LNA. The DC blocking capacitors C 3 and C 7 are used to avoid possible mixing of DC components on either sides of circuit. The imaginary part of the transistor is cancelled using the gate inductance L g. For controlling gain and noise figure, source degenerated inductor L s is used. The C 4 is bypass capacitor. The two transistors T 1 and T 2 are connected in cascode with a DC bias of 6 V and draw a current of 60 ma. Figure 6.1 Schematic of the proposed active feedback low noise amplifier The stability, noise figure, gain and linearity can be greatly influenced by the source degenerated inductor L s. The circuit is comprised of two transistors T 1 and T 2 connected in a cascode fashion and transistor T 3 connected in a regenerative active feedback. The transistors T 1 and T 2 are connected in cascode fashion to improve the transconductance and gain of the LNA. The cascode transistor T 2, hardly introduces 95
noise, since the transistor current gain is approximately equal to 1. The input impedance of the schematic shown in Figure 6.1 is 1 g ( ) m Z j j L g L s L in s j C g s C g s (6.1) From (6.1) it is clear that without degenerated inductor, real input impedance is not possible. So if we choose values of L s and L g such that it resonates out the imaginary part of the input impedance. Therefore the input at operating (resonant) frequency will be equal to the source impedance R s which is given by Z in g m L s R (6.2) S C gs If the source inductor value is increased for input matching and high linearity, there is degradation in NF & gain as the resistance of the inductor [Venkatesh Murthy and Srinivasa Rao (2015)], so the optimum selection of source inductor is required to achieve minimum noise figure. The overall noise factor of the LNA is the combination of noise from the source, load, transistor T 1 and the feedback transistor T 3. The noise factor is calculated and is given as R 1 s 1 R s 1 F 1 g g R g m 3 3 m 3 s g R g A R m 3 m1 s m1 V s R s 1 1 1 g g R m3 3 m3 s g A R m1 V s (6.3) At input matching g m3 is equal to 1 g m 3 R s (1 g R ) m1 L (6.4) g m1 and g m3 are transconductance of devices T 1 and T 3, R s and R L are source and load resistance, A V is open loop voltage gain, and γ 1 & γ 3 are the thermal noise factor of the T 1 and T 3 transistor s noise current. 96
From the above equation (6.3), it is observed that noise is mainly contributed by g m1, g m3 and Av. Larger the value of g m1, lower the noise factor. To boost the transconductance, the transistor is operated with large drain current and minimum gate voltage. Another way of reducing noise figure is to have higher voltage gain. This can be done by choosing proper values of Lg, which has impact on gain, noise figure and linearity. It has been observed from simulations results that as gate bias voltage is increased at the feedback transistor T 3, there is a slight decrease in gain and has no effect on noise figure. But it is affecting the linearity of the device, since the feedback is provided by a nonlinear device. To study the impact of the feedback, the results were simulated without feedback and the results show that there is 2 db fall in gain and IIP3 has reduced to half of its feedback value. The feedback transistor generates second order distortion at the circuit input which propagates linearly to the output [Borremans et al (2008)]. This distortion combines with fundamental tones at the circuit output generate third order distortion. A simplified expression for IIP3 with feedback contribution alone is given by IIP3 8 2 g m 3 3 1 A V K (6.5) where K is slope of g m3. From above equation (6.5), it is observed that IIP3 can be increased by increasing g m3 or by lowering the overall voltage gain. Variation of feedback transistor (T 3 ) gate voltage versus IIP3 and gain is shown in Figure 6.2. Therefore proper selection gate biasing voltage at feedback transistor and source inductance is very important in optimizing linearity and gain. 6.3 EXPERIMENTAL RESULTS To demonstrate the results of this methodology, LNA is fabricated using a phemt transistor (Avago Technologies ATF54143) on a low loss dielectric substrate (RT/duroid 5880) and is shown in Figure 6.3. The schematic shown in Figure 6.1 is used 6 V supply voltage and transistor T 1 and T 2 draw a current of 60 ma and transistor T 3 draws a current of 50 ma. The LNA consumes power of 360 mw from a 6 V supply voltage. The measured results of input and output return losses (S 11 and S 22 ) are less than 10.80 db and are shown in Figure 6.4 and Figure 6.5. The gain (S 21 ) and isolation loss (S 12 ) are measured as 28 db and -39.8 db at 1.3 GHz, which are 97
shown in Figure 6.6 and Figure 6.7. The simulated and measured results of noise figure (NF) is shown Figure 6.8, it is noticed that measured noise figure (NF) is 0.39 db, which is little more than the device NF (The device NF at 1.3 GHz is 0.2877 db), which shows that only 0.1023 db of NF is added from the entire circuit. To perform the linearity P1 db compression point and third order input intercept point (IIP3) were measured. The IIP3 and P1 db were characterized by applying a two tone test with input frequency spacing of 10 MHz. Figure 6.9 shows the measured IIP3 is 33dBm. The measured P1 db compression point is 24 dbm with respect to output power. The performance of the LNA is compared with previously reported works and the summary is given in Table 6.1. Figure 6.2 Variation of feedback transistor T 3 gate voltage versus IIP3 and gain 98
Figure 6.3 Photograph of the practically realized Low Noise Amplifier Figure 6.4 Simulated and measured results of S 11 in db 99
Figure 6.5 Simulated and measured results of S 22 in db Figure 6.6 Simulated and measured results of gain(s 21 ) in db 100
Figure 6.7 Simulated and measured results of S 12 in db Figure 6.8 Simulated and measured results of Noise Figure (NF) in db 101
Figure 6.9 Measured result of third order input intercept point (IIP3) in dbm Table 6.1 Comparison with previously reported works and performance summary for active feedback LNA Freq Gain NF IIP3 Ref. Tech. Remarks (GHz) (db) (db) (dbm) This Work phemt 1.3 28 0.39 33 [Venkatesh Murthy and Srinivasa Rao(2015)] [Kobayashshi (2012)] [Li and Serdijn(2012)] phemt 1.3 18.782 0.45 52 GaN HEMT GaAS phemt 0.25-3 20 2.5 11.7 0.3-4 23 0.6-0.8-1 Three transistors are used Single transistor is used 2 transistors are used 7 transistors are used [Gawande and Bradely (2010)] [Shih et al (2009)] [Khalil et al (2008)] [Masud et al (2006)] GaAs Super phemt AlGaN/ GaN HEMT GaN HEMT GaAs phemt 2.45 15 0.3-0.3-3 17.7 2 - Single transistor is used 2 transistors are used 2 18 2 35-2.5 47 0.81 2 12 transistors are used 102
6.4 CONCLUSION A single stage narrow band low noise amplifier at 1.3 GHz is designed using phemt. The cascode transistors and active feedback topologies are used to improve the linearity and gain along with source degenerated topology to improve noise figure, input and output return losses and linearity. The output and input matching circuits are also adapted to have complete power matching. The LNA is successfully demonstrated using simulated and measured results. It is noticed from the measured results that gain is 28 db and the lowest noise figure of 0.39 db and result is closer to the device NF. The output and input return losses are less than 10.8 db. The linearity measurement shows that third order intercept point (IIP3) is 33 dbm and P1 db compression point is 24 dbm. This work is published in the Microwave and Optical Technology Letters, Vol. 58, No.7, pp. 1618-1622, July 2016. 103