This paper was originally presented at the Power Electronics Technology Exhibition & Conference, part of PowerSystems World 2005, held October 25-27, 2005, in Baltimore, MD. To inquire about PowerSystems World 2006, October 24-26, 2006, please contact jcharno@primediabusiness.com or visit the website: www.powersystems.com AN OPTIMIZED SPECIFIC MOSFET FOR TELECOMMUNICATION AND DATACOMMUNICATION APPLICATIONS by John (Bang Sup) Lee Senior Staff Application Engineer Vishay Siliconix I. ABSTRACT As the power density requirements of dc-to-dc converters continue to increase, the industry is seeing greater demand for power MOSFET packages with a smaller footprint and improved thermal and electrical characteristics. Among the most important of these electrical characteristics is control over stray inductance. In this paper, we introduce a new application-specific MOSFET (ASM) that serves as a fully optimized buck converter module for telecom and datacom applications. Optimized for synchronous buck architectures, the new device integrates the individual components for a standard buck converter into a single MLF package. The device produces higher performance and improved efficiencies when operated at high frequencies. A buck converter employing the ASM is compared with a standard discrete buck converter solution in terms of the converter performance including parasitic effects. The integrated device helps to reduce conduction losses and switching losses of the buck converter while allowing higher power density levels. In an experimental investigation, parasitic influences are also discussed. II. INTRODUCTION One approach to improving dc-to-dc conversion performance in point-of-load (POL) architectures is to tailor the MOSFET to the specifics of the application. However, merely adding new features or integrating other parts of the circuit is not enough to guarantee a useful product. To make the product useful, the needs of the application must be understood and the product must be optimized accordingly. In this paper we discuss a fully optimized application-specific MOSFET device that replaces two discrete MOSFETs and a driver IC, resulting in a significant increase in performance as well as power density. This integrated solution will simplify designs, allow higher switching frequencies, and reduce the parasitics associated with conventional discrete solutions. The new device is optimized for POL applications where the input voltage is 12 V and the output voltage is between approximately 0.8 V to 3.3 V with high output currents. The device can also be used in multiphase buck configurations with high levels of current and fast load transients. Figure 1 and 2 show respectively the
SiC710 s thermally enhanced 10-mm by 10-mm MLF package and a functional block diagram for the device. Figure 1. Package outline of SiC710 (MLF 10x10) Figure 2. Block Diagram of SiC710 III. OPTIMIZATION OF MOSFET The SiC710 integrates power MOSFETs and a driver in the same package. The MOSFET components of the device are designed to meet a specific set of requirements for the dcto-dc converter application, including the following: 1. Low r DS(on) on-resistance and low Q gd switching losses, as enabled by new MOSFET process technologies 2. The size of the MOSFET is carefully designed to provide a good compromise between power dissipation and size. 3. The high-side MOSFET is designed to minimize the Q gd and R g for fast switching times.
4. The low-side MOSFET is designed to have low r DS(on), low R g for fast switching times, and a low Q gd /Q gs ratio to eliminate shoot-through conditions Figure 3. SiC710 packaging diagram. IV. OPTIMIZING THE DRIVER The extent to which the MOSFET driver is optimized can have a significant effect on how much cross-conduction takes place during the two transition periods of the switching cycle, i.e. from high-side turn-off to low-side turn-on and from low-side turn-off to highside turn-on (dead time). The first event is typically controlled through adaptive switching, which ensures that the high-side MOSFET is turned off before the low-side MOSFET is turned on. The SiC710 provides a reference voltage called V BBM. The comparator monitors the SW node to prevent the low-side MOSFET from turning on until the SW node voltage goes below the V BBM reference voltage. This ensures that both MOSFETs are not turned on at same time. The second transition is usually takes place within a fixed time. When this time is too long, the low-side body diode will conduct and thereby reduce the efficiency of the circuit due to the long body diode conduction. But if the dead-time is too short, excessive cross-conduction losses can result. An optimized dead time will therefore minimize body diode conduction and as well as allowing some cross-conduction. This can effectively reduce the peak ringing voltage on the MOSFET, putting less stress on the device and allowing the use of a lower V DS -rated MOSFET for improved performance or reduced cost. Another aspect of optimizing MOSFET drivers is adjusting gate impedance to help ensure an off state gate voltage during any shoot-through conditions when the high-side
MOSFET is turned on. In the SiC710, the integrated driver provides currents up to 4.1 A and a maximum switching frequency of 1 MHz. The driver in the SiC710 is designed to eliminate any shoot-through currents in the output MOSFET stage by integrating a breakbefore-make circuit topology. Table 1 shows the key parameters of the SiC710. Table 1. Key Parameters of SiC710 Input Voltage (V IN ) 12 V typical Power Stage Output Voltage (V OUT ) 0.5 V~5 V Maximum Output Current (I OUT, max) 27 A * Efficiency 90% ** Logic Input Voltage (V DD ) 5 V typical Driver High-Side Maximum Drive Current 4.1 A Low-Side Maximum Driver Current 3.0 A Switching Frequency From 100 khz to more than 1 MHz r DS(on) @ 4.5 V, I D = 20A High Side 4.5 mω Low Side 4 mω MOSFET Q g High Side 40 nc Low Side 70 nc Q gs High Side 15 nc Low Side 20 nc Q gd High Side 11 nc Low Side 24 nc V th High Side 1.6 V Low Side 1.8 V Thermal Junction to air, R th(j-a) 66.8 o C/W Resistance Junction to case, R th(j-c) 1.1 o C/W Junction to top, R th(j-t) 2.3 o C/W Applications Point Of Load (POL) High-Current Synchronous Buck Converter Multiphase DC/DC Buck Converter * 12 V IN /1.3 V OUT, 300 khz, T a = 25 C, LFM = 0 **12 V IN /1.3 V OUT, 300 khz, I OUT = 7 A, T a = 25 C, LFM = 0 V. PARASITIC INDUCTANCE EFFECT The PCB layout is very important in high-frequency switching converter designs. In switching converters with frequencies greater than 100 khz, the switching current transitions from one device to another can cause voltage spikes and ringing across the devices impedances and parasitic circuit elements. These voltage spikes and ringing degrade efficiency, radiate noise into the system, and lead to device overvoltage stress. Since the three components of the SiC710, two MOSFETs and a driver IC, are integrated into a single MLF package, the parasitic inductances caused by conventional discrete packages and PCB layout are drastically reduced, making a significant contribution to dcto-dc performance.
Figure 4 shows the efficiency comparison calculated as a function of the switching frequency for V IN = 12 V, V OUT = 1.2 V, I OUT = 20 A. It compares a discrete solution and the SiC710 in a buck converter configuration. Efficiency [%] 89 87 85 83 81 79 77 75 73 SiC710 Discrete 300 500 700 1000 Switching Frequency [khz] Figure 4. Efficiency comparison by Simulation The curves differ by the values of the parasitic components included in the converter circuit. The parasitic inductance used in the simulation is 2 nh, although this is not a realistic number in the real PCB layout. It could be much more, in fact, depending on the PCB layout (10- ~ 20-nH range). The purpose of this simulation is to show how much difference even a small amount of inductance can make on the discrete solution. The next figures show the difference in ringing for the SiC710 and a circuit built with individually packaged devices. HS_Ld HS_Ls L Vin LS_Ld LS_Ls Vo Figure 5. Synchronous Buck Converter with PCB trace parasitic inductance The baseline for the comparison was the performance simulated for a SiC710 assembly, where the package inductance was assumed to be 1.5 nh at the drain-to-source terminals.
In other words, the simulation for SiC710 package represented a more or less ideal case. Then the PCB parasitic components were introduced into the circuit individually and their impact on the V SW ringing and the resulting performance was investigated. Figure 5 shows a synchronous buck converter that includes PCB trace parasitics. η=76.4% (a) Sic710 HS_Ld=0, HS_Ls=0, LS_Ld=0, LS_Ls=0 η=75.8% η=74.1% (b) Discrete with HS_Ld=2nH, HS_Ls=0, LS_Ld=0, LS_Ls=0 (c) Discrete with HS_Ld=0, HS_Ls=2nH, LS_Ld=0, LS_Ls=0 η=75.9% η=76.6% (d) Discrete with HS_Ld=0, HS_Ls=0, LS_Ld=2nH, LS_Ls=0 (e) Discrete with HS_Ld=0, HS_Ls=0, LS_Ld=0, LS_Ls=2nH Figure 6. Effects of PCB trace inductance of 2nH in terms of locations
An inductance of 2nH introduced at the drain node of the high-side switch results in a significant ringing of the V SW node but has a very small impact on the converter efficiency (see Figure 6(a) and 6(b)). This is because the high-side drain inductance generates an oscillation of the supply voltage but doesn t have much effect on the switching losses. In the opposite case, where the same parasitic inductance is introduced on the source side of the high-side switch (see Figure 6(a) and 6(c)), efficiency is reduced markedly while the increase in ringing amplitude is only moderate. This is because the source inductance slows down the switching frequency of the device, increasing the switching losses of the high-side transistor. The same parasitic components at the low-side switch have a different effect. The drain side inductance has a moderate impact on the ringing and reduces the efficiency slightly (see Figure 6(a) and 6(d)). It is interesting to note that the source parasitic inductance of the LS switch has a slightly positive effect on the efficiency (see Figure 6(a) and 6(e)). However, the source parasitic inductance represents an external PCB trace to ground. This means that the positive same effect will be observed in either a discrete solution or in solutions using the SiC710, because the source inductance of the MOSFETs is a function of thepcb trace. The observations made in this study have been summarized in the following tables. PCB Trace Parasitic Inductances at the HS-switch: Par. Comp. Impact Vpeak tringing Efficiency Ld Ls oscill. of suppl voltage slows HS-transistor PCB Trace Parasitic Inductances at the LS-switch Par. Comp. Impact Vpeak tringing Efficiency Ld Ls oscill. of VL node slows LS-transistor As we have seen, the ringing is severely influenced by the drain inductance of the highside device, and the reduction in efficiency can be accounted for mainly by the parasitic components between the source of the high-side switch and the drain of the low-side switch. Even small changes in the parasitic components can have a significant impact on the ringing and lead to quite different calculated efficiency values. VI. EXPERIMENTAL RESULTS An SiC710 demo board and a two-phase buck converter board (designed by one of the major power supply controller manufacturers) were used to compare the performance of the SiC710 and discrete solution. Figure 7 shows the switching node waveform that was obtained from one of the PWM controller supplier s EVM boards now available on the market. The waveform shows a
lot of oscillation and spikes due to the PCB layout parasitic inductances. Figure 8 shows the same voltage node obtained from the Vishay Siliconix SiC710 under the same input/output voltage conditions. Employing the SiC710 reduces the switching spikes, resulting in low noise and higher performance. By reducing the parasitic inductances, efficiency improvements can be made as well. Figures 7 and 8 show the SiC710 efficiency and its losses, respectively. The most efficient measurement was nearly 90% at a 7-A load and device switching frequency of 300 khz. (a) Iout=40A (b) Iout=4A Figure 7. Switch node voltage (Vsw) from one of major PWM controller supplier EVMs (12 V IN /1.3 V OUT, 300 khz, LFM = 0, T a = 25 C) Figure 8. Switch node voltage (Vsw) from SiC710 (12 V IN /2.5 V OUT, I OUT = 20 A, 500 khz LFM = 0, T a = 25 C)
95.00 Sic710, 12Vin/1.3Vo, Ta=25oC, LFM=0 Efficiency - % 90.00 85.00 80.00 75.00 70.00 65.00 60.00 55.00 0.000 5.000 10.000 15.000 20.000 25.000 Output Current - A Sic710 300KHz Sic710 500kHz Sic710 700kHz Figure 9. SiC710 Efficiency (12 V IN /1.3 V OUT ) Total Loss - W 9.0000 8.0000 7.0000 6.0000 5.0000 4.0000 3.0000 2.0000 1.0000 0.0000 SiC710, 12 VIN/1.3VOUT, Ta = 25oC, LFM = 0 0.000 5.000 10.000 15.000 20.000 25.000 Output Current - A Sic710 Total Loss 300khz Sic710 Total Loss 500khz Sic710 Total Loss 700khz Figure 10. SiC710 total losses (12 V IN /1.3 V OUT )
SiC710, 12 VIN/3.3 VOUT, Ta = 25 C, LFM = 0 Efficiency - % 96 94 92 90 88 86 84 82 80 0.00 5.00 10.00 15.00 20.00 25.00 Output Current - A 300kHz 500kHz 700kHz Figure 11. SiC710 Efficiency (12 V IN /3.3 V OUT ) VII. CONCLUSIONS In this paper, we describe a single-package device in which three components a highside MOSFET, low-side MOSFET, and MOSFET driver have been integrated and optimized. The optimization is based on detailed device characterization and a synchronous buck converter simulation. An analysis of PCB parasitic inductances shows that the drain inductance degrades the performance of a buck converter while the source inductance helps, slightly, to improve the efficiency. This makes it obvious why an integrated solution provides better performance than a discrete implementation. The experimental results confirm the predictions from simulations, indicating that integration of three components will reduce the switching spikes and ringing, resulting in improved switching losses. VIII. REFERENCES [1] Jess Brown, Modeling the Benefits of Using a Thick Bottom Oxide Gated MOSFET (WFET) with Increased Switching Performance in the High Side of a Non-Isolated Buck Converter, APEC 2004, California, USA [2] A. Elbanhawy, Effect of Parasitic Inductance on Switching Performance in Proc. PCIM Europe 2003, pp. 251-255 [3] A. Elbanhawy, MOSFET Susceptibility to Cross Conduction, in Power Electronics Technology, April 2005 [4] Y.Xiao, H. Shah, T.P. Chow and R.J. Gutmann, Analytical Modeling and Experimental Evaluation of Interconnect Parasitic Inductance on MOSFET Switching Characteristics, APEC2004, California, USA.