ACPL-P346/W346 Isolated Power MOSFET Gate Driver Evaluation Board User's Manual Quick Start Visual inspection is needed to ensure that the evaluation board is received in good condition. All part references are designated with suffix a and b to indicate the lower and the upper inverter arms, respectively. If part references are made without suffixes, then they are valid for both upper and lower inverter arms (except R6, which is shared). Figure shows the default connections of the evaluation board:. Q and Q2 are not mounted. Actual Power MOSFET can be mounted at either Q (for TO-220 package) or Q2 (for TO247 package) or connected to the driver board through short wire connections from the holes provided at Q or Q2. 2. D4 and R7 are not mounted (on solder side). A 2 V Zener diode footprint at D4 is provided to allow for a single DC power supply of V ~2 V to be applied across VCC2 and VEE if needed. A virtual ground VE (at Source pin of Q or Q2) can then be generated and it acts as the reference point at the source pin of each power MOSFET. VCC2 will then stay at 2 V above the virtual ground VE. R7 is needed to generate the bias current across D4. 3. S2 and S3 jumpers are shorted by default to connect VE to VEE, assuming that a negative supply is not needed. Note: If a negative supply is needed, then S2 and S3 jumpers must be removed. 4. Bootstrap diode D3b and resistor R6 are connected by default. These two components are provided to help generate VCC2b supply through bootstrapping assuming that VCC2a supply is available. Note: Bootstrapping supply works only when Q or Q2 are mounted in a half-bridge configuration and turned on and off through proper PWM driving signals.. S is shorted by default to ground the IN- (or LED-, the cathode of LED) pin when VCC is supplied. This short can be removed if IN- cannot be grounded. 6. Upper and lower arms of the inverter will have common VCC (and GND), a provision is made to allow VCC to be connected by solder between upper and lower inverter PCB portions (and GND on the solder side). R6 mounted (shorted) VCCa and VCCb (shorted) GNDa and GNDb on solder side (also shorted) 7. Provisions are also made to allow VCC2 (and VEE) to be generated from VCC through a DC/DC converter at IC2. When this DC/DC converter is used, S2, S3 (and R6) should be disconnected. VCCb VCCa S (shorted) S2 (shorted) Figure. Actual ACPL-P346/W346 evaluation board showing default connections S3 on solder side (also shorted)
Once inspection is done, the evaluation board can be powered up in five simple steps. Figure 2 shows you how to test the top or the bottom half-bridge inverter arms in simulation mode without the need for an actual power MOSFET. Testing both arms of the half-bridge inverter driver (without a power MOSFET). Solder a 0 nf capacitor across the gate and emitter terminals of Q or Q2. This is to simulate actual gate capacitance of a power MOSFET. 2. Connect a + V DC supply (DC supply ) across the +V and GND terminals of CON. 3. Connect another DC supply (DC Supply 2 with voltage range from 2 V ~ 20 V) across V CC2 (pin 7 of IC2) and V EE (pin of IC2) terminals of IC2a, respectively. This can be non-isolated for testing purposes. 4. Connect drive signals: a. A 0 khz V DC pulse (at slightly < 0% duty) from a dual-output signal generator across IN+ and IN- pins of CONa to simulate microcontroller output to drive the lower arm of the half-bridge Inverter. b. Another 0 khz V DC pulse (at 80 out of phase to the signal in 4a) from the dual-output signal generator across IN2+ and IN2- pins of CONb to simulate microcontroller output to drive the upper arm of the half-bridge inverter.. Use a multi-channel digital oscilloscope to capture the waveforms at the following points: a. LED signal at the IN+ pin with reference to (w.r.t.) GND. b. LED signal at the IN2+ pin w.r.t. GND. Note: The V CC2b supply of voltage close to V CC2a should then be successfully generated through the built-in bootstrap components D3b and R6. c. V Ga representing the output voltage of ACPL-P346/W346 (ICa) at the gate pin of Qa (or Q2a) w.r.t. V Ea. d. V Gb (through an isolated probe) representing the output voltage of ACPL-P346/W346 (ICb) at the gate pin of Qb (or Q2b) w.r.t. V EB. In2- In2+ 4b b Signal Input 0nF d In- In+ - V CC2b + V Eb 4a a Signal Input 0nF c V Ea DC Supply Gnd +V 2-3 + 2~20 V DC Supply 2 Figure 2. Simple Simulation Test Setup of Evaluation Board 2
Schematics Figure 3 shows the schematics of the evaluation board: CONb LEDb+ LEDb- V CCb GNDb Rb 249R R3b R2b 30R Sb ICb ACPL-P346 3 4 V EEb IC2b 6 Cb 0.µF 2 TP4b 7 TP2b 6 TP3b V CC2b R7b TPb R4b 4R7 W SS32 Rb Db S2b SMBJCA V CC2b BYM26F D3b C2b S3b 0 µf T a C3b 0 µf T a D4b D2b G D S V Eb TO220/TO247 Qb/Q2b CONa LEDa+ Ra 249R ICa ACPL-P346 6 Ca 0. µf V CC2a V EEb R7a D4a 4R7 W R6 LEDa- V CCa GNDa R3a R2a 30R Sa 3 4 V EEa 2 IC2a R0P22D/R8 7 TP2a 6 TP3a TP4a TPa R4a 4R7 W SS32 Ra Da V CC2a C2a S3a 0µF T a C3a 0µF T a V EEa S2a SMBJCA BYM26F D3a D2a G D S V Ea TO220/TO247 Qa/Q2a Figure 3. Schematics of ACPL-P346/W346 evaluation board 3
Practical connections of the evaluation board using a power MOSFET for an actual inverter test. Solder actual power MOSFETs at Q (or Q2) for the top and bottom arms of the half-bridge inverter isolated drivers. 2. Connect a +V DC isolated supply across +V and GND terminals of CON for both arms of the isolated drivers. 3. Connect another isolated DC supply2 (voltage range from 2 V ~ 20 V) across V CC2a and V EEa at pin 7 and pin of IC2a respectively for the bottom arm. 4. Connect the signal output (meant to drive the bottom arm of the half-bridge inverter) from the microcontroller to Signal Input across pin IN+ and IN- of CONa of the bottom inverter arm isolated driver.. Connect the signal output (meant to drive the top arm of the half-bridge inverter) from the microcontroller to Signal Input 2 across pin IN2+ and IN2- of CONb of the top inverter arm isolated driver. Note: Signal Input 2 should be 80 out of phase w.r.t. Signal Input. Check that V CC2b (voltage close to V CC2a ) is generated through the bootstrap components D3b and R6. 6. Use a multi-channel digital oscilloscope to capture the waveforms at the following points: a. LED signal at IN+ pin w.r.t. GND for the bottom arm. b. LED signal at IN2+ pin w.r.t. GND for the top arm. c. Vga for the gate driving voltage of Qa (or Q2a) w.r.t. V Ea of the bottom inverter arm (differential probe needed). d. Vgb for the gate driving voltage of Qb (or Q2b) w.r.t. V Eb of the top inverter arm (differential probe needed). 7. Connect a power cable from the output pin (marked Load) to the inverter load. 8. Connect the high voltage cables from the top arm power MOSFET drain pin to HVDC+ and from the bottom arm power MOSFET source pin to HVDC-, respectively, as shown. (Note: It is recommended that you enable the currentlimiting function of the HV power source supplying the high voltage DC bus voltage during this test to protect the inverter and its driver circuitries). 8 HVDC+ 6d IN2+ IN2-6b Signal Input 2 Power MOSFET mounted Microcontroller IN+ 6a Signal Input IN- 4 2~20V 3 + 6c Power MOSFET mounted 7 Load DC Supply 2 GND +V + 2~20 V DC Supply2 HVDC 8 Figure 4. Connection of evaluation board in actual applications 4
Application Circuit Description The ACPL-P346/ACPL-W346 is an isolated gate driver that provides 2. A output current. The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving of MOSFET with ratings up to 000 V/00 W. It is also designed to drive different sizes of buffer stage that will make the class of power MOSFET scalable. ACPL-P346 (and ACPL-W346) provides a single isolation solution suitable for both low and high power ratings of motor control and inverter applications. Each of the ACPL-P346/ACPL-W346 evaluation boards, as shown in Figure, accommodates two ACPL-P346/ACPL-W346 ICs. Therefore, each board is enough to drive the top and the bottom arms of the half-bridge inverter. It allows the designer to easily test the performance of a gate driver in an actual application under real-life operating conditions. Operation of the evaluation board requires merely the inclusion of a common V DC isolated Supply on the input side and an isolated DC Supply2 (range from 2 V ~ 20 V) for the bottom arm of the inverter power MOSFET, while the DC supply needed for the top arm is easily generated through bootstrapping included in the evaluation board. Note: As can be seen on the board, the isolation circuitry (at the far left) is easily contained within a small area while maintaining adequate spacing for good voltage isolation and easy assembly. Figure. Top and bottom views of ACPL-P346/W346 evaluation board
Using the Board It is easy to prepare the evaluation board for use. You just need to solder cables for DC supplies, have proper cables for HVDC+/HVDC- high voltage bus, and load connections. The evaluation board has a default connection as shown in Table when it is shipped to the customer. We offer several power supply schemes from which you can choose. Power Supply Schemes The evaluation board is built with DC supply flexibility in mind; choose a power supply scheme from the seven available. Table shows all the possible power supply schemes that work for the evaluation board. A description of each scheme is given; you are encouraged to explore each scheme and decide which one works best for your needs:. Scheme is the simplest and possibly the cheapest scheme. A + V isolated DC supply is supplied externally to power the low voltage V cc circuit. Another external supply (+2 V~20 V for V cc2a ) is needed for the gate driver driving the power MOSFET at the bottom inverter arm. V cc2b supply is obtained from V cc2a by bootstrapping. For this to work, the bootstrap components D3b and R6 must be connected, all S2 jumpers must be shorted so that no negative supply of V ee is allowed, and the Signal Input 2 is at 80 out of phase to Signal Input. All S2 jumpers are shorted to connect V ee to V e so that there are no negative supplies. S3 jumpers are shorted by default but this has no effect on actual operation of the board. Contact Avago Technologies if bootstrapping operation works are required. 2. Scheme 2 is similar to Scheme : it has V cc and V cc2a supplies. However, as the power MOSFET used gets bigger, so does the driving power. Because a bootstrapped power supply can only handle a lower driving power, it is not suitable for use when Qg of power MOSFET rises above 200 nanocoulombs (nc). A third external supply (+2 V~ 20 V for V cc2b ) will be needed. 3. Scheme 3 is similar to Scheme 2 in that it uses three external supplies at V cc, V cc2a and V cc2b. Scheme 3, however, has the advantage of getting negative supplies for V ee (or V eea and V eeb ) by introducing a 2 V Zener diode at D4 and R7 of around kω to provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must be open while the external supplies (+ V ~ 24 V) on the high voltage driver side are to be connected across V cc2 and V ee pins only, not the V e pin. As the external supply changes from + V to +24 V, V cc2 will stay at +2V, but V ee changes from -3 V to -2 V, all w.r.t. virtual ground at V e. 4. Scheme 4 is another simple scheme; an alternative to Scheme. Here, only one external supply for V cc is needed. V cc2a is obtained by a lower power DC/DC converter at IC2a, with V cc as V in and +2 V output at V cc2a w.r.t. V ea. V cc2b supply is obtained from V cc2a by bootstrapping. For this to work, the bootstrap components D3b and R6 must be connected, all S2 jumpers must be shorted so that no negative supply of V ee is allowed, and the Signal Input 2 should be 80 out of phase to Signal input. S2 is shorted to connect V ee to V e so that there is no negative supply. S3 jumpers are shorted by default but this has no effect on actual operation of the board.. Scheme is similar to Scheme 4: it has V cc and a DC/DC converter for V cc2a. However, as the power MOSFET used gets bigger, so does the driving power. Because a bootstrapped power supply can only handle a lower driving power, it is not suitable for use when Qg of power MOSFET rises above 200 nanocoulombs (nc). A second DC/DC converter at IC2b with V cc as V in and +2 V output at V cc2b w.r.t.v eb. All S2 jumpers are shorted to connect V ee to V e so that there are no negative supplies. S3 jumpers are shorted by default but this has no effect on actual operation of the board. 6. Scheme 6 is similar to Scheme with the use of V cc and two DC/DC converters. Each DC/DC converter, however, has dual outputs set at ±2 V to allow for the availability of negative V ee (at V eea and V eeb ). Therefore, all S2 jumpers must be open, while all S3 jumpers must be shorted. 7. Use Scheme 7 if dual-output ±2 V DC/DC converters are not available or dual-output ±9 V DC/DC converters are preferred. 2 V V cc2 can still be obtained using ±9 V DC/DC converters by introducing a 2V Zener diode at D4 and R7 of around kω to provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must be open. As the total voltage across V cc2 w.r.t. V ee stays at 8V (=9V+9V), V cc2 of 2 V will be obtained through the 2 V D4 Zener diode, and -6V at V ee, all w.r.t. virtual ground at V e. 6
Table. Power Supply Schemes + V 2 + V 3 + V 4 + V + V 6 + V 7 + V V cc V cc2a V eea S2a S3a +2V~20V +2V~20V 0 V s/c s/c Bootstrapped from V cc2a (+2V~20V) 0 V s/c s/c +2V~20V +V~24V open open 2V/ k D4a/ R7a V cc2b V eeb S2b S3b 2V -3V~-2V 2V -3V~-2V DC/DC (=V cc /+2V) DC/DC (=V cc /+2V) 0 V s/c s/c Bootstrapped from V cc2a (+2V) 0V s/c s/c DC/DC (=V cc /+2V) D4b/ R7b Remarks 0 V s/c s/c Default (simplest) - Two external supplies needed for V cc and V cc2a 0 V s/c s/c Higher Power - Three external supplies needed for V cc, V cc2a and V cc2b +V~24V open open 2V/k V ee available - Three external supplies needed for V cc, V cc2a and V cc2b - Virtual gnds V ea and V eb generated through D4 and R7 0 V s/c s/c Cheap - One single output DC/DC converter for V cc2a - Only one external supply is needed (V cc ) 0 V s/c s/c Higher Power - Two single output DC/DC converters for V cc2a and V cc2b - Only one external supply is needed (V cc ) DC/±DC (=V cc /±2V) open s/c DC/±DC (=V cc /±2V) open s/c V ee available - Two dual output DC/DC converters for V cc2a,v cc2b, V eea +2V -2V +2V -2V and V eeb - Only one external supply is needed (V cc ) DC/±DC (=V cc /±9V) open open 2V/ k +2V -6V +2V -6V DC/±DC (=V cc /±9V) open open 2V/k V ee available - Dual output DC/DC converters for V cc2a and V cc2b - only external supply is needed (V cc ) - Virtual gnds V ea and V eb generated through D4 and R7 Note: As TVS D2 voltage is selected at a breakdown voltage of 2.2 V, it is not advised to set both V cc2 and V ee voltage at a voltage beyond ±2 V. To use a voltage higher than 2 V, please replace D2 with a bigger clamping voltage. 7
Output Measurement A sample of input LED and various output waveforms are captured and shown in Figure 6. The default setup connection is adopted, except with Qa and Qb power MOSFETs are mounted. The power MOSFETs used have a gate capacitance equivalent to 0 nf. Figure 6. Input LED signal and Power MOSFET Gate Voltage Waveforms Figure 6 also shows that, once a bootstrap supply is adopted, the amplitude of the output voltage at the top inverter arm will be slightly smaller than that of the bottom inverter arm, at 80 out of phase. (IN+ is set at 49% duty ratio, while IN2+ (not shown) is also set with 49% duty ratio, plus a turn-on delay of 00 ns with respect to IN+). Figure 7 shows the turn-off signal of IN+, the turn-off signal at gate of Qa, and the turn-on signal at gate of Qb. Figure 7. Turn-off and Turn-on Gate waveforms of Qa and Qb 8
Figure 8 shows the turn-on signal of IN+, the turn-on signal at gate of Qa and the turn-off signal at gate of Qb. Figure 8. Turn-on and Turn-off Gate waveforms of Qa and Qb As can be seen from Figure 7 and Figure 8, the turn-off speed of the power MOSFET will be slow, due to the capacitive effects of D2 and the gate capacitance of Q. To improve the turn-off speed, the board is provided with a diode resistor pair footprints at D and R (not mounted ) to increase the gate current during turn-off. Another way to further improve the turn-on and turn-off speed is by reducing the gate resistance of R4, but make sure the gate drive current is not more than 2. A. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 200-203 Avago Technologies. All rights reserved. AV02-40EN - May 2, 203