March 12, 2004 Cypress CY7C68013-56PVC USB 2.0 Integrated Microcontroller Process Analysis Introduction... Page 1 List of Figures... Page 2 Device Summary... Page 6 Device Identification Package and Assembly Analysis Major Microstructural Features Selected Layout Features For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2004 Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information.
Process Analysis Page 2 List of Figures Device Identification 0.1.1 Package Photographs 0.1.2 Package Photograph (Side View) and Package X-Ray 0.1.3 Die Marking 0.1.4 Die Photograph 0.1.5 Annotated Die Photograph Package and Assembly Analysis 1.1.1 Package X-Ray 1.1.2 Package Cross-Section (Composite) 1.1.3 External Lead Plating 1.1.4 Detail of Stitch Bond 1.1.5 Overall View of Die Mounting 1.1.6 Thermosonic Ball Bond 1.1.7 Die Edge (Top) 1.1.8 Die Edge (Bottom) 1.2.1 EDS Spectrum of External Package Lead 1.2.2 EDS Spectrum of External Lead Plating 1.2.3 EDS Spectrum of Internal Lead Plating 1.2.4 EDS Spectrum of Bond Wire 1.2.5 EDS Spectrum of Die Attach
Process Analysis Page 3 Major Microstructural Features 2.1.1 Typical Die Corner 2.1.2 Typical Die Corner 2.1.3 Die Edge 2.1.4 Edge Seal Ring 2.2.1 Bond Pad Layout 2.2.2 Bond Pad Spacing 2.2.3 Bond Pad 2.2.4 Bond Pad 2.2.5 Bond Pad 2.2.6 Bond Pad 2.3.1 General Device Structure 2.3.2 Metal 3 Spacing 2.3.3 Metal 3 Profile 2.3.4 Via 2's 2.3.5 Detail of a Via 2 2.3.6 Metal 2 Spacing 2.3.7 Metal 2 Composition 2.3.8 Via 1 Spacing 2.3.9 Metal 2 Composition 2.3.10 Metal 1 Spacing 2.3.11 Metal 1 Composition 2.3.12 Contact to Poly 2.3.13 Contact to Poly 2.3.14 Contact to N + 2.3.15 Contact to P + 2.4.1 Transistor Structure 2.4.2 Contact Region 2.4.3 Gate Dielectric 2.4.4 NMOS Transistors
Process Analysis Page 4 2.4.5 PMOS Transistors 2.5.1 Bird s Beak Profile 2.5.2 Wells 2.5.3 Wright Etch of Substrate 2.6.1 PNP Array 2.6.2 PNP Transistors 2.6.3 PNP Transistor 2.6.4 Capacitor Structure 2.6.5 Topological View of Gate Poly vs. Routing Poly 2.6.6 Topological View of Gate Poly vs. Routing Poly 2.6.7 SRAM Array 2.6.8 SRAM Array 2.7.1 Passivation 2 2.7.2 Passivation 1 2.7.3 Metal 3 Cap 2.7.4 Metal 3 2.7.5 Metal 3 Adhesion Layer 2.7.6 Metal 2 Cap 2.7.7 Metal 2 2.7.8 Metal 2 Adhesion Layer 2.7.9 Metal 1 2.7.10 Metal 1 Adhesion Layer 2.7.11 Sealant Dielectric 2.7.12 Plug Fill 2.7.13 Plug Liner 2.7.14 Silicide 2.7.15 Source/Drain Region 2.7.16 Gate Cap 2.7.17 Gate Dielectric 2.7.18 Region Beneath Sidewall Spacer
Process Analysis Page 5 Selected Layout Features 3.0.0 Annotated Die Photograph Metal 3 3.1.1 Power Line Redundant Vias Between M2 and M3 Photograph of Metal 2 3.1.2 Power Line Redundant Vias Between M2 and M3 Photograph of Metal 3 3.1.3 Signal Line Redundant Vias Between M2 and M3 Photograph of Metal 2 3.1.4 Signal Line Redundant Vias Between M2 and M3 Photograph of Metal 3 3.2.1 Multiple Power Conductors Over SRAM Array Metal 3 3.2.2 Multiple Power Conductors Over SRAM Array Metal 2 3.2.3 SRAM Array Metal 1 3.2.4 SRAM Array Poly 3.3.0 Standard Cell Poly 3.3.1 Standard Cell Metal 1 3.3.2 Standard Cell Metal 2 3.3.3 Standard Cell Metal 3 3.4.0 Annotated Analog Area Poly 3.5.1 Bipolar Transistor Poly 3.5.2 Bipolar Transistor Metal 1 3.5.3 Bipolar Transistor Metal 2 3.5.4 Bipolar Transistor Metal 3 3.6.1 Resistor Poly 3.6.2 Resistor Metal 1 3.7.1 MOS Capacitor Poly 3.7.2 MOS Capacitor Metal 1 3.7.3 MOS Capacitor Metal 2