INTEGRATED 100-V IEEE 802.3af PD AND DC/DC CONTROLLER

www.ti.cm APPLICATIONS All PE PD Devices Including: Wireless Access Pints VIP Phnes Security Cameras INTEGRATED 100-V IEEE 802.3af PD AND DC/DC CONTROLLER FEATURES DESCRIPTION Cmplete 802.3af PE Interface The integrates the functinality f the Features derived frm the TPS2375 TPS2375 with a primary-side dc/dc PWM cntrller. 100 V, 0.6 Ω Internal Pass MOSFET The designer can create a frnt-end slutin fr PE-PD applicatins with minimum external Standard and Legacy UVLO Chices cmpnents. The is identical t the Fixed 140 ma Inrush Limit with the exceptin f the undervltage Primary Side DC/DC Cnverter Cntrl lckut turn-n vltage, which is cmpatible with legacy systems. Minimum External Cmpnent Cunt Current Mde Cntrl The PE frnt end has all the necessary IEEE 802.3af functins including detectin, classificatin, Islated and Nn-Islated Tplgies undervltage lckut and inrush cntrl. The PE Prgrammable Operating Frequency input switch is integrated within the. Current Sense Leading-edge Blanking The dc/dc cntrller sectin is designed t supprt 50% Duty Cycle Limiting flyback, frward, and nnsynchrnus lw-side switch Vltage Output Errr Amplifier buck tplgies. Internal PE and Cnverter Sequencing The external switching MOSFET and current sense Industry-Standard 20 Lead Package resistr prvide flexibility in tplgy, pwer level, and current limit. The full-featured dc/dc cntrller in- Industrial Temperature Range: 40 C t 85 C cludes prgrammable sft start, hiccup type fault limiting, 50% maximum duty cycle, prgrammable cnstant switching frequency, and a true vltage-utput errr amplifier. Additinal prtectin fea- tures prvide fr rbust designs. Frm Ethernet Transfrmers V DD V BIAS COMP V BIAS FREQ TMR T P S 2 3 7 5 0 AUX GATE RSP V BIAS C TMR RSN COM RTN FB SEN Frm Spare Pairs r Transfrmers 0.1 F 5 8 V R DET R CLASS DET CLASS V SS BL MODE V DD Lw Vltage Islated Output C BIAS SENP TLV431 Figure 1. Typical Applicatin Please be aware that an imprtant ntice cncerning availability, standard warranty, and use in critical applicatins f Texas Instruments semicnductr prducts and disclaimers theret appears at the end f this data sheet. PwerPAD is a trademark f Texas Instruments. PRODUCTION DATA infrmatin is current as f publicatin date. Prducts cnfrm t specificatins per the terms f the Texas Instruments standard warranty. Prductin prcessing des nt necessarily include testing f all parameters. Cpyright 2005, Texas Instruments Incrprated

www.ti.cm This integrated circuit can be damaged by ESD. Texas Instruments recmmends that all integrated circuits be handled with apprpriate precautins. Failure t bserve prper handling and installatin prcedures can cause damage. ESD damage can range frm subtle perfrmance degradatin t cmplete device failure. Precisin integrated circuits may be mre susceptible t damage because very small parametric changes culd cause the device nt t meet its published specificatins. ORDERING INFORMATION (1) T A 40 C t 85 C UVLO THRESHOLDS PACKAGE (2) TYPE LOW HIGH TSSOP-20 PwerPAD MARKING Standard 30.5 V 39.3 V PWP Legacy 30.5 V 35.1 V PWP (1) Add an R suffix t the device type fr tape and reel. (2) Fr the mst current package and rdering infrmatin, see the Package Optin Addendum at the end f this dcument, r see the TI Web site at www.ti.cm. ABSOLUTE MAXIMUM RATINGS ver perating free-air temperature range and with respect t V SS unless therwise nted (1) Input vltage range (2) RSN, COM, RTN, SEN 0.7 V t 100 V Input vltage range AUX, VDD, DET, SENP 0.3 V t 100 V Input vltage range (3) [V BIAS, BL, TMR, FB, COMP, FREQ, RSP, MODE] t RTN 0.3 V t 6.5 V Input vltage range [GATE r AUX] t COM 0.3 V t 20 V Input vltage range [RSN t RTN] and [COM t RTN] 0.3 V t 0.3 V SENP t SEN UNIT 0.3 V t 100 V Input vltage range (3) CLASS 0.3 V t 12 V Surcing current AUX Internally limited V BIAS Surcing current Internally limited Surcing r sinking current, COMP Average surcing r sinking current, GATE HBM ESD rating ESD system level (cntact/air) at RJ-45 (4) Cntinuus ttal pwer dissipatin Internally limited 25 ma rms 2 kv 8 kv / 15 kv See Dissipatin Rating Table T J Maximum perating junctin temperature Internally limited T stg Strage temperature range 65 C t 150 C Lead temperature 1.6mm (1/16-inch) frm case fr 10 secnds 260 C (1) Stresses beynd thse listed under abslute maximum ratings may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated under recmmended perating cnditins is nt implied. Expsure t abslute-maximum-rated cnditins fr extended perids may affect device reliability. (2) I RTN = 0 fr V RTN > 80 V. Maximum I RTN = 500 ma at 80 V. (3) D nt apply external vltage surces t CLASS, DET, GATE, FREQ, V BIAS, and TMR. (4) Surges applied t RJ-45 f Figure 40 between pins f RJ-45, and between pins and utput vltage rails per EN61000-4-2, 1999 with n device failure. 2

www.ti.cm RECOMMENDED OPERATING CONDITIONS (1)(2) All vltage values are with respect t V SS unless therwise nted. DISSIPATION RATINGS TABLE MIN NOM MAX UNIT V DD Input vltage range (3) COM, SEN, SENP 0 67 V FB, COMP, MODE, BL 0 V BIAS Input vltage range AUX t COM 0 16 V RSP t RSN 0 1 AUX 0 2 Surcing current V BIAS 0 2 ma COMP 0 2 Q G GATE lading 20 nc AUX lad capacitance 0.8 25 µf V BIAS lad capacitance 0.08 1.5 µf R FREQ 30 300 kω T J Operating junctin temperature range -40 125 C T A Operating ambient temperature range -40 85 C (1) RSN, COM, and RTN shuld be tied tgether. SENP shuld be tied t V DD except fr the buck cnfiguratin, where it shuld be tied t the utput psitive rail. (2) TMR, FREQ, CLASS, DET, V BIAS, and GATE shuld nt be externally driven. (3) Junctin temperature may be a cnstraining factr fr high bias pwer designs. PACKAGE θ JP θ JC θ JA θ JA θ JA MAXIMUM POWER RATING C/W (1) C/W C/W (2) C/W (3) C/W (4) (W) (5) PWP (TSSOP-20) 1.4 26.62 32.6 151.9 73.8 1.2 (1) Thermal resistance junctin t pad. (2) See TI dcument SLMA002 fr recmmended layut. This is a best case, zer airflw number. (3) JEDEC methd with lw-k bard (2 signal layers) and pwer pad nt sldered (wrst case). (4) JEDEC methd with high-k bard (4 layers, 2 signal and 2 planes) and pwer pad nt sldered. (5) Based n TI recmmended layut and 85 C ambient. 3

ELECTRICAL CHARACTERISTICS www.ti.cm Characteristics are fr: 40 C T J 125 C; V DD V SS = 48 V. V DD, CLASS, and DET referenced t V SS, and all ther pin vltages are referenced t RSN, COM, and RTN shrted tgether unless therwise nted. SEN=MODE=BL=RSP=RTN, FB=V BIAS, SENP=V DD, C TMR = 1000 pf, C VBIAS = 0.1 µf, C VAUX = 0.1 µf, R FREQ = 150 kω, R DET = 24.9 kω, R CLASS = 255 Ω, GATE is unladed, and V BIAS and AUX have n external lads unless therwise nted. DC/DC CONTROLLER SECTION RTN = V SS fr this sectin nly. BIAS SUPPLY (VBIAS) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V BIAS Output vltage 0 I LOAD 5 ma 4.60 5.1 5.5 V AUX SUPPLY (AUX) V AUX Supply utput vltage 18 V V VDD COM 57 V, 0 ma I AUX 10 ma 9 10 11 V OSCILLATOR (FREQ) D MAX Current limit V AUX = 0 V 12 23.5 28 ma Maximum duty cycle R FREQ = 30 kω, V COMP = 3.9 V, MODE = V BIAS, Measure GATE 48.8 49.2 49.5 % vltage at 50% rising t 50% falling MODE = V BIAS, V COMP = 3 V, Measure at GATE f OSC Oscillatr frequency R FREQ = 30 kω 435 487 565 khz ERROR AMPLIFIER (FB, COMP) R FREQ = 150 kω 90 100 110 COMP surce current 0 V COMP 4 V, FB = RTN, V TMR = 2.5 V 2.5 ma COMP sink current 1.2 V V COMP V BIAS, V TMR = 2.5 V 2.4 ma V REF FB regulatin vltage V COMP = 2.5 V, V TMR = 2.5 V 1.47 1.50 1.53 V SOFT START TIMER (TMR) Open lp vltage gain 1.2 V V COMP 4 V, V TMR = 2.5 V 80 db Small signal unity gain bandwidth V COMP = 2.5 V, V TMR = 2.5 V 1.5 2 MHz COMP input resistance MODE = V BIAS, 1.1 V COMP 4.4, V TMR = 2.5 V 70 100 130 kω FB leakage (surce r sink) 0 V FB V BIAS, V TMR = 2.5 V 1 µa Surce current TMR charging, V TMR between lwer threshld and clamp 38 50 62 µa Rati f surce/sink current 9 10 11 - ON duty cycle MODE = V BIAS, V COMP = 4.4 V, Secnd cycle and beynd 8 9.1 10 % CURRENT SENSE (RSP, RSN, BL) Current limit threshld Fault current threshld MODE = V BIAS, V COMP = 4.2 V, V TMR = 2.5 V, Increase 0.46 0.5 0.54 V V RSP-RSN until the duty cycle switches frm 50% t the minimum MODE = V BIAS, V COMP = 4.2 V, V TMR = 2.5 V, Increase 0.70 0.765 0.83 V V RSP-RSN until n gate pulses ccur V RSP RSN = 0.6 V, V AUX = 12 V, MODE = V BIAS, V COMP = 4.2 V, V TMR = 2.5 V. Measure 50% f V GATE t 50% V GATE Minimum prpagatin delay, BL flating 40 60 90 t BLNK Current limit delay Blanking perid (pulse width abve minimum), BL cnnected t 45 70 95 ns RSN GATE DRIVER (GATE) Blanking perid (pulse width abve minimum), BL cnnected t 70 105 140 V BIAS FREQ = V BIAS, MODE = V BIAS, V COMP = 4 V, RSP current 2.5 4 8 µa V RSP-RSN = 0.4 V, I RSP surcing Output vltage swing 5 ma surce, V AUX = 12 V 11.9 5 ma sink, V AUX = 12 V 0.05 Peak surce current V AUX = 12 V, pulse test 0.33 0.58 0.8 A Peak sink current V AUX = 12 V, AC test r pulse test with TMR = RSN 0.7 1.0 1.3 A VOLTAGE TRANSLATOR (SEN, SENP) V TMR = 2.5 V, Measure with serv lp that includes the errr (SENP - SEN) regulatin vltage 1.456 1.492 1.526 V amplifier V 4

www.ti.cm DC/DC CONTROLLER SECTION (cntinued) RTN = V SS fr this sectin nly. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V SENP-SEN = 1.5 V, TMR = RSN, I FB = 0 µa and 10 µa, Translatr utput resistance 11.25 15 18.75 kω R FB = V FB / I FB SEN sinking current V SENP-SEN = 1.50 V, V TMR = RSN 1 µa SENP sinking current V SENP-SEN = 1.50 V, V TMR = RSN 17 22.5 28 µa PE SECTION DETECTION (DET) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Offset current DET pen, V DD = V RTN = 1.9 V, Measure I VDD I RTN I SENP 0.45 4 µa Sleep current DET pen, V DD = V RTN = 10.1 V, Measure I VDD I RTN I SENP 5.6 12 µa DET leakage current V DET = V DD = 57 V, Measure I DET 0.3 5 µa RTN = V DD, Measure I VDD I RTN V DD = 1.4 V 51.5 55 58.7 Detectin current µa I DET I SENP VDD = 10.1 V 395 411 417 CLASSIFICATION (CLASS) RTN = V DD, Measure I VDD I RTN I DET I SENP R CLASS = 4420 Ω, 13 V DD 21 V 2.2 2.5 2.8 R CLASS = 953 Ω, 13 V DD 21 V 10.3 10.6 11.3 I CLASS Classificatin current ma R CLASS = 549 Ω, 13 V DD 21 V 17.7 18.3 19.5 R CLASS = 357 Ω, 13 V DD 21 V 27.1 28.0 29.5 R CLASS = 255 Ω, 13 V DD 21 V 38.0 39.4 41.2 V CL_ON Regulatr turns n, V DD rising 10.2 11.3 13.0 Classificatin lwer threshld V CL_H Hysteresis 1 1.75 3 V CU_OFF Regulatr turns ff, V DD rising 21 21.9 23 Classificatin upper threshld V CU_H Hysteresis 0.5 0.83 1 PASS DEVICE (RTN) On resistance I RTN = 300 ma 0.60 1 Ω Current limit V RTN = 1 V 405 450 515 ma I INR Inrush limit V RTN = 1.6 V 100 140 180 ma CONTROL UVLO Inrush current state terminatin I RTN falling frm I INR, I RTN /I INR 0.85 1.00 V UVLO_R V DD rising, mnitr I RTN 38.4 39.3 40.4 V UVLO_F Standard UVLO threshld V DD falling, mnitr I RTN 29.6 30.5 31.5 V Hysteresis 8.3 8.8 9.1 V UVLO_R V DD rising, mnitr I RTN 34.1 35.1 36.0 V UVLO_F Legacy UVLO threshld V DD falling, mnitr I RTN 29.7 30.5 31.4 V Hysteresis 4.3 4.5 4.8 V V 5

www.ti.cm ELECTRICAL CHARACTERISTICS COMBINED PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS CURRENT I VDDQ Quiescent current 1 1.3 ma Operatinal current COMP = FB 1.1 1.4 COMP = FB, R FREQ = 30 kω 1.3 1.75 ma Off state current RTN = COM = RSN = V DD, V DD = 33 V 0.18 0.5 ma THERMAL SHUTDOWN Shutdwn temperature Temperature rising 140 C Hysteresis 17 C 6

www.ti.cm DEVICE INFORMATION TMR FB COMP SEN NC SENP V DD DET CLASS V SS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 FREQ BL V BIAS MODE AUX GATE COM RSN RSP RTN Figure 2. Pinut NAME TERMINAL NO. I/O TMR 1 O TERMINAL FUNCTIONS DESCRIPTION Multifunctin pin, serves as a cnverter sft start and a hiccup timer. A capacitr t RTN determines the sftstart and hiccup timing. FB 2 I Cnverter errr amplifier inverting input. Tie t RTN when nt used. COMP 3 I/O SEN 4 I Cnverter errr amplifier utput and PWM blck input. COMP is used fr lp cmpensatin r PWM cntrl with an external errr amplifier and pt-islatr. Vltage-level translatr's sense input and enable; cnnect t RTN t disable. SEN is regulated t 1.5 V belw SENP by the cntrl lp when the translatr is used. Typically used in a lw-side switch buck cnverter. NC 5 - N cnnect. There are n internal cnnectins. SENP 6 I V DD 7 PWR Psitive supply input. Vltage-level translatr's psitive reference vltage (sense psitive) used in cnjunctin with SEN. Tie t the regulated vltage psitive rail when the translatr is used, and V DD therwise. DET 8 O PE detectin pin; a 24.9 kω resistr t V DD establishes a valid signature. It is pulled t V SS during detectin. CLASS 9 O Classificatin pin fr PE. A resistr t V SS sets the PE device class. This pin is driven t 10 V during classificatin. V SS 10 PWR Negative supply input frm the PE feed (after required ORing bridges). RTN 11 I The switched PE negative utput. RTN is the cnverter s negative input rail. COM and RSN shuld be tied t RTN. RSP 12 I Cnnect t the cnverter switching MOSFET current-sense resistr (current Sense Resistr Psitive end). RSN 13 I Cnverter switching MOSFET current-sense reference (current Sense Resistr Negative end) and quiet analg return (grund). Cnnect t RTN. COM 14 I Cnverter MOSFET gate driver circuit return. Cnnect t RTN. GATE 15 O Cnverter switching MOSFET gate drive. AUX 16 I/O Cnverter gate driver supply; utputs 10 V and can accept inputs up t 16 V. Cnnect a bypass capacitr t COM. MODE 17 I Cnnect t V BIAS t disable the errr amplifier, therwise t RTN. V BIAS 18 O BL 19 I Cnverter internal 5 V bias supply utput, als used t bias external ptcupler. A bypass capacitr t RTN is required. Cnverter current sense blanking selectr. Leave flating fr minimum blanking, tie BL t RTN fr a shrt perid, and t V BIAS fr a lng perid. FREQ 20 I Cnnect a resistr t RTN t prgram the switching frequency. Internally cnnected t V SS ; used t heatsink the part t the circuit bard traces. Must be cnnected t the PwerPAD - PWR VSS pin. 7

0.27 V FREQ BLOCK DIAGRAM www.ti.cm SENP SEN Translatr 15 k 15 k OSC. CLK V DD CE REG. REG. ENABLE V BIAS AUX FB ERROR AMP 1.5 V HI LO V BIAS 80 k PWM COMP. RUN CLK CE STATE LATCH D R Q UVLO & OVLO COM EN ABLE GATE DRIVER GATE COM COMP MODE TMR 50 A 0.5 V SOFT START and FAULT CTL 20 k RUN CURRENT LIMIT COMP. 0.5 V X4 CNTR. CLK CLK FAULT COMP. DELAY 0.75 V BL RSP RSN 5 A CE V DD 1.31 V and 9.3 V Detect DET 21.9 V and 21.28 V Class High Thermal shutdwn OTSD 0 = Ht RTN 10 V Regulatr SMPS CLASS 20.5 V and 18 V UVLO SMPS OTSD UVLO OTSD CE 39.3 V and 30.5 V 1.5 V and 12 V RTN RTN UVLO RTN 375 s 36 mv 11.2 mv 1 0 Current limit RTN OTSD 0.08 VSS 8

www.ti.cm DETAILED DESCRIPTION AUX This pin is the junctin between the internal 10 V cnverter-bias regulatr, the gate driver supply, and the 5-V regulatr that pwers the rest f the cnverter cntrl circuit. Vltage may be applied t this pin during nrmal cnverter peratin t imprve efficiency and reduce the temperature rise. A UVLO f abut 8 V mnitrs V AUX-COM t prevent peratin with inadequate r weak bias. A cnverter vervltage lckut prtects the IC when a bias winding is used and V AUX rises abve 17.5 V. A lw ESR bypass capacitr f at least 0.8 µf must be cnnected frm AUX t COM. BL This pin selects the desired blanking peratin. The blanking functin prevents the sensed MOSFET current frm tripping the PWM and current limit cmparatrs fr a predetermined perid after the GATE switches high. This prevents the cmparatrs frm being falsely triggered by the gate drive current and recvery currents in the external pwer rectifiers. The recvery currents are strngly influenced by the tplgy, device selectin, and device parasitics. The current limit cmparatr, lgic, and gate driver accunt fr the minimum delay which is btained with the BL pin pen. There are tw preset delay chices, as shwn belw. Shrter perids may be btained by leaving BL pen and using an RC filter. BL CONNECTION Open RSN V BIAS Table 1. BL Cnnectins BLANKING OPERATION Nne (Minimum current-sense lp delay) Minimum plus 70 ns Minimum plus 105 ns CLASS Classificatin is a PE functin implemented by means f an external resistr, R CLASS, cnnected between CLASS and V SS. Current is drawn frm V DD thrugh R CLASS fr input vltages between 13 V and 21 V. Classificatin allws the PD t indicate the required average pwer requirements t the PSE as shwn in Table 2. CLASS Table 2. Classificatin 802.3af CLASS PD POWER R CLASS CURRENT (W) (Ω) LIMITS (ma) 0 0.44 12.95 4420 ±1% 0 4 Default class 1 0.44 3.84 953 ±1% 9 12 2 3.84 6.49 549 ±1% 17 20 3 6.49 12.95 357 ±1% 26 30 NOTE 4 Reserved 255 ±1% 36 44 Treated like class 0 Apprximately 10 V is applied t the CLASS resistr fr up t 75 ms. The resistr s wattage rating need nly be based n this transient cnditin. The CLASS pin must nt be shrted t grund. The recmmended CLASS 0 resistr serves as a bleeder fr capacitance cnnected arund the after pwer is remved. COM Switching regulatr gate driver return. This signal is internally separated frm RTN and RSN t minimize nise cupling, but it shuld always be cnnected t RSN and RTN n the circuit bard. COMP The is a traditinal current-mde cntrller. The COMP pin represents the junctin between the vltage cntrl lp s errr amplifier utput and the current cntrl lp s reference input. The name refers t the traditinal cnnectin f lp cmpensatin cmpnents, which are cnnected between COMP and FB. MODE alters the functin f COMP. If MODE is tied t RTN, the internal errr amplifier is enabled. If MODE is tied t V BIAS, the internal amplifier discnnects frm COMP, allwing an ptcupler t be fed directly int the PWM cmparatr circuit. The COMP pin shuld nly be driven between RTN and V BIAS when in this mde. Tie FB t RTN when the amplifier is disabled. The current-mde cntrl range includes COMP vltages between 1.35 V and just under 4 V. Cnverter switching is inhibited fr COMP vltages belw 1.35 V. COMP vltages higher than f 4.1 V cause the TMR circuit t begin hiccup peratin. COMP is frced lw during a hiccup-cycle ff perid when the internal errr amplifier is used. 9

www.ti.cm The COMP utput shuld nt be ver-driven when the internal errr amplifier is active. The amplifier can surce and sink significant currents which will greatly increase pwer dissipatin. TMR may be pulled lw t turn the cnverter ff when the internal errr amplifier is used. The errr amplifier will surce current when COMP is pulled belw its saturated lw vltage due t the nature f the class AB amplifier stage. DET Cnnect a 24.9 kω, ±1% resistr (R DET ), between DET and V DD. R DET is cnnected acrss the input line when V DD lies between 1.4 V and 10.1 V, and is discnnected when the line vltage exceeds 12 V t cnserve pwer. R DET may be adjusted t cmpensate fr input dide characteristics. FB This is the internal dc/dc cnverter errr amplifier s inverting input. FB is used fr utput vltage feedback and lp cmpensatin. FB equals 1.5 V when the feedback lp is in regulatin. FB shuld be tied t RTN when the errr amplifier is disabled using MODE. The internal level translatr drives this pin with a surce impedance f abut 15 kω when it is enabled using SEN. FREQ A resistr cnnected frm FREQ t RTN prgrams the cnverter switching frequency. This feature allws an existing design t be easily upgraded t use the withut requiring redesign f the magnetics and filtering. While the scillatr is characterized between 100 khz and 500 khz, it perates prperly dwn t a frequency f a few kilhertz. R (k ) 15000 FREQ Switching_Frequency (khz) (1) Althugh this expressin is reasnably accurate, the frequency will be slightly lwer than predicted at higher frequencies. FREQ must nt be shrted t grund r have vltage applied. GATE DC/DC cnverter s switching MOSFET driver utput. This pin has an internal pull-dwn t keep the external switching MOSFET ff when the cnverter is inactive. MODE This pin disables the cnverter errr amplifier, allwing an ptcupler t drive the PWM cmparatr directly frm COMP. Cnnecting MODE t RTN enables the errr amplifier, and t V BIAS disables it. MODE shuld nt be left flating. RSN This pin is the current-mde cntrller s quiet "grund" reference fr current sensing and ther lw-level signals. RTN, RSN, and COM shuld be tied tgether. RSP This pin is the current-mde cntrller s current-sense input. Current-mde cntrl mnitrs the switching MOSFET peak current, which is sensed as vltage between RSP and RSN, t set the PWM duty cycle. The peak current limit is established by limiting the maximum sense vltage t abut 0.5 V. MOSFET current may rise t high levels during the blanking perid when there is a shrt in the pwer circuit. If the RSP peak vltage exceeds 0.75 V n fur successive switching cycles, the cnverter is turned ff and a hiccup cycle is started. If the blanking is sufficient t eliminate the need fr an input RC filter, this pin may be directly cnnected t the sense resistr. RTN An internal MOSFET cnnects this pin t V SS. This MOSFET is cntrlled by the PE sectin UVLO, inrush limit, current limit, thermal limit, and fault vltage limiting. Mst applicatins cnnect RSN, COM, and RTN tgether thrugh a grund plane. SEN SEN is the negative input fr the level translatr. It can be used in buck cnverters as demnstrated in Figure 40. The translatr is enabled by cnnecting SEN abve 1 V with respect t V SS. The level translatr applies V SENP-SEN t the FB pin thrugh an internal 15 kω resistr. This feature simplifies feedback vltage sensing abve RTN. Cnnect SEN t RSN if the level translatr is nt used. SENP SENP is the psitive input fr the level translatr. It is used in cnjunctin with SEN as demnstrated in Figure 40. The presence f this pin allws a filter inductr t be placed in the psitive pwer rail between V DD and the utput. Cnnect SENP t V DD when the level translatr is disabled. The vltage n SENP shuld always be greater than the vltage n SEN. TMR Cnnect a capacitr frm TMR t RTN t prgram the sftstart and hiccup timer functins. Pull this pin t RTN t disable the cnverter. 10

www.ti.cm TMR cntrls sftstart, verlad time-ut, and autmatic restart n verlad, which is referred t as a hiccup functin. V BIAS This 5-V bias supply pwers the bulk f the cnverter functins. V BIAS can be used t pwer the feedback ptcupler in islated applicatins. External lading shuld be minimized t avid excessive pwer dissipatin. V BIAS has a UVLO functin that inhibits cnverter peratin at utputs f less than 4.6 V. V BIAS shuld be bypassed with a capacitr between 0.08 µf and 1.5 µf. D nt apply external bias t this pin. V DD This is the psitive pwer pin t the IC. V SS Cmmn grund fr the internal PE circuits. This pin is cnnected t the lw side f the rectified PE vltage. An internal pwer MOSFET cnnects RTN t V SS under cntrl f the PE sectin. The PwerPAD n the bttm f the package is internally cnnected t V SS. The PwerPAD is used t remve heat frm the die thrugh the PCB. 11

TYPICAL CHARACTERISTICS www.ti.cm 5.3 V BIAS V BIAS CURRENT LIMIT AUX VOLTAGE vs vs vs LOAD CURRENT JUNCTION TEMPERATURE LOAD CURRENT 19 10.6 V BIAS - V 5.25 5.2 5.15 5.1 5.05 5 T J = 125 C T J = 25 C T J = -40 C Current - ma 18 17 16 15 14 13 12 11 Vltage - V 10.4 10.2 10 9.8 9.6 T J = 125 C T J = 25 C T J = -40 C 4.95 0 1 2 3 4 5 IL - Lad Current - ma 10-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C 9.4 0 1 2 3 4 5 6 7 8 9 10 IL - Lad Current - ma Figure 3. Figure 4. Figure 5. Current - ma 29 27 25 23 21 19 17 AUX CURRENT LIMIT ERROR AMPLIFIER SOURCE ERROR AMPLIFIER SINK CURRENT vs CURRENT vs JUNCTION TEMPERATURE vs V COMP V COMP Current - ma 8 7 6 5 4 3 2 1 T J = -40 C T J = 25 C T J = 125 C Current - ma 20 15 10 5 0-5 T J = 125 C T J = 25 C T J = -40 C 15 0-10 -40-20 0 20 40 60 80 100 120 140 0 1 2 3 4 5 0 1 2 3 4 5 TJ - Junctin Temperature - C VCOMP - V VCOMP - V Figure 6. Figure 7. Figure 8. Gain - db, Phase Margin - 100 80 60 40 20 0 ERROR AMPLIFIER GAIN AND FB REGULATION VOLTAGE TMR SOURCE CURRENT PHASE vs vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE FREQUENCY T J = -40 C Gain T J = 25 C Phase T J = 25 C T J = 125 C T J = 125 C -20 1 10 100 1000 10000 f- Frequency - khz T J = -40 C Vltage - V 1.505 1.504 1.503 1.502 1.501 1.5 1.499 1.498 1.497-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Current - A 60 58 56 54 52 50 48 46 44 42 40-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Figure 9. Figure 10. Figure 11. 12

www.ti.cm TYPICAL CHARACTERISTICS (cntinued) Surce/Sink Rati 10.08 10.06 10.04 10.02 10.00 9.98 9.96 9.94 9.92 TMR SOURCE/SINK CURRENT CONVERTER CURRENT LIMIT RSP SOURCE CURRENT RATIO THRESHOLD (V RSP ) vs vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE 9.90-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Current Limit Threshld - V 504 503 502 501 500 499 498 497-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Current - A 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Figure 12. Figure 13. Figure 14. Resistance - 20 18 16 14 12 10 8 6 4 2 GATE OUTPUT RESISTANCE GATE PEAK DRIVE CURRENT SENP SINKING CURRENT vs vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE GATE = High GATE = Lw 0-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Current - A 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 Sink Surce 0.4-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Current - A 29 27 25 23 21 19 17-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Figure 15. Figure 16. Figure 17. 150 SEN SINKING CURRENT (SENP - SEN) REGULATION TRANSLATOR OUTPUT vs VOLTAGE RESISTANCE JUNCTION TEMPERATURE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 1.490 19 140 130 1.489 1.488 18 17 Current - na 120 110 100 90 80 70 60-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Vltage - V 1.487 1.486 1.485 1.484 1.483 1.482 1.481-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Resistance - k 16 15 14 13 12 11 Small Signal Series Resistance 10-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Figure 18. Figure 19. Figure 20. 13

TYPICAL CHARACTERISTICS (cntinued) www.ti.cm Current - A 6 5 4 3 2 1 (V DD RTN SENP) DETECTION PE CURRENT LIMIT MAXIMUM DUTY CYCLE CURRENT vs vs vs JUNCTION TEMPERATURE OSCILLATOR FREQUENCY SUPPLY VOLTAGE During PE Detectin T J = 125 C T J = 25 C T J = -40 C 0 0 2 4 6 8 10 12 VDD - Supply Vltage - V I - ma RTN 452 450 448 446 444 442 440 438 436 434 432-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Max Duty Cycle - % 49.50 49.25 49.00 48.75 48.50 T J = 125 C T J = 25 C T J = -40 C 0 100 200 300 400 500 600 Oscillatr Frequency - khz Figure 21. Figure 22. Figure 23. Respnse Time - ns 75 70 65 60 55 CONVERTER CURRENT LIMIT BLANKING TIME OSCILLATOR FREQUENCY RESPONSE TIME vs vs vs JUNCTION TEMPERATURE 15000/R FREQ JUNCTION TEMPERATURE 50-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Blanking Time - ns 130 120 110 100 90 80 70 60 50 BL = V BIAS BL = RTN 40-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Oscillatr Frequency - khz 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 15000 / R - khz FREQ Figure 24. Figure 25. Figure 26. PD Detectin Resistance - k 30.0 27.5 25.0 22.5 20.0 PD DETECTION RESISTANCE OPERATING CURRENT ( I VDD ) vs vs VOLTAGE, V PI JUNCTION TEMPERATURE Includes 24.9 k and HD01 Bridge 802.3af Limits 802.3af Limits 1 R(V PI) = ( I(V PI) - I(V PI) -1)) 17.5 1 2 3 4 5 6 7 8 9 10 11 Vltage, VPI - V Current - ma 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 Operating R (FREQ) = 30 k Operating R (FREQ) = 150 k Quiescent 0.6-40 -20 0 20 40 60 80 100 120 140 TJ - Junctin Temperature - C Figure 27. Figure 28. 14

www.ti.cm APPLICATION INFORMATION PE OVERVIEW The fllwing text is intended as an aid in understanding the peratin f the but nt as a substitute fr the actual IEEE 802.3af standard. Standards change and shuld always be referenced when making design decisins. The IEEE 802.3af specificatin defines a methd f safely pwering a PD ver a cable, and then remving pwer if a PD is discnnected. The prcess prceeds thrugh the three peratinal states f detectin, classificatin, and peratin. The PSE leaves the cable unpwered while it peridically lks t see if smething has been plugged in; this is referred t as detectin. The lw pwer levels used during detectin are unlikely t damage devices nt designed fr PE. If a valid PD signature is present, then the PSE may ptinally inquire hw much pwer the PD requires; this is referred t as classificatin. The PD may return a default full-pwer signature, r ne f fur ther chices. The PSE may then pwer the PD if it has adequate capacity. Once started, the PD must present the maintain pwer signature (MPS) t assure the PSE that it is still there. The PSE mnitrs its utput fr a valid MPS, and turns the prt ff if it lses the MPS. Lss f the MPS returns the PSE t the initial state f detectin. Figure 29 shws the peratinal states as a functin f PD input vltage. The PD input is typically an RJ-45 eight-lead cnnectr which is referred t as the pwer interface (PI). PD input requirements differ frm PSE utput requirements t accunt fr vltage drps in the cable and perating margin. The specificatin uses a cable resistance f 20 Ω t derive the vltage limits at the PD frm the PSE utput requirements. Althugh the standard specifies an utput pwer f 15.4 W at the PSE utput, nly 12.95 W is available at the input f the PD due t the wrst-case pwer lss in the cable. The PSE can apply vltage either between the RX and TX pairs (pins 1 2 and 3 6), r between the tw spare pairs (4 5 and 7 8). The applied vltage can be f either plarity and can nly be applied t ne set f pairs at a time. The PD uses input dide bridges t accept pwer frm any f the pssible PSE cnfiguratins. The vltage drps assciated with the input bridges create a difference between the IEEE 802.3af limits at the PI and the specificatins. The PSE is required t current limit at an average f between 350 ma and 400 ma during nrmal peratin, and it must discnnect the PD if it draws this current fr mre than 75 ms. Class 0 and 3 PDs may draw up t 400 ma peak currents. The PSE may set lwer utput current limits based n the PD s declared pwer requirements, as discussed belw. Detectin Lwer Limit Detectin Upper Limit Classificatin Lwer Limit Classificatin Upper Limit Must Turn Off by - Vltage Falling Lwer Limit - Prper Operatin Must Turn On by- Vltage Rising Maximum Input Vltage Detect Classify Shutdwn Nrmal Operatin 0 2.7 10.1 14.5 20.5 30 PI Vltage (V) 36 42 57 Figure 29. IEEE 802.3 PD Limits 15

APPLICATION INFORMATION (cntinued) PE THRESHOLDS www.ti.cm The has a number f internal cmparatrs with hysteresis fr stable switching between the varius states as shwn in Figure 29. Figure 30 relates the parameters in the Electrical Characteristics sectin t the PE states. The mde labeled idle between classificatin and peratin implies that the DET, CLASS, and RTN pins are all high impedance. Classificatin Idle PD Pwered Detectin V CL_H V CU_H VUVLO_F V DD V UVLO_R 1.4V V CU_OFF V CL_ON Figure 30. Threshld Vltages DETECTION This feature f IEEE 802.3af reduces the risk f damaging Ethernet devices nt intended fr applicatin f 48 V. When a vltage in the range f 2.7 V t 10.1 V is applied t the PI, an incremental resistance f 25 kω signals the PSE that the PD is bth capable f, and ready t, accept pwer. The incremental resistance is measured by applying at least tw different vltages t the PI and measuring the current it draws. These tw test vltages must be within the specified range and be at least 1 V apart. The incremental resistance equals the difference between the vltages divided by the difference between the currents. The allwed range f resistance is 23.75 kω t 26.25 kω. The is in detectin mde whenever the supply vltage is belw the lwer classificatin threshld. The draws a minimum f bias pwer in this cnditin, while RTN is high impedance and almst all the internal circuits are disabled. The DET pin is pulled t grund during detectin, s a 24.9 kω, 1% resistr frm V DD t DET presents the crrect signature. R DET may be a small, lw-pwer resistr since it nly sees a stress f abut 5 mw. When the input vltage rises abve the 11.3 V upper detectin cmparatr threshld, the DET pin ges t an pen-drain cnditin t cnserve pwer. The input dide bridge s incremental resistance may be hundreds f Ohms at the very lw currents seen at 2.7 V n the PI. The bridge s resistance is in series with R DET and increases the ttal resistance seen by the PSE. The nnlinearity in the detectin signature f Figure 29 is caused by the dide bridge. This varies with the type f dide selected by the designer, and it is nt usually specified n the dide data sheet. The value f R DET may be adjusted dwnwards t accmmdate a particular dide type. CLASSIFICATION Once the PSE has detected a PD, it may ptinally classify the PD. Classificatin allws a PSE t determine a PD s pwer requirements rather than assuming every PD requires 15.4 W, which allws the PSE t pwer the maximum number f PDs frm its 48-V pwer supply. This step is ptinal because sme PSEs can affrd t allt the full pwer t every pwered prt. The classificatin prcess applies a vltage between 14.5 V and 20.5 V t the input f the PD, which in turn draws a fixed current set by R CLASS. The PSE measures the PD current t determine which f the five available classes (see Table 2) that the PD falls int. The ttal current drawn frm the PSE during classificatin is the sum f bias currents and current thrugh R CLASS. The discnnects R CLASS at vltages abve the classificatin range t avid excessive pwer dissipatin (see Figure 29 and Figure 30). 16

www.ti.cm APPLICATION INFORMATION (cntinued) NORMAL OPERATION AND PE UNDERVOLTAGE LOCKOUT (UVLO) PD STATE MACHINE AND CONVERTER OPERATION The value f R CLASS shuld be chsen frm the values listed in Table 2 based n the average pwer requirements f the PD. The pwer rating f this resistr shuld be chsen s that it is nt verstressed fr the required 75 ms classificatin perid, during which 10 V is applied. The PD culd be in classificatin fr extended perids during bench test cnditins, r if an auxiliary pwer surce with vltage within the classificatin range is cnnected t the PD frnt end. Thermal prtectin may activate and turn classificatin ff if it cntinues fr mre than 75 ms, but the design must nt rely n this functin t prtect the resistr. The incrprates an undervltage lckut (UVLO) circuit that mnitrs PE input vltage t determine when t apply pwer t the cnverter, allwing the PD t pwer up and run. The IEEE 802.3af specificatin dictates a maximum PD turn-n vltage f 42 V and a minimum turn-ff vltage f 30 V (see Figure 30). The IEEE 802.3af standard assumes an 8 V drp in the cabling based n a 20 Ω feed resistance and a 400 ma maximum inrush limit. Because the minimum PSE utput vltage is 44 V, the PD must cntinue t perate prperly with input vltages as lw as 36 V. The allws an input dide drp f 1.5 V and sets its nminal turn-n at 39.3 V and its turn-ff at 30.5 V, while the turns n at 35 V with the same turn-ff. The UVLO limits are designed t supprt legacy systems whse minimum utput vltage is less than 44 V. These systems required a lwer turn-n vltage and smaller hysteresis. Althugh the wrks with cmpliant PSEs, it culd ptentially exhibit startup instabilities if the PSE utput vltage rises slwly. The is recmmended fr applicatins with cmpliant PSEs. The MPS is an electrical signature presented by the PD t assure the PSE that it is still present. A valid MPS cnsists f a minimum dc current f 10 ma and an ac impedance lwer than a series 26.25 kω and 0.05 µf lad. The ac impedance is usually vershadwed by the minimum capacitance requirement f 5 µf. The incrprates a state machine that cntrls the inrush and peratinal current limit states. When V DD is belw the lwer UVLO limit, the pass MOSFET is ff. Cnsequently, the RTN pin is high impedance, and at V DD nce the utput capacitr is discharged by the cnverter. When V DD rises abve the UVLO turn-n threshld with RTN high, the enables the internal pwer MOSFET with the current limit set t 140 ma. The cnverter is disabled while the utput capacitr charges and V RTN falls frm V DD t nearly V SS. Once the inrush current falls abut 10% belw the prgrammed limit, the current limit switches t the internal 450 ma peratinal level after a 375 µs delay. The cnverter sectin is enabled nce the current limit is switched and the cnverter begins a sftstart cycle. If the input vltage drps belw the lwer UVLO, the PE MOSFET turns ff, but the cnverter is allwed t perate t a (V VDD - V SS ) f abut 18 V. The internal pass MOSFET is prtected against utput faults with a current limit and a frm f fldback when it is perating in the full current limit state. The PSE utput cannt be relied n t prtect the PD MOSFET against transient cnditins, s the PD implements its wn utput prtectin. High stress cnditins include cnverter utput shrts, shrts frm V DD t RTN, r transients n the input line. An verlad n the pass MOSFET engages the current limit, with (V RTN - V SS ) rising as a result. If V RTN rises abve 12 V, the current limit state machine resets t the 140 ma inrush current limit, and turns ff the cnverter. The thermal shutdwn activates t prtect the device if the pwer dissipatin frm current limit verheats the as described in the thermal prtectin sectin belw. The RTN cmparatr is capable f detecting even shrt excursins f RTN ver 12 V that can be caused during verlads and input transients. If the fault that caused the verlad disappears, the ges thrugh a nrmal startup cycle as discussed abve. This frm f prtectin limits the peak dissipatin in the MOSFET, prevents lckup f the cnverter in current limit, prtects the lad frm a harmful vltage drp, and allws an rderly recvery frm a knwn state if the prblem disappears. The allws startup and peratin frm a 24 V t 48 V adapter when it is cnnected frm V DD t RTN withut PE pwer available. Cnverter peratin is enabled if The PE sectin is nt in inrush, and V DD - V SS has exceeded 20.5 V with RTN less than 1.5 V, and V DD - V SS is greater than 18 V. The threshlds are defined in terms f V DD - V SS even thugh the cnverter really perates frm V DD t RTN. The internal PE pass MOSFET has a reverse dide which clamps V SS t ne dide drp abve RTN when the device is pwered frm the utput side. 17

www.ti.cm APPLICATION INFORMATION (cntinued) PE STARTUP EXAMPLE Figure 31 demnstrates detectin, classificatin, and startup. The PSE cntrls the vltage n the PI, while the PD cntrls the current. The wavefrms presented are the PI vltage, PI current, and dc/dc cnverter utput vltage. Testing with different PSEs may result in wavefrms that are nt exactly the same because the IEEE 802.3af standard allws fr different implementatins. The first event is detectin. Tw vltage levels f abut 4 V and 8 V are seen, but the detectin current levels are nt seen because f the current scale. The secnd event is classificatin. The PD draws abut 28 ma while the PI vltage is abut 17 V, indicating it is a class 3 device. The third event is startup. The PI vltage ramps t abut 46 V and the PD draws an inrush current between 120 ma and 140 ma as the dwnstream bulk capacitr is charged. The PI current drps nce the bulk capacitr is charged, allwing the inrush state t terminate and the cnverter t enable. The final event is cnverter startup int a fixed 1-Ω lad. The cnverter utput vltage ramps t 3.3 V with a crrespnding PI current draw. The PI current increases t a steady-state value f 260 ma with nly a small versht as the utput capacitr is charged. The PD is pwered, and the applicatins circuits are peratinal at the end f startup. 3.3V Output D etectin C lass C nverter Starts PE Input Vltage I nrush PE Input Current Figure 31. Typical Startup Wavefrms THERMAL PROTECTION The enters a lw-pwer mde if the die temperature exceeds 140 C. The pass MOSFET, dc/dc cnverter, AUX regulatr, and CLASS regulatr are turned ff when this ccurs. Surces f internal dissipatin include bias currents, the pass MOSFET, and the AUX, V BIAS, and CLASS regulatrs. Lading n AUX and V BIAS is a dminant cntributr when the AUX rail is nt externally biased. The autmatically restarts when the die temperature has fallen apprximately 17 C with the pass MOSFET set in the inrush state, the cnverter disabled, and the TMR capacitr discharged. The is built using a PwerPAD package t prvide a lw thermal resistance frm the junctin t the circuit bard. The PwerPAD shuld be sldered t a large cpper area n the circuit bard t prvide gd thermal perfrmance. Other surces f lcal PCB heating shuld be cnsidered during the thermal design. Typical calculatins assume that the is the nly heat surce cntributing t the PCB temperature rise. CONVERTER CONTROLLER OVERVIEW The dc/dc cntrller implements a typical current-mde cntrl tplgy reminiscent f the UC3844, but with a number f enhancements. 18

www.ti.cm APPLICATION INFORMATION (cntinued) A class AB inverting errr amplifier, with a 1.5 V fixed reference, cnnects between input FB and utput COMP. The errr amplifier has a 1.5 MHz gain-bandwidth prduct and can surce r sink several milliamps. This amplifier can be disabled t allw an ptcupler feedback circuit t drive the PWM sectin COMP is als the input t the current-mde PWM sectin. A 1/5 divider scales the COMP input t the current cmparatrs. Offsets built int the cmparatr assure that the duty cycle can be driven t 0%. The current limit cmparatr threshld f 0.5 V n the RSP pin prvides a regulated current limit. The fault cmparatr detects a runaway cnditin when the peak vltage n RSP is greater than 0.75 V. This can ccur with a shrted transfrmer winding, a shrt n the switching MOSFET drain, r a shrted buck cnverter inductr. The shuts dwn immediately after fur cnsecutive fault cmparatr trips and enters a TMR-based hiccup cycle. The duty cycle is limited t 50% based n typical circuits used in PE, prviding a number f benefits. First, it eliminates the cmplexity f a stabilizing current ramp. Secnd, it gives an assured reset perid fr the magnetics. Third, many frward cnverters with a 1:1 reset winding require a 50% r less duty cycle. Mst applicatins that use a transfrmer r buck-mde cnverter prefer this lwer duty cycle. User-prgrammable current sense blanking eliminates the need fr an RC filter. A 70 ns blanking perid is prvided t serve higher-frequency switching circuits with lw utput-rectifier recvery perids. A 115 ns blanking perid is prvided t serve medium-t-slw frequency circuits that have significant gate drive and recvery requirements. The minimum blanking ptin is prvided t allw shrt perid RC filters t be used. The TMR pin prvides a clsed-lp sftstart when the errr amplifier is used. An pen-lp sftstart is prvided if the internal errr amplifier is disabled. TMR als implements a synthesized hiccup, r pause and restart, t limit average pwer dissipatin when there is a fault in the cnverter. Cascading failures are avided during a fault because the cnverter perates nly abut 9% f the time, allwing the pwer cmpnents t cl. A hiccup can be triggered when the COMP pin is railed high fr a prgrammed perid, which ccurs when there is an verlad, r the input vltage is t lw. The internal bias regulatrs eliminate external btstrap resistrs and startup regulatrs. The internal regulatrs allw the cnverter t start and run as sn as inrush cmpletes. This avids the pitfalls assciated with the btstrap-startup tplgy including failure t start and excessive startup delay. Sme PD designs use a 24 V wall adapter t perate when PE is nt available. The cnverter cntrl allws startup with at least 20.5 V applied V DD - RTN, and peratin dwn t abut 18 V. ERROR AMPLIFIER CONNECTIONS The accmmdates many types f cnverters and feedback methds. A level translatr supprts a simple lw-side switch buck cnverter, a class-ab vltage errr amplifier supprts nn-islated cnverters, and an errr amplifier disable supprts ptcupler feedback. Sme PD designers prefer t create multi-utput pwer supplies using a flyback r frward tplgy, but d nt require metallic islatin between the PE frnt end and the applicatin circuits. Figure 32 shws a cnfiguratin that enables the internal errr amplifier and disables the level shifter. A standard utput vltage divider and cmpensatin scheme utilizes the FB and COMP pins. The cntrl lp design shuld accunt fr a 0.2 V/V attenuatin factr frm the errr amplifier t the PWM cmparatr. The TMR pin ramps the reference vltage t the errr amplifier giving a clsed-lp sftstart. 19

APPLICATION INFORMATION (cntinued) www.ti.cm T RTN Cnverter Output Stage Vltage Output T V DD Part f FB 1.5V Errr Amplifier COMP SENP Translatr Sft start SEN 80k 1.5V 15k T PWM 15k Cmparatr 20k RTN MODE Figure 32. Nnislated Cnverter Cnfiguratin Islated PD cnverters that use an ptcupler, such as TL431-based circuits, shuld use the cnfiguratin f Figure 33. The MODE cnnectin disables the internal errr amplifier, rendering its utput high impedance. A primary-side PWM sftstart is internally implemented when the errr amplifier is disabled. The same gain f 0.2 V/V appears befre the PWM cmparatr. The COMP pin is still mnitred t implement hiccup in this cnfiguratin. T V DD SENP SEN Translatr Part f 15k 15k Sft start 1.5V Errr Amplifier Sftstart Frm Blanker 80k 20k RSN PWM Cmparatr Cnverter Output Stage Lw Vltage Output RTN FB MODE COMP V BIAS RTN RTN TLV431 Figure 33. Islated Cnverter Cnfiguratin The buck cnverter cnfiguratin is shwn in Figure 34. The lp regulates the vltage acrss R LO t 1.5 V. The translatr tplgy prvides a gain f 1 V/V frm V SENP-SEN t the 15 kω internal series resistr. The errr amplifier gain expressin is (Z COMP-FB / 15 kω). The utput divider and translatr attenuate bth the ac and dc cmpnents, unlike the cnfiguratin f Figure 32 where the ac signal is nt divided because the virtual grund at the amplifier input cancels the effect f R LO. Additin f C BYP acrss R HI applies the full ac signal t the errr amplifier. The R HI C BYP crner frequency shuld be at least an ctave lwer than the R Z C Z zer frequency. This methd assures C BYP has little effect n standard lp design practices. 20

www.ti.cm APPLICATION INFORMATION (cntinued) Cnverter Pwer Stage T V DD 1.5V R LO Lw Vltage Output C BYP R HI FB R Z C Z COMP T GATE SENP SEN RSP Part f Translatr 15k Sft start 15k 1.5V Errr Amplifier 80k 20k T PWM Cmparatr RTN, COM, RSN MODE Figure 34. Buck Cnverter Cnfiguratin ADDITIONAL USES OF SENP AND SEN The level translatr inputs, SENP and SEN, are nt limited t the buck applicatin shwn in Figure 34. They may be used at vltages abve V DD, but within their recmmended vltage range with respect t V SS. SENP draws abut 22.5 µa f current, while the SEN pin draws less than 1 µa. The SENP current can cause a small ffset in the utput vltage if cnnected t the center tap f an utput vltage divider. If necessary, the ffset can be minimized r cmpensated. The fllwing example shws a methd f creating a vltage greater than V DD fr a telecm applicatin that requires a vltage greater than battery grund. Cnverter Pwer Stage C OUT C BYP R LO Lw Vltage Output T V DD R HI - FB COMP T GATE SENP SEN RSP Part f Translatr 15k Sft start 15k 1.5V Errr Amplifier - T TPWM current Cmparatr cmparatr RTN, COM, RSN MODE Figure 35. Buck-Bst Cnfiguratin Example 21

www.ti.cm APPLICATION INFORMATION (cntinued) Bias Supplies The has tw bias supplies, the AUX input/utput and the V BIAS supply, each with its wn UVLO. The AUX supply is a current-limited, 10 V regulatr that draws its current frm V DD. It may be verridden by feeding a higher external vltage int this pin t imprve efficiency. The gate driver draws large current pulses frm this rail. It requires lw-impedance bypass capacitrs, such as a 1 µf ceramic capacitr, lcated next t the and cnnected by lw-impedance cnnectins. A UVLO prevents gate drive if the vltage is less than 8 V. A 17.5 V vervltage lckut (OVLO) n AUX prevents an pen-lp cnverter, such as the ne in Figure 1, frm damaging the part by inhibiting gate drive. The V BIAS regulatr draws its pwer frm the AUX pin. The V BIAS regulatr is a current-limited, 5.1 V regulatr that requires a capacitr between 0.08 µf 1.5 µf frm its utput t RTN. An ptcupler can be pwered frm this rail. Current drawn frm the V BIAS pin shuld nt exceed 5 ma. This regulatr als has a UVLO that turns the cnverter ff if it is pulled belw 4.6 V. BLANKING CONSIDERATIONS AND RSP Prgrammable blanking typically eliminates the need fr the traditinal RC filter n the RSP input. Blanking prevents the current-mde and current-limit cmparatrs frm reacting t the current spike that ccurs as the cnverter s switching MOSFET turns n. This current spike cnsists f the MOSFET gate current, parasitic drain capacitance current, and utput rectifier recvery current. The required blanking perid is highly dependent n the specific design. Having t shrt a blanking time causes the cnverter t current limit, r switch erratically at less than full lad. A lnger blanking time increases the minimum lad required befre cycle skipping ccurs. The pwer required t run an Ethernet link shuld prvide mst PDs adequate lad t prevent cycle skipping. Starting recmmendatins fr the BL setting are: Use the lng blanking perid fr transfrmer-based designs perating belw abut 150 khz r using synchrnus rectifiers. Use the shrt blanking perid fr transfrmer-based designs perating abve 150 khz r using Schttky utput dides. Use the shrt blanking perid fr buck r bst cnverter tplgies. BL pin cnnectins t achieve each blanking length are listed belw. BL CONNECTION Open RSN V BIAS BLANKING OPERATION Nne (Minimum current-sense lp delay) Minimum plus 70 ns Minimum plus 105 ns An RC filter may be used n the RSP pin shuld the need arise. A bias current f less than 8 µa flws ut f the RSP pin. The blanking perid is specified as an increase in bservable minimum gate n-time. The blanking circuit, current limit r PWM cmparatr, cntrl lgic, and laded gate driver cntribute t the bservable current-sense lp delay. The PWM and current limit cmparatrs d nt respnd t signals shrter than 20 ns, prviding sme inherent blanking within the current-sense lp delay measurement. The blanking circuit cntributes almst negligible lp delay when the BL pin is pen. The blanking perids are measured as the difference between the bserved gate n-time with BL pen, and its perid with the BL pin cnnected high r lw. The blanking perids shwn d nt include the cmparatr delays. While many cnverter designs d nt require a resistr in series with RSP, there may be instances where ne is required t prtect the pin frm harmful currents. Even thugh the RSP pin has an abslute maximum vltage rating f 0.3 V, the ESD clamp can withstand ccasinal negative current pulses, prvided they are limited t less than 100 ma. Sme supply tplgies, such as the self-driven synchrnus rectifier circuit f Figure 38, have the ability t drive energy back thrugh the transfrmer. This causes negative vltages n RSP and currents that can exceed the 100 ma. A small series prtectin resistr n RSP prtects the device withut requiring a Schttky dide clamp. 22