Session 4: Analog ircuits JT iasing Single stage amplifier 1
Outline JT Amplifier 2
JT: ipolar Junction Transistor i D A p D n R F F : Forward R : Reverse V D p n p n p n 1 2 1 : F 2 : R Active V 1 : F 2 : F Saturation 1 2 Qp utoff 1 : R 2 : R Reversed 1 : R 2 : F V Qn 3
JT: ipolar Junction Transistor A p D n i D V D Qn / Δ Δ2 2 / / Δ Δ2 2 / 4
JT onfigurations : ommon mitter : ommon ase : ommon ollector Qn Qn Qn Input haracteristic vs. for different Output haracteristic vs. for different or Transfer haracteristic vs. or for different 5
: ommon mitter Qn Input haracteristic 0 0 very little dependence to output voltage Output haracteristic arly voltage Saturation 30 20 10 0 620 Active: 1 600 560 Active 0.2 0.5 utoff 6
: Transistor Model Qn Saturation utoff Output haracteristic SOA: Safe Operatin g Area 0.2 7
: Output haracteristic Ideally linear: SPI Qn 1 Saturation utoff 1 8
eta : urrent Gain 9
: ommon ase Qn Output haracteristic Saturation 0.4 Input haracteristic Active utoff 3 2 1 0 0 0 Active: 1 very little dependence to output voltage Δ Δ2 10
Large Signal Model Qn Saturation 2 1 Active Saturation 0.2~0.3 0.4 ideal ideal 0.7 11
Voltage Amplifier Qn 0.1v 10v 1 cutoff active saturation 12
iasing: V = cte 0.1v 10v cutoff active saturation 13
iasing: I = cte For max swing: For max gain: 10 1 10 ~ 5 ~ 0.3 100 ~ 5Ω ~ 9.7Ω 10 1 930Ω What is the problem? Replace it with transistor with 250 2.5 1052.52.5 14
iasing: I = cte 10 1 100 For max swing: ~ 5 430Ω Negative feedback! 15
iasing: I = cte independent of ~ 2.7 4Ω 2.7 10 6 1 2 2Ω 10 5Ω 10v Where is the tradeoff? 0.7 6.7 16
iasing: I = cte 2.7 10 4Ω 6 1 2 2Ω Assume: 10 10 10 0.1 73Ω 2.7 10 27Ω 4Ω 6 1 2 2Ω? This is for design how about analysis 17
iasing: I = cte 0.1 73Ω 2.7 10 27Ω 6 2 10 4Ω 1 2Ω Assume: 0.1 2.7 2 1 0.01 What if was 10! 10 KVL / 1 1 For the above numbers: 2 1.0120.0119.70.92 18
iasing: I = cte D similar Only in Integrated ircuits! / 1 / 1 area 19
iasing: xample 01 15V 100 0.7 0.07 150kΩ 4 0.01 Q1 5.6kΩ 9.4 3.3 Q2 3.9kΩ 10.1 5.9 1.26 1.26 [ma] [V] 1 1.26 6.1 4.2 4.08 56kΩ / 150 56 41kΩ 3.3kΩ 1 15V Q1 5.6kΩ 3 0.9 4.7kΩ 9.89 KVL / 15V Q2 3.9kΩ 10.59 5.31 4.7kΩ 3.9 0.75.60.9 1.13 KVL 3.3kΩ 4.08 3.340.8/101 0.91 20
iasing: xample 02 Vcc=10V 100 0.7 1.05 8.2kΩ 1.4 0.015 Q2 1.49 [ma] [V] 1.05 1.49 1.4 9.3 Q1 1.05 0.01 0.7 470Ω 1.49 21
iasing: xample 03 2.3 2 Vcc=9V 3.3 kω 2.2 kω 1.4 2.4 Q1 0.007 7.46 5.26 Q2 100 0.7 0.7 1.7 8.3 3.3 [ma] [V] 3.3 kω 2 1.7 2.4 3.56 9V 2.2 kω 0.7 0.023 47kΩ 0.7 1.7 1 kω 0.7 1.7 Q1 0.7 Q2 47kΩ 8.3 330 0.7 47 1.65 0.7 47 1 kω 22
iasing: xample 04 Vcc=10V 100 0.7 0.1 68 kω 3.3 15 kω 1.8 18 kω Q2 Q1 3.9 kω 5.71 2.6 1.1 1 kω 1.1 [ma] [V] Find bias points if 8.2 Ω 1.1 1.1 1.5 3.11 3.3 10 Q2 8.2 kω 2.8 2.6 0.2 101.18.2 2.6 1.62 0.88 [ma] [V] 1.1 0.88 1.5 0.2 23
Linear JT Amplifier V 26 200 V in R Qn V o 1 sin 1 sin 2 sin sin 24
JT Small Signal Model (hπ) Qn 1 1 1 Input resistance: Output resistance: Tranceonductance: 1 25
xample 01 D: A: 1 100.7 0.01 1 10 930Ω Assume Design for 100 1 Find,, window for ~ cutoff saturation and maximum swing 10? 5 5Ω 0.2~0 ~ ollector resistance mitter s circuit resistance if 0: 26
xample 02 1Ω 0.1 10 73Ω 2.7 10 27Ω 6 2 2Ω 4Ω 1 Assume A circuit 100 ~ Find,, 1 1 1 1 : ~20Ω 10 1 20 21 4 3.5 100 2101 100 1.8 27
xample 02 1Ω 10 73Ω 27Ω 4Ω 2Ω 1.8 How we can increase gain? 1Ω 10 73Ω 27Ω 4Ω 2Ω ypass capacitance 28
xample 03 10 Design a buffer A circuit : 1 window for saturation cutoff 5Ω 0 9.3~10? 5 0 105.7 0.01430Ω 1 1 1 1 1 1 1 1 ~1 29
xample 03 1 1 1 1 1 30
xample 04 Multistage Amplifier 1Ω 73Ω 27Ω 10 2Ω 930Ω Design an amplifier: 1 100 1000 103 17Ω 105 15Ω 10 1Ω A circuit 1Ω 20Ω 27 73 20 20 0.69 1 7Ω 930Ω 5Ω 5 200 7 930 73 7Ω 1Ω 10143 buffer 5Ω 31
xample 05,, 10 73 2.7 27 7 3 8 2 2 1 27 2 7.3 73 1 4 4 5.7 430 5 5 1 A circuit 7 2 4 430 5 20? 1.5 4 5 32
ommon ase 1 1 1 33
xample 05,, 1.5 4 5 1.5 1 4 5 160 5 5 1 160 2.5 4 4 1 63Ω 34
ascode Amplifier, neglecting base current 6.8 5.6 18 5 4.7 11.2 A circuit: 1.5 11.5 10.5 4.3 1 4.3 18 6.85.64.7 1.1 1.5 1 1.5 245 245 35
Some Notes: 36
Summary 1 1 1 1 1 1 1 37
? V A 1 1 1 1 1 1 38
Input / Output Impedances Input port Output port 39