ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout! Inverter Layout! Gate Layout and Stick Diagrams! Design Rules! Standard Cells! Linear Elements Penn ESE 570 Spring 2017 Khanna Adapted from GATech ESE3060 Slides 2 MOSFET MOSFET IV Characteristics 50 V DS! Metal Oxide Semiconductor Field Effect Transistor " Primary active component for the term " Three terminal device V GS = V G - V S V DS = V D - V S " Voltage at gate controls conduction between two other terminals (source, drain) 3 I DS Drain current [arbitrary unit] 40 30 20 10 0 0 2 4 6 8 10 Gate to source voltage [V] V GS Define: V th = Threshold Voltage 4 MOSFET IV Characteristics MOSFET IV Characteristics V DS <V GS -V TH V GS -V th V GS -V th I DS I DS V DS V GS -V TH V DS 5 V DS 6 1
MOSFET Zeroeth Order Model MOSFET Zeroeth Order Model I DS! Ideal Switch V GS > V th # switch is closed, conducts V GS < V th # switch is open, does not conduct! Gate draws no current from input " Loads input capacitively (gate capacitance) V GS 7 8 MOSFET N-Type, P-Type Symmetry! N negative carriers " electrons! Switch turned on positive V GS! P positive carriers " holes! Switch turned on negative V GS! NMOS: " Electrons are carriers " Electrons flow from source-to-drain " From lowest voltage#highest " Drain is most positive terminal " Current flows from drain-tosource V th,n > 0 V GS > V th,n to conduct V th,p < 0 V GS < V th,p to conduct 9! Symmetric Device " Like a resistor, doesn t know difference between two ends " Drain and source are defined by circuit connections 10 Symmetry MOSFET N-Type, P-Type! PMOS: " Holes are carriers " positively " Holes flow from source#drain " Flow from highest voltage#lowest " Drain is most negative terminal " Current flows from source-todrain! N negative carriers " electrons! Switch turned on positive V GS! P positive carriers " holes! Switch turned on negative V GS! Symmetric Device " Like a resistor, doesn t know difference between two ends " Drain and source are defined by circuit connections 11 V th,n > 0 V GS > V th,n to conduct V th,p < 0 V GS < V th,p to conduct 12 2
Typical N-Well CMOS Process Typical N-Well CMOS Process 13 14 Interconnect Cross Section CMOS Layers! Standard n-well Process " Active (Diffusion) (Drain/Source regions) " Polysilicon (Gate Terminals) " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMOS bulk region) " n Select (used with active to create n-type diffusion) " p Select (used with active to create p-type diffusion) ITRS 2007 15 16 NMOS vs PMOS MOS Layout Well, Active, Select! NMOS built on p substrate! PMOS built on n substrate " Needs an N-well 17 18 3
MOS Layout Poly Gate Typical N-Well CMOS Process 19 20 CMOS Layers Wiring and Contact Layout! Standard n-well/p-substrate Process " Active (Diffusion) (Drain/Source regions) " Polysilicon (Gate Terminals) " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) Diffusion (Active) Contact Poly Contact Via (metal1-metal2) " Via (connects metal 2 to metal 1) " nwell (PMOS bulk region) " n Select (used with active to create n-type diffusion) " p Select (used with active to create p-type diffusion) 21 22 Substrate and Well Contacts Layout Example: CMOS Inverter! Properties " Set Well and Substrate Voltages to Vdd and Gnd " Prevent Forward Biasing and Latch-Up " Must Be at Least One per Well " Should Be Placed Regularly! Set Pitch (place well and power/ground busses) 23 24 4
Layout Example: CMOS Inverter Layout Example: CMOS Inverter! Add Transistors (active, select and poly)! Make Connections (poly, metal, and contacts) 25 26 Layout Example: CMOS Inverter Layout Example: CMOS Inverter! Add Substrate and Well Contacts! Add External Wiring and Resize 27 28 Example: Mystery Gate Example: NAND Gate 29 30 5
Example: NAND Gate (Horizontal) Symbolic Layout! Stick diagrams capture spatial relationships, but abstract away design rules (coming up next )! What function does this gate perform? " How many NMOS? PMOS? D/S connections? 31 32 Layout Design Rules Design Rules! Physical Layer " Design Rules are a set of process-specific geometric rules for preparing layout artwork to enable the layout to be manufacturable, i.e. preserve all of the circuit structures and feature geometries intended by the chip designers! Purpose " Realize fabricated chips that are die area efficient and manufacturable by balancing the conflicting objectives to minimize die area and maximize yield! Design Rule Waiver " Explicit permission granted by the fabrication organization to the design organization to violate certain design rules or to allow certain design rule errors on a given design! Minimum Separation [A] " Intralayer (all layers) " Interlayer (active to poly/well/select) " From Transistor! Minimum Width (all layers) [B]! Minimum Overlap [C] " Past Transistor (poly, active) " Around Contact Cut (all contacted layers) " Around Active (well, select)! Exact Size (contact cuts) [D] 33 34 Scalable CMOS Rules Width/Spacing Design Rules! Definition " Design Rules Based on a Unitless Parameter (λ) " λ Scales with Process Feature Size N-Well Rules Active Rules Poly Rules " λ = 0.5*L min " Example: λ = 0.6um in a 1.2um Process! Advantages " Simplifies Design - Requires Learning Only One Set of Design Rules " Facilitates Translating Designs between Processes Metal Rules 35 36 6
Contact Design Rules Potential Consequences of Design Rule Violations! Inter-Layer Design Rule Origins Intended Transistor Catastrophic Error Unintended misalignment cause Source-Drain short circuit Intended Unrelated Poly & Diffusion Catastrophic Error Unintended overlap cause fabrication of a parasitic Transistor 37 38 Potential Consequences of Design Rule Violations Design Capture Tools! Inter-Layer Design Rule Origins Both Metal 1 & Diffusion Intended Contact Alignment Contact and Via Masks M1 contact to n-diffusion M1 contact to p-diffusion M1 contact to poly Mn contact to Mn-1 for n = 2, 3,.. -> Contact Mask -> Via Mask Both Metal 1 & Diffusion Mask misalignment Error Unintended misalignment cause poor contact! Hardware Description Languages (HDL) & " capture a textual hierarchical description of design at abstraction ranging from gate or even transistor level up to a behavioral description (eg. VHDL, Verilog)! Schematic capture " capture a structural, hierarchical graphical representation of the design netlist (eg. Cadence Composer)! Layout " capture a hierarchical view of the physical geometric aspect of a design. The units of hierarchy are called cells, and have physical extent (size). In general, good design requires that only one cell contain the design info for a particular area of the chip (eg. Cadence Virtuoso) 39 40 Rules Checking DRC Error Example! Complex designs invariably suffer design and design entry errors. There are a number of tools and methodologies to detect and correct " Physical Design Rules Checking (DRC) checks for design rule violations such as minimum spacing etc. DRC checking is complicated by hierarchy and overlap between cells " Electrical Rule Checking (ERC) checks for violations such as shorts between Vdd and GND, opens, and so on " Layout vs. Schematic (LVS) checks for a one-to-one correspondence between transistor schematic and the layout! Formal verification is used to show that the design satisfies a formal description of what it should do! Simulation is used to show that the design is functional on some well selected set of input vectors! Timing analysis is used to predict design performance 41 42 7
Circuit Extraction! Standard Cells Circuit extraction extracts a schematic representation of a layout, including transistors, wires, and possibly wire and device resistance and capacitance.! Lay out gates so that heights match " "! Motivation: automated place and route "! Rows of adjacent cells Standardized sizes EDA tools convert HDL to layout Circuit extraction is used for LVS, and for spice simulation of layouts 43 Standard Cell Area 44 Standard Cell Layout Example All cells uniform height inv nand3 Cell area Width of channel determined by routing http://www.laytools.com/images/standardcells.jpg 45 CMOS Process Enhancements 46 CMOS Poly-Poly Capacitors W L C. Bipolar Transistors 47 48 8
Resistors 22nm 3D FinFET Transistor High-k gate dielectric Tri-Gate transistors with multiple fins connected together increases total drive strength for higher performance 49 http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_presentation.pdf 50 High-K dielectric High-K dielectric Survey SiO 2 Dielectric Poly gate MOSFET High-K Dielectric Metal gate MOSFET Dielectric constant=3.9 Dielectric constant=20 51 Wong/IBM J. of R&D, V46N2/3P133 168, 2002 52 Big Idea! Layouts are physical realization of circuit " Geometry tradeoff " Can decrease spacing at the cost of yield " Design rules! Can go from circuit to layout or layout to circuit by inspection! Can draw stick diagram for any logic gate Admin! HW 1 should be submitted! HW 2 due next week 1/28 " Posted tonight after class! Office hours updated on Course website " Tania: W 2-4:30 in Moore 203E " Ryan: MW 4:30-6pm in DRLB 4C8 " Watch piazza and course website for location announcement " Location can change, especially later in course. Will get announced on Piazza 53 54 9