TEL:7-896822 FAX:7-876182 E-MAIL: szss2@16.com v1.77 HMC64 Typical Applications The HMC64 is ideal for: EW Receivers Weather & Military Radar Satellite Communications Beamforming Modules Phase Cancellation Functional Diagram Features Low RMS Phase Error:. Low Insertion Loss: 6. db High Linearity: +8 dbm 6 Coverage, LSB =.62 Die Size: 2.7 x.99 x.1 mm General Description The HMC64 is a 6-bit digital phase shifter die which is rated from 9 to 12 GHz, providing 6 degrees of phase coverage, with a LSB of.62 degrees. The HMC64 features very low RMS phase error of. degrees and extremely low insertion loss variation of ±.6 db across all phase states. This high accuracy phase shifter is controlled with complementary logic of /-V, and requires no fi xed bias voltage and is internally matched to Ohms with no external components. Simple external level shifting circuitry can be used to convert a positive CMOS control voltage into complementary negative control signals. Electrical Specifications, T A = +2 C, Ohm System, Control Voltage = /-V Parameter Min. Typ. Max. Units Frequency Range 9 12 GHz Insertion Loss* 6. 1. db Input Return Loss* db Output Return Loss* 12 db Phase Error* ±7-1 / + deg RMS Phase Error. deg Insertion Loss Variation* ±.6 db Input Power for 1 db Compression 22 dbm Input Third Order Intercept 8 dbm Control Voltage Current <1 μa *Note: Major States Shown - 2 SUNSTAR 2 Alpha 射频通信 http://www.rfoe.net/ Road, Chelmsford, MA TEL:7-897 1824 Phone: 978-2-4 FAX:7-876182 978-2-7 szss2@16.com
TEL:7-896822 FAX:7-876182 E-MAIL: szss2@16.com v1.77 HMC64 Insertion Loss, Major States Only Normalized Loss, Major States Only 4 INSERTION LOSS (db) -2-4 -6-8 -1-12 8 9 1 11 12 1 Input Return Loss, Major States Only RETURN LOSS (db) -1 - -2-2 - 8 9 1 11 12 1 Output Return Loss, Major States Only NORMALIZED LOSS (db) 2 1-1 -2 - -4 8 9 1 11 12 1 Phase Error, Major States Only PHASE ERROR (degrees) 2 1-1 - -2 8 9 1 11 12 1 4 Relative Phase Shift Major States, Including All Bits RETURN LOSS (db) -1 - -2-2 - 8 9 1 11 12 1 RELATIVE PHASE SHIFT (degrees) 2 2 1 8 9 1 11 12 1 SUNSTAR 2 Alpha 射频通信 http://www.rfoe.net/ Road, Chelmsford, MA TEL:7-897 1824 Phone: 978-2-4 FAX:7-876182 978-2-7 szss2@16.com - 21
TEL:7-896822 FAX:7-876182 E-MAIL: szss2@16.com v1.77 HMC64 Relative Phase Shift, RMS, Average, Max, All States Input IP, Major States Only RELATIVE PHASE SHIFT (degrees) 2 2 1 RMS AVERAGE MAX -1 9 9. 1 1. 11 11. 12 Input IP2, Major States Only IP2 (dbm) 1 9 8 7 6 9 9. 1 1. 11 11. 12 RMS Phase Error vs. Temperature 2 IP (dbm) Input P1dB, Major States Only P1dB (dbm) 4 4 2 9 9. 1 1. 11 11. 12 4 2 2 1 9 9. 1 1. 11 11. 12 Insertion Loss vs. Temperature, Major States Only RELATIVE PHASE SHIFT (degrees) 1 +2C +8C C INSERTION LOSS (db) -2-4 -6-8 -1 9 9. 1 1. 11 11. 12-1 9 9. 1 1. 11 11. 12-22 SUNSTAR 2 Alpha 射频通信 http://www.rfoe.net/ Road, Chelmsford, MA TEL:7-897 1824 Phone: 978-2-4 FAX:7-876182 978-2-7 szss2@16.com
TEL:7-896822 FAX:7-876182 E-MAIL: szss2@16.com v1.77 HMC64 Phase Error vs. State PHASE ERROR (degrees) 2 1-1 - Truth Table 9., 1, 1., 11, 11., 12 GHz -2 4 9 18 22 27 6 STATE (degrees) 9 GHz Control Voltage Input Absolute Maximum Ratings Input Power (RFIN) Channel Temperature (Tc) C Thermal Resistance (channel to die bottom) 27 dbm (T= +8 C) 1 C/W Storage Temperature -6 to + C Operating Temperature to +8 C Control Voltage State Low () High (1) Bit 1 Bit 2 Bit Bit Bit 4 Bit 4 Bit Bit Bit 6 Bit 6 Bias Condition -2. to -.V @.4 μa Typ. to +.V @.4 μa Typ. ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Phase Shift (Degrees) RFIN - RFOUT 1 1 1 1 Reference* 1 1 1 1 1.62 1 1 1 1 1 11.2 1 1 1 1 22. 1 1 1 1 4. 1 1 1 1 9. 1 1 1 1 18. 1 1 1 1 1 1 4.7 Any combination of the above states will provide a phase shift approximately equal to the sum of the bits selected. *Reference corresponds to monotonic setting Pad Descriptions Pad Number Function Description Interface Schematic 1,, 4, 6 GND These pads and die bottom must be connected to RF/DC ground. 2 RFIN This port is DC coupled and matched to Ohms. RFOUT This port is DC coupled and matched to Ohms. 7, 9, 11, BIT6, BIT4 BIT, BIT Inverted Control Input. See truth table and control voltage tables. 8, 1, 12, 1, 14, 16 BIT6, BIT4, BIT, BIT2, BIT1, BIT Non-Inverted Control Input. See truth table and control voltage tables. SUNSTAR 2 Alpha 射频通信 http://www.rfoe.net/ Road, Chelmsford, MA TEL:7-897 1824 Phone: 978-2-4 FAX:7-876182 978-2-7 szss2@16.com - 2
TEL:7-896822 FAX:7-876182 E-MAIL: szss2@16.com v1.77 HMC64 Outline Drawing Die Packaging Information [1] Standard Alternate GP-2 (Gel Pack) [2] [1] Refer to the Packaging Information section for die packaging dimensions. [2] For alternate packaging information contact Hittite Microwave Corporation. Application Circuit NOTES: 1. ALL DIMENSIONS IN INCHES (MILLIMETERS) 2. DIE THICKNESS IS.4. BACKSIDE METALLIZATION: GOLD 4. BACKSIDE METAL IS GROUND. BOND PADS METALLIZATION: GOLD 6. OVERALL DIE SIZE ±.2 Note: This circuit converts a single line positive (/+V) control signal to complementary negative (/-V) control signals. - 24 SUNSTAR 2 Alpha 射频通信 http://www.rfoe.net/ Road, Chelmsford, MA TEL:7-897 1824 Phone: 978-2-4 FAX:7-876182 978-2-7 szss2@16.com
TEL:7-896822 FAX:7-876182 E-MAIL: szss2@16.com v1.77 HMC64 Assembly Diagram Handling Precautions Follow these precautions to avoid permanent damage. Storage: All bare die are placed in either Waffle or Gel based ESD protective containers, and then sealed in an ESD protective bag for shipment. Once the sealed ESD protective bag has been opened, all die should be stored in a dry nitrogen environment. Cleanliness: Handle the chips in a clean environment. DO NOT attempt to clean the chip using liquid cleaning systems. Static Sensitivity: Follow ESD precautions to protect against > ± 2V ESD strikes. Transients: Suppress instrument and bias supply transients while bias is applied. Use shielded signal and bias cables to minimize inductive pick-up. General Handling: Handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. The surface of the chip has fragile air bridges and should not be touched with vacuum collet, tweezers, or fi ngers. Mounting The chip is back-metallized and can be die mounted with electrically conductive epoxy. The mounting surface should be clean and fl at. Epoxy Die Attach: Apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fi llet is observed around the perimeter of the chip once it is placed into position. Cure epoxy per the manufacturer s schedule. Wire Bonding Ball or wedge bond with.2mm (1 mil) diameter pure gold wire. Thermosonic wirebonding with a nominal stage temperature of deg. C and a ball bonding force of 4 to grams or wedge bonding force of 18 to 22 grams is recommended. Use the minimum level of ultrasonic energy to achieve reliable wirebonds. Wirebonds should be started on the chip and terminated on the package or substrate. All bonds should be as short as possible <.1mm (12 mils). SUNSTAR 2 Alpha 射频通信 http://www.rfoe.net/ Road, Chelmsford, MA TEL:7-897 1824 Phone: 978-2-4 FAX:7-876182 978-2-7 szss2@16.com - 2