Design Assistance Assembly Assistance Die handling cnsultancy Hi-Rel die qualificatin Ht & Cld die prbing Electrical test & trimming Custmised Pack Sizes / Qtys Supprt fr all industry recgnised supply frmats: Waffle Pack Gel Pak Tape & Reel Onsite strage, stckhlding & scheduling 1% Visual Inspectin MIL-STD 88 Cnditin A MIL-STD 88 Cnditin A On-site failure analysis Bespke 24 Hur mnitred strage systems fr secure lng term prduct supprt On-site failure analysis Cntact baredie@micrss.cm Fr price, delivery and t place rders HMC647 www.analg.cm www.micrss.cm
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v1.28 HMC647 PHASE SHIFTER, 2.5 -.1 GHz Typical Applicatins The HMC647 is ideal fr: EW Receivers Weather & Military Radar Satellite Cmmunicatins Beamfrming Mdules Phase Cancellatin Functinal Diagram Features Lw RMS Phase Errr: 1. Lw Insertin Lss: 4 db High Linearity: +54 dbm Psitive Cntrl Lgic 6 Cverage, LSB = 5.625 Die Size:.85 x 1.9 x.1 mm General Descriptin Electrical Specificatins, T A = +25 C, Vss= V, Vdd= +5V, Cntrl Vltage = /+5V, 5 Ohm System The HMC647 is a 6-bit digital phase shifter die which is rated frm 2.5 t.1 GHz, prviding 6 degrees f phase cverage, with a LSB f 5.625 degrees. The HMC647 features very lw RMS phase errr f 1. degrees and extremely lw insertin lss variatin f ±.5 db acrss all phase states. This high accuracy phase shifter is cntrlled with psitive cntrl lgic f /+5V, and is internally matched t 5 Ohms with n external cmpnents. Parameter Min. Typ. Max. Units Frequency Range 2.5.1 GHz Insertin Lss* 4 6 db Input Return Lss* 16 db Output Return Lss* 17 db Phase Errr* ± +5 / -15 deg RMS Phase Errr 1. deg Insertin Lss Variatin* ±.5 db Input Pwer fr 1 db Cmpressin 1 dbm Input Third Order Intercept 54 dbm Cntrl Vltage Current 5 25 μa Bias Cntrl Current 5 15 ma *Nte: Majr States Shwn - 2 2 Alpha Rad, Chelmsfrd, MA 1824 Phne: 978-25-4 Fax: 978-25-7
HMC647 v1.28 PHASE SHIFTER, 2.5 -.1 GHz Insertin Lss, Majr States Only Nrmalized Lss, Majr States Only 4 INSERTION LOSS (db) -2-4 -6-8 -1-12 2 2.4 2.8.2.6 Input Return Lss, Majr States Only RETURN LOSS (db) -1-15 -2-25 - 2 2.4 2.8.2.6 Output Return Lss, Majr States Only NORMALIZED LOSS (db) Phase Errr, Majr States Only PHASE ERROR (degrees) 2 15 1 5-1 -15 2 1-1 -2 - -4 2 2.4 2.8.2.6-2 2 2.4 2.8.2.6 4 Relative Phase Shift Majr States, Including All Bits RETURN LOSS (db) -1-15 -2-25 - 2 2.4 2.8.2.6 RELATIVE PHASE SHIFT (degrees) 5 25 2 15 1 5 2 2.4 2.8.2.6 2 Alpha Rad, Chelmsfrd, MA 1824 Phne: 978-25-4 Fax: 978-25-7 -
HMC647 v1.28 PHASE SHIFTER, 2.5 -.1 GHz Relative Phase Shift, RMS, Average, Max, All States Input IP, Majr States Only 8 RELATIVE PHASE SHIFT (degrees) Input IP2, Majr States Only IP2 (dbm) 25 2 15 1 5 14 1 12 11 1 9 RMS AVERAGE MAX -1 2.5 2.6 2.7 2.8 2.9..1 8 2.5 2.6 2.7 2.8 2.9..1 RMS Phase Errr vs. Temperature IP (dbm) Input P1dB, Majr States Only P1dB (dbm) 75 7 65 6 55 5 45 4 2.5 2.6 2.7 2.8 2.9..1 4 5 25 2 15 1 2.5 2.6 2.7 2.8 2.9..1 Insertin Lss vs. Temperature, Majr States Only 2 RELATIVE PHASE SHIFT (degrees) 15 1 5 +25C +85C 5C -1 2.5 2.6 2.7 2.8 2.9..1 INSERTION LOSS (db) -2-4 -6-8 -1 2.5 2.6 2.7 2.8 2.9..1-4 2 Alpha Rad, Chelmsfrd, MA 1824 Phne: 978-25-4 Fax: 978-25-7
HMC647 v1.28 PHASE SHIFTER, 2.5 -.1 GHz Phase Errr vs. State Abslute Maximum Ratings PHASE ERROR (degrees) 1 5 Truth Table 2.7, 2.8, 2.9,.,.1 GHz -1 45 9 15 18 225 27 15 6 Cntrl Vltage Input Phase Shift Bit 1 Bit 2 Bit Bit 4 Bit 5 Bit 6 (Degrees) RFIN - RFOUT Reference* 1 5.625 1 11.25 1 22.5 1 45. 1 9. 1 18. 1 1 1 1 1 1 54.75 Any cmbinatin f the abve states will prvide a phase shift apprximately equal t the sum f the bits selected. *Reference crrespnds t mntnic setting Pad Descriptins STATE (degrees) Input Pwer (RFIN) dbm (T= +85 C) Bias Vltage Range (Vdd) -.2 t +12V Bias Vltage Range (Vss) +.2 t -12V Channel Temperature (Tc) 15 C Thermal Resistance (channel t die bttm) 14 C/W Strage Temperature -65 t +15 C Operating Temperature 5 t +85 C ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Bias Vltage & Current Cntrl Vltage State Lw () High (1) Vdd Idd 5. 5.mA Vss Iss. 5.mA Bias Cnditin t.2 Vdc Vdd ±.2 Vdc @ 5 μa Typ. Pad Number Functin Descriptin Interface Schematic 1 RFIN This prt is DC cupled and matched t 5 Ohms. 2, 11 GND These pads and die bttm must be cnnected t RF/DC grund. Vdd Supply vltage. 4-6, 8-1 BIT1, BIT2, BIT, BIT4, BIT5. BIT6 Cntrl Input. See truth table and cntrl vltage tables. 7 Vss Supply vltage. 12 RFOUT This prt is DC cupled and matched t 5 Ohms. 2 Alpha Rad, Chelmsfrd, MA 1824 Phne: 978-25-4 Fax: 978-25-7-5
HMC647 v1.28 PHASE SHIFTER, 2.5 -.1 GHz Outline Drawing Die Packaging Infrmatin [1] Standard Alternate GP-1 (Gel Pack) [2] [1] Refer t the Packaging Infrmatin sectin fr die packaging dimensins. [2] Fr alternate packaging infrmatin cntact Hittite Micrwave Crpratin. NOTES: 1. ALL DIMENSIONS IN INCHES (MILLIMETERS) 2. DIE THICKNESS IS.4. BACKSIDE METALLIZATION: GOLD 4. BACKSIDE METAL IS GROUND 5. BOND PADS METALLIZATION: GOLD 6. OVERALL DIE SIZE ±.2-6 2 Alpha Rad, Chelmsfrd, MA 1824 Phne: 978-25-4 Fax: 978-25-7
v1.28 HMC647 PHASE SHIFTER, 2.5 -.1 GHz Assembly Diagram Handling Precautins Fllw these precautins t avid permanent damage. Strage: All bare die are placed in either Waffle r Gel based ESD prtective cntainers, and then sealed in an ESD prtective bag fr shipment. Once the sealed ESD prtective bag has been pened, all die shuld be stred in a dry nitrgen envirnment. Cleanliness: Handle the chips in a clean envirnment. DO NOT attempt t clean the chip using liquid cleaning systems. Static Sensitivity: Fllw ESD precautins t prtect against > ± 25V ESD strikes. Transients: Suppress instrument and bias supply transients while bias is applied. Use shielded signal and bias cables t minimize inductive pick-up. General Handling: Handle the chip alng the edges with a vacuum cllet r with a sharp pair f bent tweezers. The surface f the chip has fragile air bridges and shuld nt be tuched with vacuum cllet, tweezers, r fi ngers. Munting The chip is back-metallized and can be die munted with electrically cnductive epxy. The munting surface shuld be clean and fl at. Epxy Die Attach: Apply a minimum amunt f epxy t the munting surface s that a thin epxy fi llet is bserved arund the perimeter f the chip nce it is placed int psitin. Cure epxy per the manufacturer s schedule. Wire Bnding Ball r wedge bnd with.25mm (1 mil) diameter pure gld wire. Thermsnic wirebnding with a nminal stage temperature f 15 deg. C and a ball bnding frce f 4 t 5 grams r wedge bnding frce f 18 t 22 grams is recmmended. Use the minimum level f ultrasnic energy t achieve reliable wirebnds. Wirebnds shuld be started n the chip and terminated n the package r substrate. All bnds shuld be as shrt as pssible <.1mm (12 mils). 2 Alpha Rad, Chelmsfrd, MA 1824 Phne: 978-25-4 Fax: 978-25-7-7