Virtex-5 FPGA GTX Transceiver OC-48 Protocol Standard

Virtex-5 FPGA GTX Transceiver OC-48 Protocol Standard Characterization Report

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Revision History The following table shows the revision history for this document. Date Version Revision 02/23/10 1.0 Initial Xilinx release. www.xilinx.com Virtex-5 FPGA GTX Transceiver OC-48 Protocol

Virtex-5 FPGA GTX Transceiver OC-48 Protocol www.xilinx.com

Table of Contents Revision History............................................................. 3 Introduction................................................................. 7 Test Conditions.............................................................. 7 Transceiver Selection......................................................... 8 Summary of Results.......................................................... 8 OC-48 Electrical Characterization Details..................................... 9 Transmitter Near-End Output Eye.......................................... 10 Test Methodology...................................................... 10 Test Results........................................................... 10 Transmitter Output Jitter.................................................. 11 Test Methodology...................................................... 11 Test Results........................................................... 13 Receiver Jitter Tolerance................................................... 14 Test Methodology...................................................... 14 Test Results........................................................... 16 References.................................................................. 16 Virtex-5 FPGA GTX Transceiver OC-48 Protocol www.xilinx.com 5

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Virtex-5 FPGA GTX Transceiver OC-48 Protocol Standard Introduction This characterization report compares the electrical performance of the Virtex -5 FPGA RocketIO GTX transceiver against the GR-253-CORE standard [Ref 1]. Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) are a set of related standards for synchronous data transmission over fiber optic networks. SONET links are traditionally used in the telecommunication industry. The applicable test specifications are found in GR-253, International Telecommunication Union Telecommunication Standardization Sector (ITU-T) G.783 [Ref 2], and ITU-T G.957 [Ref 3]. The specifications are written for optical signals. Thus, a reference optical device is used in the test setup. The characterization is performed as per specifications at a data rate of 2.488 Gb/s across voltage, temperature, and worst-case transceiver performance corners. The following tests are included in this report: Transmitter Output Jitter Receiver Jitter Tolerance Test Conditions Table 1 and Table 2 show the supply voltage and temperature conditions, respectively. Table 1: Supply Voltage Test Conditions Condition MGTAVCC (V) MGTAVCCPLL (V) MGTAVTTRX (V) MGTAVTTTX (V) V MIN 0.95 0.95 1.14 1.14 V MAX 1.05 1.05 1.26 1.26 Notes: 1. Other FPGA voltages remain at their nominal values. Table 2: Temperature Test Conditions Condition Temperature ( C) T -40 40 Virtex-5 FPGA GTX Transceiver OC-48 Protocol www.xilinx.com 7

Transceiver Selection Table 2: Temperature Test Conditions (Cont d) Condition Temperature ( C) T 0 0 T 100 100 Transceiver Selection As part of the transceiver selection process, volume generic transceiver characterization is first performed across process, voltage, and temperature (PVT). The generic data from this characterization can be found in Virtex-5 FPGA RocketIO GTX Transceiver Characterization Report [Ref 4]. Protocol-specific characterization is then performed using representative transceivers from generic characterization. The chosen transceivers represent a mixture of worst-case and typical performance transmitters and receivers. Transceivers with the absolute worst-case transmitter output jitter and receiver jitter tolerance are selected from the corner silicon used during generic volume characterization. The histograms in this characterization report are therefore skewed towards worst-case performance and do not contain a true statistical representation of the entire population. Summary of Results Table 3 shows a comparison of the GTX transceiver using two reference clock rates: 311.04 MHz and 155.52 MHz. The data reported in Table 3 represents the worst-case voltage, temperature, and performance corners tested. Table 3: OC-48 Characterization: Summary of Results Test Parameter Specification (P2P) (1) Test Results for 311.04 MHz REFCLK (P2P) Test Results for 155.52 MHz REFCLK (P2P) Units Compliant Transmitter HP1 + LP 0.1 0.057 0.083 UI Yes Output Jitter (2) Receiver Jitter HP1 + LP 0.3 0.375 0.375 UI Yes Tolerance (3) HP2 + LP 0.1 0.375 0.375 UI Yes Notes: 1. P2P is peak to peak. 2. Tests were run for 60 seconds as per the ITU-T Recommendation G.2851. 3. The jitter tolerance tester is limited at 0.375 UI. Table 3 uses standard SONET terminology for filters: HP, HP1, HP2, and LP. These values are described in Figure 1 and Table 4. 8 www.xilinx.com Virtex-5 FPGA GTX Transceiver OC-48 Protocol

OC-48 Electrical Characterization Details X-Ref Target - Figure 1 100.00 Jitter Generate Mask Jitter Tolerance Mask 10.00 HP1 UI 1.00 HP2 0.10 HP LP 0.01 1 10 10 2 10 3 10 4 10 5 10 6 10 7 10 8 Frequency (Hz) RPT116_01_013009 Figure 1: OC-48 Jitter Tolerance and Generation Filter Specifications Table 4: SONET Filter Description Parameter HP HP1 HP2 LP Specification 12 KHz 6 KHz 1 MHz 20 MHz OC-48 Electrical Characterization Details This section contains the detailed OC-48 test methodology and results of each test summarized in Table 3. The GTX transceiver is configured using version 1.5 of the RocketIO GTX Wizard, including attribute settings. GTX transceiver attribute settings that differ from the GTX Wizard default settings are identified in Table 6, Table 7, page 12, and Table 9, page 15 for each test. Table 5 shows the phase-locked loop (PLL) settings for OC-48 characterization for 311.04 MHz and 155.52 MHz REFCLKs. Table 5: 2.488 Gb/s Line Rate PLL Settings Data Rate (Gb/s) PLL Frequency (GHz) REFCLK Frequency (MHz) PLL_DIVSEL_REF PLL_DIVSEL_FB and DIV PLL_TXDIVSEL_OUT and PLL_RXDIVSEL_OUT 2.488 2.488 311.04 1 2 4 = 8 2 2.488 2.488 155.52 1 4 4 = 16 2 Virtex-5 FPGA GTX Transceiver OC-48 Protocol www.xilinx.com 9

OC-48 Electrical Characterization Details Transmitter Near-End Output Eye This section details the test methodology and results of the transmitter near-end output eye. Test Methodology The FPGA is configured to transmit a received pattern on the TX data pins, and the resulting eye is captured using an Agilent DSA91304A infiniium high-performance oscilloscope for 1,000 samples at nominal voltage and room temperature. Table 6 details the test setup and conditions. Table 6: Transmitter Near-End Output Eye Test Setup and Conditions Parameter Value Load Board Measurement Instrument Pattern Temperature ML523 characterization platform, revision D (FF1136) Agilent DSA91304A infiniium high-performance oscilloscope: 13 GHz OTN bulk PRBS23 Room temperature TX Amplitude/Pre-Emphasis Maximum amplitude, TXDIFFCTRL = 111 TX Coupling Voltage AC coupled using DC blocks Nominal Test Results Figure 2 and Figure 3 show the transmitter near-end output eye at 2.488 Gb/s with 311.04 MHz and 155.52 MHz REFCLKs, respectively. X-Ref Target - Figure 2 RPT116_02_011509 Figure 2: TX Near-End Output Eye (2.488 Gb/s with 311.04 MHz REFCLK) 10 www.xilinx.com Virtex-5 FPGA GTX Transceiver OC-48 Protocol

OC-48 Electrical Characterization Details X-Ref Target - Figure 3 RPT116_03_011509 Figure 3: TX Near-End Output Eye (2.488 Gb/s with 155.52 MHz REFCLK) Transmitter Output Jitter This section details the transmitter output jitter test methodology and test results. Test Methodology Transmitter output jitter data was collected using the test setup shown in Figure 4. A JDSU ONT-506 optical network tester was used to collect the output jitter data. To obtain the appropriate reference clock rate for the GTX transceiver under test, the bit rate clock supplied by the JDSU optical network tester was divided down by factors of eight (311.04 MHz REFCLK) and sixteen (155.52 MHz REFCLK) using the Agilent 81134A pulse pattern generator. Virtex-5 FPGA GTX Transceiver OC-48 Protocol www.xilinx.com 11

OC-48 Electrical Characterization Details X-Ref Target - Figure 4 JDSU ONT-506 Agilent E3631A 0 6V, 5A / 0 ±25V, 1A Electrical Connection Display Adjust TxClk TxData RxClk On/Off Function GPIB Addr = 6 Voltage/Current 6V + 25V + - - + - COM - RxData MGTAVTT Power Supply Optical Connection 1550 1310 1550 1310 TxData TxData RxData RxData Agilent E3631A 0 6V, 5A / 0 ±25V, 1A Display Adjust Function Voltage/Current On/Off 6V + + + - 25V - - COM - GPIB Addr = 5 MGTAVTT Power Supply 81134A 3.35 GHz Pulse/Pattern Generator Display Keyboard and Miscellaneous Buttons Clock Input Output Channel 2 Output GPIB Addr = 13 Start Input Trigger Out Channel 1 Output Output Xilinx SMA-SFP RXN RXP TXP TXN Channel 1 TXP TXN RXP RXN MGTAVCC 1.0V AVCCPLL 1.0V AVTTTX 1.2V SMA Matched Pair Cables for GT Receiver SMA Matched Pair Cables for GT Transmitter SMA Matched Pair Cables for GT Clocks SC to LC Fibre Cable, Single Mode Cable for 1.0V Power Supply Cable for 1.2V Power Supply Cable for Ground Power Supply DC Blocks 50Ω Termination CLKN CLKP Channel 1 Virtex-5 FPGA GND AVTTRX 1.2V ML523 Virtex-5 FPGA DUT Board RPT116_04_010410 Figure 4: OC-48 Transmitter Output Jitter Test Setup Table 7 details the test setup and conditions. Table 7: OC-48 Transmitter Output Jitter Test Setup and Conditions Parameter Value Load Board ML523 characterization platform, revision D (FF1136) Measurement Instrument JDSU ONT-506 optical network tester BN 3061/90.27 Optical to SFP Board Pattern FiberOn FTM-3128C-SL2G OTN bulk PRBS23 REFCLK 311.04 MHz: JDSU bit rate clock divided by 8 155.52 MHz: JDSU bit rate clock divided by 16 Temperature T -40, T 0, T 100 12 www.xilinx.com Virtex-5 FPGA GTX Transceiver OC-48 Protocol

OC-48 Electrical Characterization Details Table 7: OC-48 Transmitter Output Jitter Test Setup and Conditions (Cont d) Parameter Value TX Amplitude/Pre-Emphasis TX Coupling Voltage GTX transceiver attributes: TXDIFFCTRL = 000 TXBUFDIFFCTRL = 101 TXPREEMPHASIS = 0000 AC coupled using DC blocks V MIN, V MAX Test Results Figure 5 and Figure 6 show the output jitter test results for 311.04 MHz and 155.52 MHz REFCLKs, respectively, using an OTN bulk PRBS23 pattern. Due to mechanical limitations, the measurement is taken with 4 to 6.8 inches of FR4 between the TXP/TXN FPGA pins and the SMA connectors on the ML523 characterization platform. The added FR4 channel contributes additional ISI (deterministic jitter) when tested with an OTN bulk PRBS23 pattern, artificially increasing the measured output jitter. X-Ref Target - Figure 5 Number of Datapoints 20 18 16 14 12 10 8 6 4 2 0 0.0300 0.0400 0.0500 0.0600 0.0700 0.0800 0.0900 TJ (UI) RPT116_05_012709 Figure 5: OC-48 Transmitter Output Jitter Test Results (OTN Bulk PRBS23) Using 311.04 MHz REFCLK Virtex-5 FPGA GTX Transceiver OC-48 Protocol www.xilinx.com 13

OC-48 Electrical Characterization Details X-Ref Target - Figure 6 Number of Datapoints 18 16 14 12 10 8 6 4 2 0 0.0300 0.0400 0.0500 0.0600 0.0700 0.0800 0.0900 TJ (UI) RPT116_06_012709 Figure 6: OC-48 Transmitter Output Jitter Test Results (OTN Bulk PRBS23) Using 155.52 MHz REFCLK Table 8 summarizes the results of the transmitter output jitter characterization. Table 8: Summary of OC-48 Transmitter Output Jitter Characterization (1) Parameter Specification (P2P) Test Results for 311.04 MHz REFCLK (P2P) Test Results for 311.04 MHz REFCLK (RMS) Test Results for 155.52 MHz REFCLK (P2P) Test Results for 155.52 MHz REFCLK (RMS) Units Compliant HP1 + LP 0.1 0.057 0.0053 0.083 0.0079 UI Yes Notes: 1. Tests were run for 60 seconds as per the specification. Receiver Jitter Tolerance This section details the receiver jitter tolerance test methodology and test results. Test Methodology Receiver jitter tolerance was measured using the test setup shown in Figure 4, page 12. The JDSU optical network tester generates an SDH frame using a PRBS23 pattern. The GTX transceiver under test recovers the data and transmits the pattern back to the error detector input of the optical network tester where bit errors are measured. To obtain the appropriate reference clock rate for the GTX transceiver under test, the bit rate clock supplied by the JDSU optical network tester is divided down by factors of eight (311.04 MHz REFCLK) and sixteen (155.52 MHz REFCLK) using the Agilent 81134A pulse pattern generator. Eye diagrams are generated using the Agilent DSA91304A oscilloscope. 14 www.xilinx.com Virtex-5 FPGA GTX Transceiver OC-48 Protocol

OC-48 Electrical Characterization Details Figure 7 shows a screen capture of the jitter injected to the GTX transceiver under test for OC-48 testing. X-Ref Target - Figure 7 RPT116_08_011509 Figure 7: OC-48 Eye Diagram of OTN Bulk PRBS23 Pattern Table 9 details the test setup and conditions. Table 9: OC-48 Receiver Jitter Tolerance Test Setup and Conditions Parameter Value Load Board ML523 characterization platform, revision D (FF1136) Measurement Instrument JDSU ONT-506 optical network tester BN 3061/90.27 Optical Module Optical to SFP Board Pattern FiberOn FTM-3128C-SL2G Xilinx HW-AFX-SMA-SFP, Rev. A OTN Bulk PRBS23 REFCLK 311.04 MHz: JDSU bit rate clock divided by 8 155.52 MHz: JDSU bit rate clock divided by 16 RX Coupling AC coupled using DC blocks Temperature T -40, T 0, T 100 Voltage V MIN, V MAX Table 10 lists filter parameter specifications. Table 10: OC-48 Jitter Tolerance Filter Description Parameter Specification HP1 HP2 LP 6 KHz 1 MHz 20 MHz Virtex-5 FPGA GTX Transceiver OC-48 Protocol www.xilinx.com 15

References Test Results Table 11 and Figure 8 show the results of jitter tolerance for both 311.04 MHz and 155.52 MHz REFCLKs at the worst-case voltage, temperature, and performance corners. Table 11: Summary of OC-48 Receiver Jitter Tolerance Characterization Parameter Specification (P2P) Test Results for 311.04 MHz REFCLK (P2P) Test Results for 155.52 MHz REFCLK (P2P) Units Compliant HP1 + LP 0.3 0.375 0.375 UI Yes HP2 + LP 0.1 0.375 0.375 UI Yes Notes: 1. The tolerance of the GTX transceiver devices exceeded the 0.375 UI limit of the jitter tolerance tester. X-Ref Target - Figure 8 1000.00 100.00 Jitter Tolerance Mask 10.00 UI 1.00 0.10 0.01 1 10 10 2 10 3 10 4 10 5 10 6 10 7 10 8 Frequency (Hz) RPT116_08_013009 Figure 8: JItter Tolerance Results for Both 311.04 MHz and 155.52 MHz REFCLKs References This characterization report uses the following references: 1. GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, Telcordia Technologies, Inc., http://telecom-info.telcordia.com/sitecgi/ido/newcust.pl?page=idosearch&docnum=gr-253. 2. ITU-T G.783, Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks, International Telecommunication Union, http://www.itu.int/rec/t-rec-g.783-200603-i/en. 3. ITU-T G.957, Optical Interfaces for Equipments and Systems Relating to the Synchronous Digital Hierarchy, International Telecommunication Union, http://www.itu.int/rec/t-rec-g.957-200603-i/en. 4. RPT109, Virtex-5 FPGA RocketIO GTX Transceiver Characterization Report. 16 www.xilinx.com Virtex-5 FPGA GTX Transceiver OC-48 Protocol