Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V ) Distributes One Clock Input to Ten s s Have Internal Series Damping Resistor to Reduce Transmission Line Effects Distributed and Ground Pins Reduce Switching Noise State-of-the-rt EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages DB OR DW PCKGE (TOP VIEW) P0 P1 1 2 3 4 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 1 14 13 Y description The CDC231 is a high-performance clock-driver circuit that distributes one input () to ten outputs (Y) with minimum skew for clock distribution. The output-enable () input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC231 operates at nominal 3.3-V. The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to. The CDC231 is characterized for operation from 0 C to 70 C. FUNCTION TBLE INPUTS OUTPUTS Yn L H Z H H Z L L L H L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated. PRODUCTION DT information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 199, Texas Instruments Incorporated POST OFFICE BOX 6303 DLLS, TEXS 726 1
logic symbol EN 6 23 21 19 18 16 14 11 9 4 2 Y This symbol is in accordance with NSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 23 21 19 6 7 8 P0 P1 18 16 Y 14 11 9 4 2 2 POST OFFICE BOX 6303 DLLS, TEXS 726
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range,........................................................ 0. V to 4.6 V Input voltage range, V I (see Note 1).................................................. 0. V to 7 V Voltage range applied to any output in the high state or power-off state, V O (see Note 1)................................................................ 0. V to 3.6 V Current into any output in the low state, I O.................................................. 24 m Input clamp current, I IK (V I < 0)........................................................... 18 m clamp current, I OK (V I < 0)........................................................ 0 m Maximum power dissipation at T = C (in still air) (see Note 2): DB package................. 0.6 W DW package................. 1.7 W Storage temperature range, T stg.................................................. 6 C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 10 C and a board trace length of 70 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 BT dvanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 3) MIN MX UNIT VCC Supply voltage 3 3.6 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0. V IOH High-level output current 12 m IOL Low-level output current 12 m fclock Input clock frequency 100 MHz T Operating free-air temperature 0 70 C NOTE 3: Unused pins (input or I/O) must be held high or low. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PRMETER TEST CONDITIONS MIN TYP MX UNIT VIK VCC =, II = 18 m 1.2 V VOH VCC =, IOH = 12 m 2 V VOL VCC =, IOL = 12 m 0.8 V II VCC = 3.6 V, VI = VCC or ±1 µ IO VCC = 3.6 V, VO = 2. V 7 70 m IOZ VCC = 3.6 V, VCC = or 0 ±10 µ ICC VCC = 3.6 V, IO = 0, VI =VCC or s high 0.3 s low 1 m s disabled 0.3 Ci VI = VCC or, VCC = 3., f = 10 MHz 4 pf Co VO = VCC or, VCC = 3., f = 10 MHz 6 pf Not more than one output should be tested at a time, and the duration of the test should not exceed one second. POST OFFICE BOX 6303 DLLS, TEXS 726 3
switching characteristics, C L = 0 pf (see Figures 1 and 2) PRMETER FROM (INPUT) TO (OUTPUT) VCC = 3., T = 2 C VCC = to 3.6 V, T = 0 C to 70 C MIN TYP MX MIN MX tplh 3.8 4.3 4.8 Y tphl 3.6 4.1 4.6 ns tpzh 2.4 4.9 6.0 1.8 6.9 Y tpzl 2.4 4.3 6.0 1.8 6.9 ns tphz 2.2 4.4 6.3 2.1 7.1 Y tplz 2.2 4.6 6.3 2.1 7.3 ns tsk(o) Y 0.3 0. 0. ns tsk(p) Y 0.2 0.8 0.8 ns tsk(pr) Y 1 1 ns tr Y 2. ns tf Y 2. ns UNIT switching characteristics temperature and coefficients over recommended operating free-air temperature and range (see Note 4) tplh(t) tphl(t) tplh(vcc) PRMETER verage temperature coefficient of low to high propagation delay verage temperature coefficient of high to low propagation delay verage VCC coefficient of low to high propagation delay FROM (INPUT) TO (OUTPUT) MIN MX UNIT Y 8 ps/10 C Y 0 ps/10 C Y 14 verage tphl(vcc) VCC coefficient of high to low propagation Y 100 delay tplh(t) and tphl(t) are virtually independent of VCC. tplh(vcc) and tphl(vcc) are virtually independent of temperature. NOTE 4: These data were extracted from characterization material and are not tested at the factory. ps/ 100 mv ps/ 100 mv 4 POST OFFICE BOX 6303 DLLS, TEXS 726
PRMETER MESUREMENT INFORMTION CDC231 From Under Test CL = 0 pf (see Note ) 00 Ω 00 Ω S1 6 V Open TEST tplh /tphl tplz /tpzl tphz /tpzh S1 Open 6 V LOD CIRCUIT tw Timing Input Input VOLTGE WVEFORMS tsu th Data Input Input tplh VOLTGE WVEFORMS 2 V 0.8 V tr tf 2 V tphl 0.8 V VOH VOL Control (low-level enabling) Waveform 1 S1 at 6 V (see Note B) Waveform 2 S1 at (see Note B) tpzl tpzh tplz tphz VOL + 0. VOL VOH VOH 0. VOLTGE WVEFORMS VOLTGE WVEFORMS NOTES:. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. ll input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 0 Ω, tr 2. ns, tf 2. ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 6303 DLLS, TEXS 726
PRMETER MESUREMENT INFORMTION tphl1 tplh1 tphl2 tplh2 tphl3 tplh3 tphl4 tplh4 Y tphl tplh tphl6 tplh6 tphl7 tplh7 tphl8 tplh8 tphl9 tplh9 tphl10 tplh10 NOTES:. skew, tsk(o), is calculated as the greater of: The difference between the fastest and slowest of tplhn (n = 1, 2, 3, 4,, 6, 7, 8, 9, 10) The difference between the fastest and slowest of tphln (n = 1, 2, 3, 4,, 6, 7, 8, 9, 10) B. Pulse skew, tsk(p), is calculated as the greater of tplhn tphln (n = 1, 2, 3, 4,, 6, 7, 8, 9, 10). C. Process skew, tsk(pr), is calculated as the greater of: The difference between the fastest and slowest of tplhn (n = 1, 2, 3, 4,, 6, 7, 8, 9, 10) across multiple devices under identical operating conditions The difference between the fastest and slowest of tphln (n = 1, 2, 3, 4,, 6, 7, 8, 9, 10) across multiple devices under identical operating conditions Figure 2. Waveforms for Calculation of t sk(o), t sk(p), t sk(pr) 6 POST OFFICE BOX 6303 DLLS, TEXS 726
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