Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology

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Voltage IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 02, 2014 ISSN (online): 2321-0613 Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology Sunil R. Gupta 1 Pratik P. Shah 2 1, 2 Dept. of Electronics & Communication 1, 2 SSESGI(Gujarat Technological University), Rajput, Kadi, India Abstract---In this paper voltage mode sense amplifier, current latch sense amplifier and c urrent sense amplifier is analyzed and simulated with and without MTCMOS technique in a 45nm process technology using Ngspice circuit simulator. When density of memory is increased, the bit line capacitance is also increases and due to that, it limits the speed of voltage sense amplifier. To overcome this problem current sense amplifier is used, which is not dependent on bit line capacitance. This paper shows that delay time is reduced in current sense amplifier compare to voltage mode sense amplifier and current latch sense amplifier but power consumption is increased. MTCMOS technique is used to reduce power dissipation. Keywords: SRAM, Sense amplifier, Cross coupled Voltage mode sense amplifier, Current latched sense amplifier, Current sense amplifier due to process variations. The initial voltage difference at the output nodes created by bit-line voltage difference may not result in the flipping of the cross-coupled inverters in the right direction if there is sufficient trip point voltage. I. INTRODUCTION SRAM is used at where high speed and high performance microprocessor is used. Simultaneously SRAM is also used at where low power is required. When number of SRAM cell is increased to store large number of data, it becomes necessary to use sense amplifier. Sense amplifiers detect the data being read by sensing a small differential voltage swing on the bit-lines rather than waiting for a full rail-to-rail swing. Depending on the performance and power requirements, it s very important for the sense amplifiers to operate fast and do so while burning a minimum amount of power. Conventional Voltage Sense Amplifiers need a minimum amount of differential voltage to be developed on the bit-lines for reliable operation. In digital electronics, the power delay product is a figure of merit correlated with the energy efficiency of a logic gate or logic family. Fig. 1: Cross-coupled voltage mode SA [10] SAEN 1 800m SL 600m 400m II. VOLTAGE MODE SENSE AMPLIFIER Fig.1 shows the schematic of Cross-coupled voltage mode SA. M1 and M2 are the access transistors, whereas M3-M6 forms cross-coupled inverters. When SAEN is low, M1 and M2 are turned ON and voltage on BL and BLB will be transferred to SL and SLB respectively. Due to positive feedback, higher voltage level goes to VDD and other level goes towards zero. In the basic cross-coupled SA, the nodes SL and SLB are input and output terminals simultaneously at one time. Hence, the circuit is not being connected directly to the bit line since the circuit would attempt to discharge the bit line capacitance during the decision phase and would increase delay and power [6]. The NMOS devices M3 and M4 in the cross coupled inverter pair as well as the enable device M7 need to be sized for speed since they are in the critical discharge path. Speed is improved if the M7 device is sized higher. But higher widths on M3 and M4 are very important 200m 0 SLB -200m 0 20p 40p 60p 80p 100p 120p 140p 160p 180p 200p Time(s) Fig. 2: Simulation result of cross coupled VSA MTCMOS technique can be applied for reducing leakage currents in low voltage circuit in standby mode is based on using two different types of transistor (both NMOS and PMOS ) with two different threshold voltages in the circuit. Low V T transistors are used to design logic gates where switching speed is essential, whereas High V T transistors are used to effectively isolate logic gates in stand by and to prevent leakage dissipation. All rights reserved by www.ijsrd.com 229

Voltage(V) Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology III. CURRENT LATCH SENSE AMPLIFIER Fig.3: VSA using MTCMOS Technique The working of Voltage mode sense amplifier using MTCMOS circuit is same as Voltage mode sense amplifier circuit but the difference is that M8 and M9 are high V T MOSFET and rest of MOSFET (M1-M7) are low V T MOSFET. When SAEN is low, M1 and M2 are turned ON and voltage on BL and BLB will be transferred to SL and SLB respectively. When SAEN is low at that time SLEEP is high so M8 is turn off but due to inverted SLEEP is given to M9, it is also turn off and no leakage current is flow. Hence due to reduction of leakage current, power consumption is also decreased. Fig.5: Current latch sense amplifier [9]. The current flow of the differential input transistors M1 and M2 controls the serially connected latch circuit. This current latched SA is faster than conventional cross coupled SA. During reset phase when SAEN=0V, the output nodes of the SA (O1 and O2) are reset to VDD through the reset transistors M6 and M9. During evaluation phase when SAEN=VDD, M3 turns ON and the input transistors M1 and M2 starts to discharge O1 and O2 node voltages to GND. Fig. 6 shows simulation results of current latched sense amplifier trying to read data of memory cell containing logic 1. When word line WL is high to access the memory cell, BLB starts to discharge from VDD and BL remains high. After SAEN is asserted, cross coupled inverters amplify small differential voltage. 1.2 1.0 BL 0.8 BLB 0.6 O2 0.4 SAEN 0.2 V OUT O1 V OUTB 0.0 0 20p 40p 60p 80p 100p 120p 140p 160p 180p 200p Time(s) Fig.4: Simulation result of VSA using MTCMOS Technique Fig.6: Simulation result of CLSA All rights reserved by www.ijsrd.com 230

Fig.7: CLSA using MTCMOS technique Fig.9: Current sense amplifier [8]. The operating current of the sense amplifier is determined by the sizes of devices M5-M8. At the end of the pre charge phase, pre charge and equalization devices M11- M13 are turned OFF. During the evaluation phase, Y ael is pulled low and current is immediately transported to the nodes A and B through the drains of M3 and M4. Fig.8: Simulation result of CLSA using MTCMOS technique IV. CURRENT SENSE AMPLIFIER The current sense amplifier operates in two phases: pre charge and evaluate. During the pre-charge phase, the bitlines are pre charged through pre charge devices connected to the bit-lines. The Output nodes SA and SA# are also pre charged high through M11 and M12 PMOS devices. Fig.10: Simulation result of CSA All rights reserved by www.ijsrd.com 231

This causes nodes Int and A to go high causing M2 to be cut off. Therefore, the path from the low going BL# to ground is cut off, reducing the voltage swing on it. This scheme enhances the speed of the sense amplifier further due to the fact that there is a flow of bias current before the sense amplifier is actually enabled. Fig.11 shows the Current sense amplifier using MTCMOS technique. In CSA using MTCMOS technique high threshold voltage MOSFET is used so that power dissipation is reduced. V. PERFORMANCE SUMMARY OF SA All three types of sense amplifiers are simulated in 45nm technology using NGSPICE. Table 1, shows performance summary of these sense amplifiers. Fig. 11: Current sense amplifier using MTCMOS technique The difference in current flowing through A and B will be equal to the cell current. The sense amplifier is enabled two-inverter delay after the SAen is pulled high during which bias current flows through two legs of the sense amplifier, while M14 keeps the output equalized. After this two inverter delay, M14 is disabled and the differential current causes a differential voltage to be developed at SA and SA#. This differential voltage is then amplified to CMOS logic levels by the high-gain positive feedback cross-coupled inverters formed by M5-M8. The sensing delay is relatively insensitive to bit-line capacitance as the operation is not dependent on the development of a differential voltage across the bit-lines. The CSA have low voltage swing on bit-lines. This is because the cross coupled PMOS pair M1 and M2 cuts off the discharge path to ground for both bit-lines. If BL is high and BL# is low. Fig.12: Simulation result of CSA using MTCMOS technique Table1. Comparison of different types of SA VI. CONCLUSION Cross Coupled VSA, Current latched SA and Current SA is analyzed and simulated in 45nm CMOS technology using Ngspice. From the simulation result, Current Sense amplifier (CSA) is the best choice with minimum delay of 30.65 ps but power consumption 362.28µw which is higher than VSA and CLSA. Power dissipation is reduced by using MTCMOS Technique in VSA, CLSA and CSA. PDP is also decreased by using MTCMOS Technique. REFERENCES [1] J. Zhu, N. Bai, J. Wu et al., A Review of Sense Amplifier For Static Random Acess Memory, IETE Journal,Vol.30,Issue 1, Jan-Feb 2013 [2] Gaytri. A.V, D. Sujatha, et al., Analysis of New Current Mode Sense Amplifier IEEE 2012 [3] L. Zhang, C.Wu, Y. Ma et al., Leakage Power Reduction Techniques of 55 nm SRAM Cells, IETE Journal,Vol.28,Issue 2, Mar-Apr 2011 [4] Z. Wang, et al., A Robust Design of SRAM Sense Amplifier for Submicron Technology, IEEE 2010. [5] J.Yeung and H. Mahmoodi, "Robust Sense Amplifier under Random Dopant Fluctuation in CMOS Technologies," IEEE 2006. [6] M. Saibal, A. Ray Chowdhury, M. Hamid, and R. Kaushik, "Leakage Current Based Stabilization Scheme for Robust Sense Amplifier Design for Yield All rights reserved by www.ijsrd.com 232

Enhancement in Nano-scale SRAM," IEEE 14th Asian Test Symopsium 2005 (Feb 2005), pp. 183-192. [7] B. Wicht, Thomas Nirschl and Doris Schmitt- Landsiedel, Yield and Speed Optimization of a Latch- Type Voltage Sense Amplifier, IEEE Journal of Solid- State Circuits, Vol 39, No 7, July 2004. [8] Manoj Sinha, et al, " High-Performance and Low- Voltage Sense Amplifier techniques for sub 90nm SRAM," IEEE 2003. [9] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, A Current- controlled Latch Sense Amplifier and a Static Power-saving Input Buffer for Low-Power Architecture, IEEE Journal of Solid-State Circuits, vol. 28, pp. 523 527, Apr. 1993. [10] E.Seevinck, et al., Current-mode techniques for highspeed VLSI circuits with application to CSA for CMOS SRAM, IEEE Journal of Solid-State Circuits,Vol.26, No 4, pp 525-536,April 1991. ACRONYMS SRAM Static random access memory SA Sense amplifier VSA Voltage sense amplifier CLSA Current latch sense amplifier CSA Current sense amplifier MTCMOS Multi threshold Complementary Metal Oxide Semiconductor PDP Power delay product. All rights reserved by www.ijsrd.com 233

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