Broadcom BCM43224KMLG Baseband/MAC/Radio All-in-One Die SMIC 65 nm Process Structural Analysis 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
Structural Analysis Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc. 2012 all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. SAR-1212-201 24115CKWM Revision 1.0 Published: December 10, 2012
Table of Contents Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Layout 3.1 Layout Overview 4 Process Analysis 4.1 General Device Structure 4.2 Dielectrics 4.3 Metallization 4.4 Vias and Contacts 4.5 Capacitor 4.6 Logic Transistors and Polysilicon 4.7 Isolation 4.8 Wells and Substrate 5 SRAM Cell Analysis 5.1 Overview 5.2 6T SRAM Schematic 5.3 6T SRAM Analysis Plan View 5.4 Cross-Sectional 6T SRAM Analysis 5.5 8T SRAM Analysis 6 Materials Analysis 6.1 Overview 6.2 Dielectrics 6.3 Metals
Structural Analysis 7 Critical Dimensions 7.1 Package, Die, and Standard Logic Cell Size 7.2 Dielectrics 7.3 Metals 7.4 Vias and Contacts 7.5 Transistors 7.6 Isolation 7.7 Wells and Substrate 7.8 SRAM Transistors 8 References 9 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package X-Ray 2.1.4 Die Photograph 2.1.5 Die Markings 2.1.6 Die Photograph at Polysilicon Layer Annotated with SRAM Memory Locations 2.1.7 Die Photograph at Polysilicon Layer Annotated with Analysis Sites 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Bond Pads 2.2.6 Inductor 1 of 41 2.2.7 Inductor 2 of 41 2.2.8 Inductor 3 of 41 2.2.9 Inductor 4 of 41 2.2.10 Inductor 5 of 41 2.2.11 Inductor 6 of 41 2.2.12 Inductor 7 of 41 3 Layout 3.1.1 Logic Transistor Plan View 3.1.2 Minimum NAND Cell Size Plan View 3.1.3 Polysilicon Resistor Plan View 4 Process Analysis 4.1.1 General Structure 4.1.2 Die Thickness 4.1.3 Die Edge 4.1.4 Die Seal 4.2.1 General View of Dielectrics 4.2.2 SEM of Passivation and Interlevel Dielectric ILD 7 4.2.3 TEM of Passivation 4.2.4 TEM of ILD 7 4.2.5 SEM of ILD 6-4 and ILD 6-3 4.2.6 SEM of ILD 6-2 and ILD 6-1 4.2.7 TEM of ILD 5 4.2.8 TEM of ILD 4 4.2.9 TEM of ILD 3 4.2.10 TEM of ILD 2 4.2.11 TEM of ILD 1 4.2.12 TEM of PMD
Overview 1-2 4.3.1 SEM of Metal 8 4.3.2 TEM of Layer Between Passivation 1 and Metal 8 4.3.3 TEM of Metal 8 Barrier 4.3.4 SEM of Minimum Width and Minimum Pitch Metal 8 4.3.5 SEM of Metal 7 4.3.6 TEM of Metal 7 Liner 4.3.7 SEM of Metal 6 4.3.8 TEM of Metal 6 Liner 4.3.9 SEM of Metal 5 4.3.10 TEM of Metal 5 Minimum Pitch 4.3.11 SEM of Metal 4 4.3.12 SEM of Metal 4 Liner 4.3.13 TEM of Metal 3 4.3.14 TEM of Metal 3 Liner 4.3.15 SEM of Metal 3 Minimum Pitch 4.3.16 TEM of Metal 2 4.3.17 TEM of Metal 1 Minimum Width 4.3.18 TEM of Metal 1 Liner 4.3.19 SEM of Metal 1 Minimum Pitch 4.4.1 SEM of Via 7s Mínimum Pitch 4.4.2 SEM of Pitch Via 6s 4.4.3 SEM of Pitch Via 5s 4.4.4 SEM of Via 4s 4.4.5 TEM of Via 3s 4.4.6 SEM of Via 2s 4.4.7 TEM of Via 1s 4.4.8 STEM Dark Field of Via 1 Linescan Location 4.4.9 TEM Contact to Silicon 4.4.10 TEM of Contact Plug Top 4.4.11 TEM Contact Plug Bottom 4.4.12 TEM Contact to Polysilicon 4.4.13 Contact in SRAM Array 4.5.1 SEM Interdigitized Fingers Capacitor 4.5.2 Close-Up SEM Interdigitized Fingers Capacitor 4.5.3 SEM Interdigitized Fingers Capacitor Along the Finger 4.5.4 SEM Interdigitized Fingers Capacitors 4.5.5 SEM of Likely MOS Capacitor Array 4.6.1 SEM Minimum Gate Length Logic NMOS Transistor 4.6.2 SEM Minimum Gate Length Logic PMOS Transistor 4.6.3 TEM Minimum Gate Length Logic Transistors 4.6.4 TEM Close-Up of Minimum Gate Length Logic Transistor 4.6.5 TEM Logic Transistor Gate Oxide 4.6.6 TEM of Minimum Contacted Gate Pitch 4.6.7 SEM Minimum Polysilicon Pitch 4.6.8 Logic Transistor Width
Overview 1-3 4.6.9 TEM Wide Gate Transistor 4.6.10 TEM Thick Gate Oxide 4.6.11 Polysilicon Resistor 4.7.1 TEM Minimum STI Width in the Logic Region 4.7.2 TEM of STI Recess 4.7.3 TEM of STI Structure Covered by Polysilicon 4.7.4 TEM Close-Up of the STI Edge 4.7.5 TEM of STI Under Polysilicon 4.7.6 SEM of STI in the SRAM Region 4.8.1 SRP Carrier Concentration in P-Well 4.8.2 SRP Carrier Concentration in N-Well 4.8.3 SCM of P-Well and N-Well 5 SRAM Cell Analysis 5.2.1 6T SRAM Schematic 5.3.1 SRAM at Metal 4 Layer 5.3.2 SRAM at Metal 3 Layer 5.3.3 SRAM at Metal 2 Layer 5.3.4 SRAM at Metal 1 Layer 5.3.5 SRAM at Contact and Polysilicon Layers 5.3.6 SRAM at Substrate Layer 5.4.1 6T SRAM NMOS Cross-Sectional View Perpendicular to Wordlines 5.4.2 TEM NMOS Transistors at 6T SRAM 5.4.3 TEM NMOS Transistor Close-Up 5.4.4 6T SRAM PMOS Cross-Sectional View Perpendicular to Wordlines 5.4.5 TEM PMOS Transistor 5.4.6 TEM PMOS Transistor Close-Up 5.4.7 6T SRAM Cross-Sectional View Parallel to Wordline 5.5.1 8T SRAM Cell Schematic 5.5.2 8T SRAM Array at Polysilicon Layer 6 Materials Analysis 6.2.1 TEM-EDS Spectrum of Passivation 6.2.2 TEM-EDS Spectrum of ILD 7-4 and ILD 7-3 6.2.3 TEM-EDS Spectrum of ILD 7-2 and ILD7-1 6.2.4 TEM-EDS Spectrum of ILD 6-4 and ILD 6-3 6.2.5 TEM-EDS Spectrum of ILD 6-2 and ILD 6-1 6.2.6 TEM-EDS Spectrum of ILD 5 6.2.7 TEM-EDS Spectrum of ILD 4 6.2.8 TEM-EDS Spectrum of ILD 3 6.2.9 TEM-EDS Spectrum of ILD 2 6.2.10 TEM-EDS Spectrum of ILD 1 6.2.11 TEM-EDS Spectrum of PMD 5, PMD 4, and PMD 3 6.2.12 TEM-EDS Spectrum of PMD 2 and PMD 1 6.3.1 TEM-EDS Spectrum of Metal 8 Bulk 6.3.2 TEM-EDS Spectrum of Metal 8 Barrier Layer
Overview 1-4 6.3.3 TEM-EDS Spectrum of Metal 1 Liner 6.3.4 TEM-EDS Linescan Through Via 1 Fill and Via 1 Liner 6.3.5 TEM-EDS of Contact Liner 6.3.6 TEM-EDS Spectrum of Gate Silicide 6.3.7 TEM-EDS Spectrum of S/D Silicide 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Die Summary 1.6.1 Process Summary 4 Process Analysis 4.2.1 Dielectric Thicknesses 4.3.1 Metallization Vertical Dimensions 4.3.2 Metallization Horizontal Dimensions 4.4.1 Via and Contact Dimensions 4.6.1 Logic Transistors Horizontal Dimensions 4.6.2 Logic Transistors Vertical Dimensions 4.7.1 STI Critical Dimensions 4.8.1 P-Well and N-Well Impurity Concentrations and Depths 5 SRAM Cell Analysis 5.4.1 6T SRAM Transistors Dimensions 7 Critical Dimensions 7.1.1 Package, Die, and Standard Logic Cell Size 7.2.1 Dielectric Thicknesses 7.3.1 Metallization Vertical Dimensions 7.3.2 Metallization Horizontal Dimensions 7.4.1 Via and Contact Dimensions 7.5.1 Transistor Horizontal Dimensions 7.5.2 Transistor Vertical Dimensions 7.6.1 STI Critical Dimensions 7.7.1 N-Well and P-Well Impurity Concentrations and Depths 7.8.1 SRAM Transistor Dimensions
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