Power Supply Unit (550W)

Contents Power Supply Unit (550W) Chapter 3.1 GENERAL DESCRIPTION...3.1-1 APPLIED VOLTAGE...3.1-2 INPUT CURRENT...3.1-2 DC OUTPUT...3.1-3 VOLTAGE DROPOUT...3.1-4 OUTPUT ISOLATION...3.1-4 OVERLOAD/UNDERLOAD PROTECTION...3.1-4 BLEED OFF...3.1-4 INTERNAL FUSES...3.1-4 THE POWER GOOD SIGNAL...3.1-5 Fan Out...3.1-6 OUTPUT VOLTAGE SEQUENCE...3.1-6 NO LOAD OPERATION...3.1-7 LOAD SHARING...3.1-7 STATE-OF-HEALTH (SOH) INDICATOR...3.1-7 THEORY OF OPERATION...3.1-7 A2 BOARD...3.1-7 Input Surge Limiting...3.1-7 Input Voltage Range Selection...3.1-7 Input Overvoltage Protection...3.1-8 Precharge...3.1-8 Transformer T1...3.1-8 A1 BOARD...3.1-8 A3 BOARD...3.1-8 Regulation...3.1-8 Overvoltage Protection (OVP)...3.1-8 Overcurrent Protection (OIP)...3.1-9 Power Good Signal...3.1-9 LED Signal...3.1-9 24 V Sequencing...3.1-9 +5 V Discharge...3.1-9 EDGE CONNECTOR PINOUT...3.1-10 BOARD INTERCONNECTION DIAGRAM...3.1-11 3.1-i

SCHEMATIC DIAGRAMS...3.1-11 3.1-ii

Contents Chapter 3.1 Power Supply Unit (550W) GENERAL DESCRIPTION 3.1-1

This chapter describes the 550W (input power rating) system power supply unit (PSU) in some 5682 Interactive Terminals and 5663 Account Services Terminals. The PSU provides the following dc supplies: l +5 V l +12 V l -12 V l +24 V. Provision is made on the PC bus board for a possible future supply of -5 V dc derived from the -12 V output of the PSU (refer to Chapter 2.1). The system PSU is a switch mode power supply unit. An edge connector (P1) on the underside of the PSU carries the ac input to the PSU and all of its output signals. Two signals are available for external monitoring of power supply health: a Power Good signal indicating an input or output failure and an LED signal indicating a failure on one or more of the output voltages. On the front of the power supply unit, a small viewing hole permits a state-ofhealth indicator LED to be seen. This indicator LED is driven by the same signal that is made available on P1. A 70 CFM (cubic feet per minute), 24 Vdc cooling fan is incorporated in the top of the power unit. If the fan fails, an overtemperature switch turns the supply off. Automatic restart occurs after cooling. APPLIED VOLTAGE The power supply unit incorporates an automatic voltage ranging circuit to configure the unit for either, 115 Vac nominal (90 to 136 Vac) or 230 Vac nominal (198 to 257 Vac) input. INPUT CURRENT The maximum input current under any combination of normal operating conditions is as follows: Input Voltage Range (Vrms) Frequency Range (Hz) Maximum Input Currenct (A) 90-136 47-63 9.0 198-257 47-63 4.5 Input inrush current is less than 150 A peak at 257 Vac input repetitive (warm start), measured at 20 deg. C ambient temperature. 3.1-2

DC OUTPUT The following table defines the dc output: Performance Requirement DC1 DC2 DC3 DC4 UNITS Nominal Voltage +5.1 +12-12 +24 Vdc Current (Static) - Max 21 5 0.8 9*** Adc - Min 4 0.004 0 0 Adc Current (Dynamic) N/A N/A (for 12s additional) 3.0 Adc (for 5s additional) 4.0 Adc * Total Voltage Drift Minimum Voltage 4.95 11.52-13.2 22.8 Vdc Maximum Voltage 5.25 12.6-10.92 25.2 Vdc ** Ripple and Noise Deviation (to 1 MHz) 50 120 120 240 mv(p-p) Overshoot (Resistive Load) 10 10 10 10 % Overvoltage Protection Absolute Maximum Voltage 7.0 N/A N/A N/A Vdc Efficiency (Minimum at full load) ------------------------------ 70------------------------------ % Maximum Switch-On Time ----------------------------- 500------------------------------ msec (At maximum load) Maximum Output Power ----------------------------- 393------------------------------ w NOTE: * The total voltage drift consists of the following: line regulation, load regulation (with all load variations), dynamic load, temperature warm-up drift, ripple and noise, interaction and manufacturing tolerances. NOTE: ** Ripple and noise are measured differentially at the load using loads that are each shunted by at least one 0.1 uf ceramic disc capacitor. The load should should be attached to the power supply by at least one foot of cable. NOTE: *** Maximum average current is 13 amps for periods less than 5 seconds with a repetition rate of 30 seconds. The following figure shows a typical output current waveform under dynamic load conditions. 3.1-3

i(a) 21.7 18.2 0.7 0 0.18 0.29 0.66 t (msec) 01980301.002 VOLTAGE DROPOUT An input voltage change to 50% of nominal for 1/2 cycle in 10 seconds will not cause the outputs to exceed the specified tolerance limits. OUTPUT ISOLATION The secondary winding and circuit for the 24 V output is independent from those of the +5 V, +12 V, and -12 V. OVERLOAD/UNDERLOAD PROTECTION The PSU is capable of being operated with any combination of one output at overload and the rest at maximum load condition, or any combination of output current underload conditioning without incurring damage. It will also survive an indefinite short on any of the dc outputs. BLEED OFF The bleed off time down to 10% of the initial voltage, does not exceed the following: l l DC voltages less than 7 V - 50 seconds Other - 60 seconds. INTERNAL FUSES Two fuses exist within the PSU, both located on the A2 board. These are: l F1, 250V 10A (ceramic) line fuse, part number 007-3040023 l F2, 250V 5A (glass) inverter fuse, part number 007-3040020. 3.1-4

THE POWER GOOD SIGNAL Power Good Signal Output Voltage Vn Vm t ovs t don t t ovs doff 01980301.003 t son Where, Vn Nominal Voltages (+5V, +12 V, -12 V, +24 V) Vm Minimum Voltages (+4.5 v, +10.8 V, -10.4 V, 21.8 V) tson Switch On Time (500 ms maximum) tdon Delay Turn-On (100 ms < tdon < 500ms) tdoff Delay Turn-Off (1 ms minimum) tovs Output Voltage Sequencing (300 ms maximum) The power good signal is reset by the power supply unit to indicate that the dc outputs and the line voltage are present and within their specified range. The signal is distributed to the processor board via the PC bus board, and to the SDC 40-column and 80-column printers via the dc distribution board. The signal is generated when the power supply has been switched off for at least 1 second, and is then switched on again without any failures. The signal is TTL compatible, with logic low indicating a failure condition, and logic high indicating normal condition. When the power supply has been switched off or the mains input has failed the power good signal will go low at least 1 ms before any of the output voltages fall below their normal regulated range. This delay must be measured with the PSU in normal operation, with maximum load and minimum line voltage. The power good signal must go low if one or more of the dc outputs drops below their minimum sense level shown in the table below. the signal must go high between 200 ms and 500 ms after all the dc outputs have reached their normal regulated range. 3.1-5

On power up, the power good signal is held low until all the output voltages reach their minimum sense levels as shown in the following table: V Nominal V Minimum V Maximum +5.1 4.75 5.5 +12 +10.8 13.2-12 -10.4 13.2 +24 +21.8 26.4 The turn on delay for the power good signal is between 100 ms and 500 ms. Fan Out The power good signal will sink a minimum of 30 ma with an open collector transistor output. OUTPUT VOLTAGE SEQUENCE With at least the minimum specified loading applied, the output voltages will track within 300 ms of each other whenever the power supply is switched on. The +5 V and ±12 V will stabilize and be within tolerance before the 24 V output is enabled. Additionally, if +5 V or ±12 V fail for any reason or go outside the sense levels shown in the table in the section "Power Good Signal", the 24 V will be disabled. The +5 V output should reach its minimum output level of +4.95 V in a rise time of less than 150 ms, and should be monotonic. At switch-off the +5 V should decay as shown in the following figure and the other voltages should decay as shown in the figure in the "Power Good Signal" section. 3.1-6

Where, t1 = NVRAM storage - this interval must be no less than 1 ms. t2 = Loss of logic control - this interval must be no more than 3 ms. NOTE: Decay measured with capacitive load of 200 uf. NO LOAD OPERATION Damage or hazardous conditions will not occur if primary voltage is applied to the PSU when no loads are connected. LOAD SHARING The maximum load current on the 24 Vdc output is 10.5 A when the +5 Vdc output current is limited to not more than 13.8 A. STATE-OF-HEALTH (SOH) INDICATOR The SOH indicator LED is visible through a viewing hole in the front of the PSU. The indication is green only when all voltages are within their specified range. A slow flashing red indicates that a short circuit exists on an external dc circuit supplied by the PSU. THEORY OF OPERATION Refer to the block, assembly and schematic diagrams on fold-out pages FO-1 to FO-10 while reading this description. The power supply unit contains three electronics boards housed in a two piece chassis. It uses a Forward Converter topology operating at 65 khz to produce four fully regulated dc output voltages from the line voltage ac input. The outputs: +5 V/21 A, +12 V/5A, (8 A max for 12 seconds), +24 V/10.5 A (13 A max for 5 seconds) -12 V/0.8 A, must not exceed 400 W continuous. Overvoltage protection is provided for the +5 V and +12 V outputs. Overcurrent and short circuit protection are provided for all outputs. A2 BOARD The "front end" of the power supply is housed on the A2 board. Line voltage is applied to the input/output connector on the A1 board and reaches the A2 board through the A1-J4/A2-P1 connectors. Line voltage is applied to the EMI filter (L1 and C1-C5) and bridge rectifier CR1 to be stored on bulk capacitors C7 and C8. Input Surge Limiting R1 and R2 provide input current surge limiting. Input Voltage Range Selection Input voltage range selection is provided by K1. At low range (90-136 Vac) K1 is energized by Q3, closing K1 contacts, providing voltage doubling on to C7 and C8. At high range, a latch, consisting of Q1 and Q2, is activated preventing Q3 from energizing K1. 3.1-7

Input Overvoltage Protection If K1 fails, safety input overvoltage protection is provided by gas-filled discharge devices SG1 and SG2. Precharge A precharge circuit (R22-R24 and CR8) provides starting current for the Pulse Width Modulator (PWM) control circuit (see A3 board). Transformer T1 Transformer T1 drives the power FETs Q4-Q7 to provide regulated power to the power transformer and the four outputs (see A1 board). This also provides the power for all internal control and interface circuits. A1 BOARD After the supply has started, auxiliary power is provided to the control circuits through the power transformer T1 supplying L1 and C2. The main control loop is closed around the 5 V output also providing semi-regulated voltages for the remaining three outputs. The -12 V output is regulated by a three terminal linear regulator which also provides current limiting for that output. The 24 V and +12 V outputs are regulated with magnetic amplifiers controlling SR1 and SR2 respectively. Current limiting is accomplished on the +5 V and +12 V outputs by current transformers T2 and T4 respectively. The 24 V output has two-stage current limiting: overcurrent protection is provided by T3 and an undervoltage sense on the A3 board (which ultimately triggers the OVP latch), short circuit protection is provided through the overcurrent latch on the A3 board. During turn off, the +5 V output is discharged by Q1 which is driven by an undervoltage sense circuit on the A3 board. A3 BOARD The A3 board houses the control and interface circuits. Regulation The pulse width modulator U1 regulates the +5 V output at the remote sense point, using the error signal fed through optocoupler U2. Potentiometer R58 adjusts the +5 V output voltage. Overvoltage Protection (OVP) The OVP latch, consisting of Q1 and Q2, is triggered by optocoupler U3 which feeds a latching signal from the output control circuits under any of the following conditions: l l +5 V or +12 V output voltage reaches ovp trip point The 24 V output drops below the undervoltage trip point. 3.1-8

Overcurrent Protection (OIP) The timed reset overcurrent latch consisting of U5, Q3, and Q4 and surrounding circuit, is triggered by current sense comparator U4 which senses the +5, +12, and 24 V output currents. Once tripped, the oip latch will reset in about six seconds. A second stage current limit is built into the 24 V output, offering protection against a prolonged overcurrent condition. This will limit the 24 V output current to about 14.5 A at which the 24 V undervoltage latch is tripped. Power Good Signal The power good signal is developed by sensing the bulk capacitor voltage as it is applied to T1 and divided by the turns ratio to the 5 V output winding. This voltage is stored on C14 and compared to a precision reference by U6. The output signal, driven by Q6, can be triggered by a low voltage on C14 and/or a voltage failure condition on any output. Potentiometer R36 adjusts the timing of the power good signal. LED Signal The LED signal is driven by U15 and responds to output voltage failure and tracks the condition of the internal LED CR35. Whenever the signal is pulled low (-12 V), the internal LED is red, indicating a failure. Within 0.8 seconds after the LED turns red, a 24 V undervoltage latch occurs. 24 V Sequencing A voltage failure on the +5 V, +12 V, or -12 V output opens relay K1 (A1 board), which is driven by Q12, disabling the 24 V output. This also triggers the 24 V undervoltage latch which latches the supply until ac input voltage is removed and re-applied. the output voltages are detected for undervoltage and overvoltage by U12 and U13. The outputs of these comparators control the 24 V relay K1 and undervoltage latch, the red/green LED and the power good signal. +5 V Discharge When a +5 V undervoltage condition (+4.5 V) is detected, Q11 provides the drive signal for the +5P V crowbar which applies a short circuit, discharging the output to +0.4 V within 3ms. 3.1-9

EDGE CONNECTOR PINOUT 3.1-10

BOARD INTERCONNECTION DIAGRAM SCHEMATIC DIAGRAMS The following fold-out pages FO-1 to FO-10 give the block diagram and schematics of the system dc power supply unit. 3.1-11

3.1-12