6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 25 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS inverter with current-source pull-up 3. Complementary MOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, 5.3
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-2 Key questions What are the key design trade-offs of the NMOS inverter with resistor pull-up? How can one improve upon these trade-offs? What is special about a CMOS inverter?
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-3 1. NMOS inverter with resistor pull-up (cont.) V = =V DS V OH =V MAX = R I R slope= A v (V M ) I D V M = CL V OL =V MIN V T V M VDD =V GS V IL V IH Noise margins: NM L = V IL V OL = V M V MAX V M A v (V M ) V MIN 1 NM H = V OH V IH = V MAX V M (1 A v (V M ) ) V MIN A v (V M ) Need to compute A v (V M ).
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-4 Small-signal equivalent circuit model at V M (transistor in saturation): R G v in v gs gm v gs D r o v out - - S - v in gm v in r o //R v out - - v out = g m v in (r o //R) Then: Then: A v = v out v in = g m (r o //R) g m R A v (V M ) = g m (V M )R From here, get NM L and NM H using above formulae.
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-5 Dynamics C L pull-down limited by current through transistor [will study in detail with CMOS] C L pull-up limited by resistor (t PLH RC L ) pull-up slowest : LO HI R C L : HI LO : HI LO R C L : LO HI pull-down pull-up
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-6 Inverter design issues: noise margins A v R RC L slow switching g m W big transistor (slow switching at input) Trade-off between speed and noise margin. During pull-up, need: high current for fast switching, but also high resistance for high noise margin. use current source as pull-up.
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-7 2. NMOS inverter with current-source pull-up I-V characteristics of current source: i SUP v SUP i SUP I SUP 1 r oc _ v SUP Equivalent circuit models: i SUP v SUP I SUP roc r oc _ large-signal model small-signal model high current throughout voltage range: i SUP I SUP high small-signal resistance, r oc.
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-8 NMOS inverter with current-source pull-up: i SUP =I D load line V GS = i SUP I SUP V GS = C L V GS =V T V DS Transfer characteristics: VDD V T High r oc high noise margin
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-9 Dynamics: i SUP i SUP : LO HI C L : HI LO : HI LO C L : LO HI pull-down pull-up Faster pull-up because capacitor charged at constant current.
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-1 PMOS as current-source pull-up I-V characteristics of PMOS: S G IDp D -IDp -IDp saturation VSGp VSGp=-VTp VSDp -VTp VSGp Note: enhancement-mode PMOS has V Tp <. In saturation: I Dp (V SG V Tp ) 2
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-11 Circuit and load-line diagram of inverter with PMOS current source pull-up: -I Dp =I Dn PMOS load line for V SG = -V B V B C L Transfer function: NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation VDD V Tn
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-12 Noise margin: compute V M = = compute A v (V M ) At V M both transistors saturated: I Dn = W n 2L n µ n C ox (V M V Tn ) 2 And: I Dp = W p 2L p µ p C ox ( V B V Tp ) 2 Then: I Dn = I Dp V M = V Tn µ p W p L p µ n W n L n ( V B V Tp )
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-13 Small-signal equivalent circuit model at V M : S2 v sg2 = g mp v sg2 r op - G2 D2 D1 G1 v in v gs1 g mn v gs1 r on v out - - - S1 v in gmn v in r on //r op v out - - A v = g mn (r on //r op )
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-14 NMOS inverter with current-source pull-up allows fast switching with high noise margins. But... when =, there is a direct current path between supply and ground power consumption even if inverter is idling. -I Dp =I Dn PMOS load line for V SG = -V B V B :LO :HI C L Would like to have current source that is itself switchable, i.e., it shuts off when input is high CMOS!
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-15 Screen shots of NMOS inverter transfer characteristics: NMOS inverter with resistor pull-up NMOS inverter with current source pull-up
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-16 3. Complementary MOS (CMOS) Inverter Circuit schematic: C L Basic operation: = = V GSn =<V Tn NMOS OFF V SGp = > V Tp PMOS ON = = V GSn = >V Tn NMOS ON V SGp =< V Tp PMOS OFF No power consumption while idling in any logic state.
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-17 Output characteristics of both transistors: I Dn -I Dp V GSn V SGp V GSn =V Tn V SGp =-V Tp V DSn V SDp Note: = V GSn = V SGp V SGp = = V DSn = V SDp V SDp = I Dn = I Dp Combine into single diagram of I D vs. with as parameter.
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-18 I D - C L no current while idling in any logic state. Transfer function: NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation NMOS triode PMOS cutoff V Tn V Tp rail-to-rail logic: logic levels are and high A v around logic threshold good noise margins
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-19 Transfer characteristics of CMOS inverter in WebLab:
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-2 Key conclusions In NMOS inverter with resistor pull-up: trade-off between noise margin and speed. Trade-off resolved using current-source pull-up: use PMOS as current source. In NMOS inverter with current-source pull-up: if = HI, power consumption even if inverter is idling. Complementary MOS: NMOS and PMOS switch alternatively no power consumption while idling rail-to-rail logic: logic levels are and high A v around logic threshold good noise margins