Faculty of Engineering and Information Technology Department of Engineering ENGN3227 - Analogue Electronics Digital PC Oscilloscope David Dries u2543318 Craig Gibbons u2543813 James Moran u4114563 Ranmadhu Wijayatilaka u2549590 Dr. Salman Durrani 24 October 2006
CONTENTS Contents 1 Introduction 1 2 Theory 1 2.1 Operational Amplifiers........................... 1 2.2 Analogue to Digital Converter....................... 1 2.3 Full Wave Rectifier............................. 1 2.4 Voltage Regulation............................. 2 2.5 Multiplexer................................. 2 2.6 Sample and Hold Circuit.......................... 3 3 Implementation 3 3.1 Full Wave Rectifier............................. 3 3.2 Zero Crossing Detector........................... 4 3.3 Sample and Hold Circuit.......................... 5 3.4 ADC, MUX and Parallel Port Interface................... 6 4 Results 7 4.1 Program in Turbo C............................. 7 4.2 Input Signal reaching Conversion Circuit.................. 7 4.2.1 Fullwave Rectifier......................... 7 4.2.2 Sample and Hold.......................... 8 4.3 Conversion Circuit............................. 8 4.3.1 Verifying ADC Performance.................... 8 4.3.2 Multiplexer............................. 9 4.4 Parallel Port Interface............................ 9 4.5 Zero Crossing Detector........................... 10 4.6 Results of Debugging............................ 10 5 Conclusion 10 A Circuit Design 11 B Components 13 i
CONTENTS C Cathode Ray Oscilloscope Outputs 14 C.1 Zero Crossing Circuit............................ 14 C.2 Fullwave Rectifier.............................. 14 C.3 Sample and Hold Circuit.......................... 15 C.4 Zero-Crossing Detector........................... 16 D PSpice Implementation 17 D.1 Fullwave Rectifier.............................. 17 D.2 Sample and Hold Circuit.......................... 18 E 74244 Internal Pin Connections 19 ii
Abstract This project looks at the design and implementation processes used in the construction and testing of a PC based oscilloscope. Multiple input signals (DC, sinusoidal, square wave) waveforms, limited to 0-5 V peakto-peak with a maximum frequency of 1 khz were tested on a breadboard design, with the output signals observed on a PC graphical user interface (GUI) via hardware interfacing. Various signal conditioning processes were constructed within the project, including full rectification of signals, sampling and holding, digitising of signal information, and multiplexing of streams of data. Interfacing the oscilloscope to a personal computer was made via a standard 25 pin printer port (known commonly as a parallel port). Communication between the parallel port and the circuit was done through software constructed in the Turbo C. The final results obtained demonstrated the project is susceptible to large quantities of noise, as the output signals displayed on the GUI demonstrated large quantities of noise. It was noted though that each subsystem within the circuit, when treated individually, functioned properly, however this was not the case when the entire circuit was implemented as a whole system. It should be noted that the student engineers who participated in this project were satisfied with the final results, even though the circuit did not function properly. New concepts were learnt by each of the participating individuals, in particular hardware interfacing, system troubleshooting and system analysis. These skills, not taught in regular university classes, will be of fundamental use in their engineering careers, making the project a satisfying accomplishment.
2 THEORY 1 Introduction Oscilloscopes are electronic test equipment used primarily to accurately display the voltage of a signal against time or frequency. They have a wide range of possible applications, ranging from a medical researcher measuring brain waves to an automotive engineer measuring engine vibrations. Most modern oscilloscopes utilise digital storage, which digitally store data for as long as required. However, as modern computers become more widespread and prevalent, it is becoming advantageous to use PC oscilloscopes running on computers to obtain and display the data. This has many advantages: Easier to analyse the data. More processing power Easier to export and transport data from one device to another. Better resolution displays. Larger memory capacities for holding data. 2 Theory 2.1 Operational Amplifiers An operational amplifier, commonly referred to as an op-amp, is a high-gain differential voltage amplifier used extensively in electronic applications. Common examples include control system electronics, active filter design and bridge oscillator designs. Within this project, op-amps are used in the capacity of voltage followers and inverting amplifiers 2.2 Analogue to Digital Converter Analogue to digital converters (ADC) are a fundamental component in PC oscilloscopes. ADCs receive an analogue input signal, where it is then converted into a digital output. The resolution of an ADC states the number of discrete values its output can occupy, for example, an 8-bit ADC can have 256 (or 2 8 ) discrete values. 2.3 Full Wave Rectifier For our project, the use of a full wave rectifier is essential as the ADC cannot convert a negative signal to digital. To compensate for this, a full wave rectifier can be implemented, 1
2 THEORY whereby a sinusoidal wave can be rectified into a positive cyclic signal, as shown in Figure 1. (a) A non-rectified sine wave (b) A rectified sine wave Figure 1: Rectification of a sine wave 2.4 Voltage Regulation As a means of reducing the use of voltage supplies, voltage regulators can be used to produce a desired output voltage through the use of only one voltage source. An LM7805 chip was implemented in the project, whereby a 9 V input signal is regulated to a 5 V output, as shown in Figure 2 Figure 2: Voltage regulator circuit Capacitors C 1 and C 2 are vital in improving the quality of the regulator s input and output signals. C 1 is used to remove unwanted oscillations from the input signal that may arise when the power supply is a considerable distance from the regulator circuit. C 2 is used primarily to improve the transient response of the signal by acting as a line filter. 2.5 Multiplexer Transfering of information within electronic circuits can be a costly process when each stream of data has its own individual line of transmission. As a means of compensating for this, multiplexers can accept multiple input signals and encode them to a single output line. Figure 3 shows the concept of a basic multiplexer. 2
3 IMPLEMENTATION 2.6 Sample and Hold Circuit Figure 3: 2 to 1 multiplexer, analogous to a switch Sample and hold circuits are frequently used when converting analogue signals to digital. The sample and hold circuit takes the analogue input and outputs it to the ADC. When a sample is taken, the input signal is held via a capacitor. This output value is maintained until the next sample. See Figure 7 for an example implementation of sample and hold circuit. 3 Implementation Figure 4 displays a high level block diagram of the PC oscilloscope circuit that was implemented (see Figure 9 in Appendix A for full design). The signal is inputted into both the zero-crossing detector and the full-wave rectifier. Initially the full-wave rectifier converts the negative part of the sinusoidal input signal values to positive values, thus the signal is now the absolute value of the original signal. The zero-crossing detector determines when the original signal has negative values and sends that information to the PC, this ensures the PC can correctly determine which parts of the signal are negative even after it has been recitified. The full-wave rectifier sends the rectified signal to the sample and hold circuit. This subcircuit does not forward the signal through to the ADC until it receives a signal telling it to do so from the PC. When it receives this signal, it sends a sample of the signal to the ADC. The length of this sample is determined by the user s settings on the PC. The ADC converts the signal from analog to an 8-bit digital signal and sends that signal to the multiplexer. 3.1 Full Wave Rectifier A full wave rectifier can be implemented in different ways. The method used in this circuit utilizes two op-amps and two diodes as shown in Figure 5. When the signal is positive, A1 acts as an inverter, thus the signal current travels through Dio3 into the inverting pin of A2. Therefore, when the signal is negative, both the op-amps act as inverters, thus the signal is unchanged. However, when the signal is negative, A1 acts as an inverter but 3
3 IMPLEMENTATION Figure 4: Block diagram of implementation Figure 5: Full wave rectifier component (see Table 1 for component values) since the output signal from A1 is now positive, the signal current travels through Dio4 into the non-inverting pin of A2. Thus only A1 acts as an inverter when the input signal is negative. 3.2 Zero Crossing Detector Since the input signal is rectified before being sent to the ADC and onwards to the PC, the PC will not know whether the signal is positive or negative. To handle any negative inputs, the zero crossing detector is used. The 3rd LED will signal whether the input signal is negative or not. If the LED is on, the signal is positive. This signal is then sent to the PC to handle. 4
3 IMPLEMENTATION Figure 6: Zero crossing detector circuit (see Table 1 for component values) The zero crossing detector is implemented using a LM3914 chip, which is a monolithic integrated circuit. The chip senses analog voltage levels and drives a series of LEDs. Refer to Figure 6. 3.3 Sample and Hold Circuit The rectified signal is then fed into the sample and hold circuit. Figure 7: Sample and hold circuit (see Table 1 for component values) Figure 7 shows the sample and hold circuit that is implemented using two LM741 op- 5
3 IMPLEMENTATION amps and a CD4016 IC, which is a quad bilateral switch. This circuit divides the input signal (in the case of the project, a rectified sinuosoid) into several discrete voltage levels, samples each voltage level and then sends the delayed signal to the ADC for processing. By triggering the transistor, T1 with a low input signal sent from the computers parallel port, the transistor stops conducting and the voltage at the transistors collector switches to high. Once the collector goes high, an internal switch within the CD4016 closes, causing an output current to be produced from port Q1 of the CD4016. The output current begins to charge the capacitor C3 to a voltage level almost equal to the signal voltage. When the transistor is triggered with a high input signal from the parallel port D1, the switch of the CD4016 is left open, causing capacitor C3 to retain the voltage it had stored previously. The voltage is then sent to op-amp A4 (configured as a voltage follower) in order to transfer the signal from the high impedance CD4016 component to the low impedance ADC component. 3.4 ADC, MUX and Parallel Port Interface The ADC used in this circuit is an ADC0804 IC chip. It is powered by a 5 V supply and converts the input signal into an 8-bit output which is fed into the multiplexer unit (MUX) for PC interfacing. Figure 8: ADC and MUX pin connections and sorrounding circuitry (see Table 1 for component values) The inter-connection of the ADC, MUX and parallel ports is shown in Figure 8. The MUX unit is a 72422 type with tri-state buffer i.e. three possible outputs LOW, HIGH, Z (high impedance). It has 8 inbuilt buffers for processing of 8-bit data received from the 6
4 RESULTS ADC. Four of these buffers control the least signicant bits from the ADC (DB0-DB3), whilst the remaining four control the most signifcant bits of the ADC (DB4-DB7). The reason for this is detailed below. Conversion of the data between the ADC and the PC is initiated after port 16 of the parallel port sends pin 3 of the ADC an active low signal. 8-bit data is now sent to the MUX from the ADC. After a small time delay, pin 1 of the MUX is initialised from an active low signal from port 2 of the parallel port, allowing the four least significant bits of the 8-bit data stream to be sent to the PC. A short time later, another active low signal is sent from the parallel port, this time from port 9 to pin 19 of the MUX, causing the four most significant bits to be sent to the PC. The reason for separating the 8-bit data into two 4-bit streams of data is due to the parallel port s limitation in not allowing 8-bit input. 4 Results Upon initial inspection of the circuit s operation, multiple problems were noted. The input signal waveform was not replicated on the PC graphical user interface. Troubleshooting of the circuit was undertaken in order to isolate causes of the circuit failure. 4.1 Program in Turbo C The design that was implemented was originally published in 2002 and computers have come along way since then. So the first obstical to over come before even purschasing the components and constructing the circuit was to verify the code. The C code uses the parallel port (LPT1) for interfacing to the ciruit in digital form. Hence the program would not run easily under Windows XP, as XP has greater restrictions on the parallel port interface and does not co-operate with Turbo C very well. Thus, the choice was made to implement the system using Windows 98 as this would provide adequate control of the parallel ports. The code compiled and ran without errors, which meant the construction of the circuit could now begin. 4.2 Input Signal reaching Conversion Circuit 4.2.1 Fullwave Rectifier The reason for this subsection of the circuit not initially functioning correctl is yet to be determined. In the original circuit diagram, the project uses an LM324, an IC containing four amplifiers, that were configured to achieve full wave rectification. Instead, the output signal resembled a heavily noise distorted signal that showed no form of periodicity, even when the input to the IC was a sinusoidal waveform. Multiple LM324 s were tested with no varying result. See Figure 12 in Appendix C.2. 7
4 RESULTS By using LM741 op-amps, the full wave rectification circuit was reconstructed as shown in Figure 5 4.2.2 Sample and Hold In the original circuit design, the T1 transistor was a SL100 type transistor, however it could not be obtained as it is now obsolete. The 2N22 is a newer transistor with similar specifications. The voltage at the collector of the transistor was viewed on the CRO when sampling was requested from the PC. The transistor was switching on and off (0-9 V) in sync with the sample pulses which means it was working correctly. After changing the fullwave rectifier circuit to using LM741s, it was confirmed that the sample and hold circuit receives a correct input signal. Thus it was then necessary to correct the operation in this circuit. The issue assosciated in doing so is that the sample and hold circuit receives inputs from the PC via pin 1 on the parallel port. So we needed to know what happens to the output of this sample and hold circuit for a giving input when the PC is commanded to take a sample. There was a very quick fluctuation when the program requested a sample. The CRO was hooked up to display pin1 of the parallel port when a sample was requested by the PC (see Figure 13). From viewing this figure the signal being sent to the sample and hold was mainly a logical low with a short logical high pulse every 100 µs. When this pin is logical low the sample and hold circuit holds the current voltage level of the input. When logical high, the sample and hold follows the input then holds the value once logical low is returned. This can be seen in Figure 14. This confirmed that the sample and hold circuit was functioning correctly. 4.3 Conversion Circuit When initially debugging the circuit, the fullwave rectifier and the sample and hold circuits were not used. This helps to isolate any problems the circuit may have to individual modules. Thus the ADC and MUX were tested seperately from the rest of the circiut. 4.3.1 Verifying ADC Performance At first, no output signal was generated on the PC side of the system. First impressions for the cause of this was the 8-bit ADC not functioning properly (i.e. a faulty component). In order to test this, the resolution of the ADC was firstly computed: Resolution = V cc 2c 8 1 = 19.6 mv The resolution of the ADC allowed for the computation of the expected binary equivalent of an applied DC voltage signal. For example, the decimal equivalent output due to a 1 V 8
4 RESULTS supplied voltage signal is given as: 1 V 10 = The binary equivalent value is therefore: 1 V 19.6 mv = 51.02 51 51 10 = 110011 2 Thus the expected output signals from ports DB7 (most significant) to DB0 (least significant) of the ADC should be 00110011. This was confirmed experimentally by probing each of the ADC output pins, with corresponding high/lo (1 and 0) changes noted on the digital oscilloscope, verifying the output datastream being 00110011. To test the ADC directly with the C program, 4 of the 8 bit outputs were connected directly to the parallel port data lines (D3, D4, D5, D6) with a small DC voltage into the input V in(+). The constant DC waveform was displayed perfectly on the PC and increasing the input voltage increased the voltage on the PC in sync. 4.3.2 Multiplexer The pins 1 and 19 of the multiplexer (MUX) (see Figure 21 in Appendix E) are active low pins that determine which set of four output pins will be active. If pin 1 is on, then pins 18, 16, 14 and 12 will have the same voltage as pins 2, 4, 6 and 8 respectively. Likewise, if pin 19 is on, pins 3, 5, 7 and 9 will have the same voltage as pins 17, 15, 13 and 11 respectively. This behaviour was observed by inputting voltages into the different input pins and changing the values of the control pins (pins 1 and 19). Thus it was confirmed that the MUX unit was working correctly. 4.4 Parallel Port Interface The C code was setup to default on LPT1 with Data port 0x0378. To make sure the PCs parallel port was also setup on LPT1 debug was used in DOS. The following command was used: Debug d 0040:08 L8. Which resulted in 78 03 00 00 00 00 0B 02 being returned. This means LPT1 is used for Data port 0x0378, LPT2 and LPT3 arent used, and LPT4 0x020B is assigned. This concludes that the code is using the correct data, status and controls ports. The next step was to ensure that the parallel port interface between the circuit and the PC functioned correctly. To determine this, the parallel port was seperated from the circuit and voltages were applied to the individual pins of the port to simulate logical high (3 V to 5 V). Whilst doing this, the software was run and data captured onto the PC oscilloscope and recorded. From this observed data, it was confirmed that inputting logical highs into the individual pins affected the output on the PC oscilloscope. 9
5 CONCLUSION 4.5 Zero Crossing Detector This step was left to last because this only determines if the signal is above or below 0 V. The zero-crossing detector was tested in isolation to ensure that it works as designed. The output was observed via the cathode ray oscilloscope (see Figure 15) in Appendix C.4). This output waveform confirmed that the zero-crossing detector was working but it wasnt switching states exactly at zero volts. V R1 was varied so the detector was switching states exactly at zero (see Figure 16) in Appendix C.4) When the input signal was negative, the zero-crossing detector was a logical high. 4.6 Results of Debugging After debugging the circuit s individual modules, it was found that each of them functioned as were expected. The problems arose when the system was constructed as a whole. The output then was inconsistent and heavly noise affected. There are several possible reasons for this is the timing of the circuit: The PC sends a signal to the MUX to send the first 4-bit packet, followed by the next 4-bits, the timing of this operation must be very precise in order to calculate and display a proper waveform. Thus any mis-timings in the output side of the circuit will result in varying results. Another major cause of the incorrect output is the noise generated by the sample and hold circuit. The circuit should ideally hold the same value, however, when observed via the oscilloscope, it was noted that the output was heavily affected by noise. This constant change in the output of the sample and hold circuit means both the ADC and the MUX will also have varying outputs, thus skewing the final display on the PC. 5 Conclusion Overall, the project was satisfactorily completed. The initial objective could not be achieved; however, it was observed that each component functioned correctly in isolation. The problems in the integrated circuit was narrowed down to the MUX-PC interface timing and the noise in the sample and hold output. Most importantly, the project confirmed that PC interfacing is a achievable, and that PC digital oscilloscopes can be implemented with further study and analysis. 10
A CIRCUIT DESIGN A Circuit Design Figure 9: The original circuit design 11
A CIRCUIT DESIGN Figure 10: The circuit implemented on breadboards 12
B COMPONENTS B Components Table 1: Components used in the circuit ID Component Value Notes R1 Resistor 10 KΩ R2 Resistor 330 Ω R3 Resistor 330 Ω R4 Resistor 330 Ω R5 Resistor 330 Ω R6 Resistor 330 Ω R7 Resistor 1 MΩ R8 Resistor 470 Ω R9 Resistor 470 Ω R10 Resistor 470 Ω R11 Resistor 470 Ω R12 Resistor 470 Ω R13 Resistor 470 Ω R14 Resistor 470 Ω R15 Resistor 470 Ω R16 Resistor 470 Ω R17 Resistor 470 Ω R18 Resistor 1 kω R19 Resistor 10 kω 1 W power rating C1 Capacitor 1000 µf C2 Capacitor 0.1 µf C3 Capacitor 1500 pf A1 Op-amp LM741 A2 Op-amp LM741 A3 Op-amp LM741 A4 Op-amp LM741 A5 Op-amp LM741 VR1 Variable resistor 10 kω VR2 Variable resistor 10 kω Dio1 Diode (1N4001) Dio2 Diode (1N4001) Dio3 Diode (1N4001) Dio4 Diode (1N4001) IC1 Multiplexer (74244) IC3 ADC (0804) T1 Transistor (2N22) 13
C CATHODE RAY OSCILLOSCOPE OUTPUTS C Cathode Ray Oscilloscope Outputs C.1 Zero Crossing Circuit Figure 11: Input and output from the zero crossing circuit. The output goes high when the input signal is negative. C.2 Fullwave Rectifier Figure 12: Input and output from the fullwave rectifier circuit. The output is the absolute value of the input signal. 14
C CATHODE RAY OSCILLOSCOPE OUTPUTS C.3 Sample and Hold Circuit Figure 13: Input from the PC (via pin 1 on the parallel port) to the sample and hold circuit Figure 14: Output from the sample and hold circuit 15
C CATHODE RAY OSCILLOSCOPE OUTPUTS C.4 Zero-Crossing Detector Figure 15: Incorrect output from the zero crossing detector Figure 16: Corrected output from the zero crossing detector 16
D PSPICE IMPLEMENTATION D PSpice Implementation D.1 Fullwave Rectifier Figure 17: PSpice implementation of the fullwave rectifier Figure 18: Output waveform 17
D PSPICE IMPLEMENTATION D.2 Sample and Hold Circuit Figure 19: PSpice implementation of the sample and hold circuit Figure 20: Output waveform 18
E 74244 INTERNAL PIN CONNECTIONS E 74244 Internal Pin Connections Figure 21 shows the internal circuitry of a 74244 MUX IC unit (obtained from Fairchild Semiconductor s DM74LS244 data sheet). Figure 21: Internal circuitry of 74244 MUX IC unit 19