Digital Fundamentals Systems pproach Thomas L. Floyd First Edition
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LOgI gtes ND gte OmINTIONS Figure 95 section 6 the nor gate 27. Repeat Problem 23 for a 2-input NOR gate. 28. Determine the output waveform in Figure 96 and draw the timing diagram. Figure 96 29. Repeat Problem 25 for a 4-input NOR gate. 30. The NND and the negative-or symbols represent equivalent operations, but they are functionally different. For the NOR symbol, look for at least one HIgH on the inputs to give a LOW on the output. For the negative-nd, look for two LOWs on the inputs to give a HIgH output. Using these two functional points of view, show that both gates in Figure 97 will produce the same output for the given inputs. Figure 97 section 7 the exclusive-or and exclusive-nor gates 31. How does an exclusive-or gate differ from an OR gate in its logical operation? 32. Repeat Problem 23 for an exclusive-or gate. 33. Repeat Problem 23 for an exclusive-nor gate. 34. Determine the output of an exclusive-or gate for the inputs shown in Figure 88 and draw a timing diagram. section 8 gate Performance characteristics and Parameters 35. Determine t PLH and t PHL from the oscilloscope display in Figure 98. The readings indicate volts/div and sec/div for each channel. Input Output h1 2 V h2 2 V 5 ns Figure 98 169
LOgI gtes ND gte OmINTIONS 36. Gate has t PLH = t PHL = 6 ns. Gate has t PLH = t PHL = 10 ns. Which gate can be operated at a higher frequency? 37. If a logic gate operates on a dc supply voltage of +5 V and draws an average current of 4 m, what is its power dissipation? 38. The variable I H represents the dc supply current from V when all outputs of an I are HIGH. The variable I L represents the dc supply current when all outputs are LOW. For a given 5 V I with four NND gates, what is the average power dissipation when all the gate outputs are HIgH for half the time and LOW for half the time? I H = 0.5 m and I L = 1 m. section 9 Programmable Logic 39. In the simple programmed ND array with programmable links in Figure 99, determine the oolean output expressions. 1 2 3 Figure 99 40. Determine by row and column number which fusible links must be blown in the programmable ND array of Figure 100 to implement each of the following product terms: 1 =, 2 =, 3 =. 1 2 1 3 4 5 2 6 7 8 3 9 1 2 3 4 5 6 170 Figure 100
LOgI gtes ND gte OmINTIONS 41. Describe a 4-input ND gate using VHDL. 42. Repeat Problem 41 using Verilog. 43. Describe a 5-input NOR gate using VHDL. 44. Repeat Problem 43 using Verilog. section 10 troubleshooting 45. Define troubleshooting. 46. Explain the half-splitting method of troubleshooting. 47. Explain the signal-tracing method of troubleshooting. 48. Discuss signal substitution and injection. 49. give some examples of the type of information that you look for when a system is reported to have failed. 50. If the symptom in a particular system is no output, name two possible general causes. 51. If the symptom of a particular system is an incorrect output, name two possible causes. 52. What obvious things should you look for before starting the troubleshooting process? 53. How would you isolate a fault in a system? 54. Name two common instruments used in troubleshooting. 55. ssume that you have isolated the problem down to a specific circuit board. What are your options at this point? special Problems 56. Sensors are used to monitor the pressure and the temperature of a chemical solution stored in a vat. The circuitry for each sensor produces a HIgH voltage when a specified maximum value is exceeded. n alarm requiring a LOW voltage input must be activated when either the pressure or the temperature is excessive. Develop a circuit for this application. 57. In a certain automated manufacturing process, electrical components are automatically inserted in a P board. efore the insertion tool is activated, the P board must be properly positioned, and the component to be inserted must be in the chamber. Each of these prerequisite conditions is indicated by a HIgH voltage. The insertion tool requires a LOW voltage to activate it. Develop a circuit to implement this process. 58. modify the frequency counter in Figure 31 to operate with an enable pulse that is active-low rather than HIgH during the 1 ms interval. 59. ssume that the enable signal in Figure 31 has the waveform shown in Figure 101. ssume that waveform is also available. Show how to produce an active-high reset pulse to the counter only during the time that the enable signal is LOW. Enable Figure 101 60. Develop a device to fit in the beige block of Figure 102 that will cause the headlights of an automobile to be turned off automatically 15 s after the ignition switch is turned off, if the light switch is left on. ssume that a LOW is required to turn the lights off. LOW turns off the lights. Ignition switch Light switch HIGH = On LOW = Off HIGH = On LOW = Off Headlight control Figure 102 171
LOgI gtes ND gte OmINTIONS 61. modify the logic circuit for the intrusion alarm in Figure 39 so that two additional rooms, each with two windows and one door, can be protected. 62. Further modify the logic circuit from Problem 61 for a change in the input sensors where Open = LOW and losed = HIGH. multisim multisim troubleshooting Practice 63. Open file P03-63, and follow the instructions given there. 64. Open file P03-64, and follow the instructions given there. 65. Open file P03-65, and follow the instructions given there. 66. Open file P03-66, and follow the instructions given there. answers to section checkups section 1 introduction to boolean algebra 1. = 0 = 1 2. = 1, = 1, = 0; + + = 1 + 1 + 0 = 0 + 0 + 0 = 0 3. = 1, = 0, = 1; = 1 # 0 # 1 = 1 # 1 # 1 = 1 4. + ( + + D) = ( + + ) + D 5. ( + + D) = + + D section 2 the inverter 1. When the inverter input is 1, the output is 0. (a) (b) negative-going pulse is on the output (HIgH to LOW and back HIgH). section 3 the and gate 1. n ND gate output is HIgH only when all inputs are HIgH. 2. n ND gate output is LOW when one or more inputs are LOW. 3. Five-input ND: = 1 when DE = 11111, and = 0 for all other combinations of DE. section 4 the or gate 1. n OR gate output is HIgH when one or more inputs are HIgH. 2. n OR gate output is LOW only when all inputs are LOW. 3. Three-input OR: = 0 when = 000, and = 1 for all other combinations of. section 5 the nand gate 1. NND output is LOW only when all inputs are HIgH. 2. NND output is HIgH when one or more inputs are LOW. 3. NND: active-low output for all HIgH inputs; negative-or: active-high output for one or more LOW inputs. They have the same truth tables. 4. = 172 section 6 the nor gate 1. NOR output is HIgH only when all inputs are LOW. 2. NOR output is LOW when one or more inputs are HIgH.
LOgI gtes ND gte OmINTIONS 3. NOR: active-low output for one or more HIgH inputs; negative-nd: active-high output for all LOW inputs. They have the same truth tables. 4. = + + section 7 the exclusive-or and exclusive-nor gates 1. n OR output is HIgH when the inputs are at opposite levels. 2. n NOR output is HIgH when the inputs are at the same levels. 3. pply the bits to the OR inputs; when the output is HIgH, the bits are different. section 8 gate Performance characteristics and Parameters 1. Lowest power mos 2. t PLH = 10 ns; t PHL = 8 ns 3. 18 pj 4. I L dc supply current for LOW output state; I H dc supply current for HIgH output state 5. V IL LOW input voltage; V IH HIgH input voltage 6. V OL LOW output voltage; V OH HIgH output voltage section 9 Programmable Logic 1. Fuse, antifuse, EPROm, EEPROm, flash, and SRm 2. Volatile means that all the data are lost when power is off and the PLD must be reprogrammed; SRm-based 3. Text entry and graphic entry 4. JTg is Joint Test ction group; the IEEE Std. 1149.1 for programming and test interfacing. 5. entity NORgate is vhdl verilog module NORgate (,,, ); port (,, : in bit; : out bit); input,, ; end entity NORgate; output ; architecture NORfunction of NORgate is begin <= nor nor ; end architecture NORfunction; assign =!( ); endmodule 6. vhdl verilog entity ORgate is module ORgate (,, ); port (, : in bit; : out bit); input, ; end entity ORgate; output ; architecture ORfunction of ORgate is assign = ( &&!) (! && ); begin endmodule <= xor ; end architecture ORfunction; section 10 troubleshooting 1. gather information, identify symptoms and possible causes, isolate point(s) of failure, apply proper tools to determine cause, and fix problem. 2. Half-splitting and signal tracing 3. lown fuse, absence of D power, loose connections, broken wires, loosely connected circuit board 4. Yes 173