74HC595; 74HCT General description. 2. Features and benefits. 3. Applications

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 8 25 February 2016 Product data sheet 1. General description The is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V CC. 2. Features and benefits 3. Applications 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs Shift register with direct clear 100 MHz (typical) shift out frequency Complies with JEDEC standard no. 7A Input levels: For 74HC595: CMOS level For 74HCT595: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C Serial-to-parallel data conversion Remote control holding register

4. Ordering information Table 1. Type number Ordering information Package Temperature range Name Description Version 74HC595D 74HCT595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm 74HC595DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; 74HCT595DB body width 5.3 mm 74HC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; 74HCT595PW body width 4.4 mm 74HC595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced 74HCT595BQ very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm 5. Functional diagram SOT109-1 SOT338-1 SOT403-1 SOT763-1 Fig 1. Functional diagram Product data sheet Rev. 8 25 February 2016 2 of 23

Fig 2. Logic symbol Fig 3. IEC logic symbol Fig 4. Logic diagram Product data sheet Rev. 8 25 February 2016 3 of 23

6. Pinning information 6.1 Pinning (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO16, SSOP16 and TSSOP16 Fig 6. Pin configuration for DHVQFN16 6.2 Pin description Table 2. Pin description Symbol Pin Description Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input Q0 15 parallel data output 0 V CC 16 supply voltage Product data sheet Rev. 8 25 February 2016 4 of 23

7. Functional description Table 3. Function table [1] Control Input Output Function SHCP STCP OE MR DS Q7S Qn X X L L X L NC a LOW-level on MR only affects the shift registers X L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages [1] H = HIGH voltage state; L = LOW voltage state; = LOW-to-HIGH transition; X = don t care; NC = no change; Z = high-impedance OFF-state. Fig 7. Timing diagram Product data sheet Rev. 8 25 February 2016 5 of 23

8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7 V I IK input clamping current V I < 0.5 V or V I >V CC + 0.5 V - 20 ma I OK output clamping current V O < 0.5 V or V O > V CC + 0.5 V - 20 ma I O output current V O = 0.5 V to (V CC +0.5V) pin Q7S - 25 ma pins Qn - 35 ma I CC supply current - 70 ma I GND ground current 70 - ma T stg storage temperature 65 +150 C P tot total power dissipation SO16 package [1] - 500 mw SSOP16 package [2] - 500 mw TSSOP16 package [2] - 500 mw DHVQFN16 package [3] - 500 mw [1] For SO16 package: P tot derates linearly with 8 mw/k above 70 C. [2] For SSOP16 and TSSOP16 packages: P tot derates linearly with 5.5 mw/k above 60 C. [3] For DHVQFN16 package: P tot derates linearly with 4.5 mw/k above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions 74HC595 74HCT595 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V t/v input transition rise and V CC = 2.0 V - - 625 - - - ns/v fall rate V CC = 4.5 V - 1.67 139-1.67 139 ns/v V CC =6.0V - - 83 - - - ns/v T amb ambient temperature 40 +25 +125 40 +25 +125 C Product data sheet Rev. 8 25 February 2016 6 of 23

10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max 74HC595 V IH HIGH-level V CC = 2.0 V 1.5 1.2-1.5 - V input voltage V CC = 4.5 V 3.15 2.4-3.15 - V V CC = 6.0 V 4.2 3.2-4.2 - V V IL LOW-level V CC = 2.0 V - 0.8 0.5-0.5 V input voltage V CC = 4.5 V - 2.1 1.35-1.35 V V CC = 6.0 V - 2.8 1.8-1.8 V V OH HIGH-level output voltage V I =V IH or V IL all outputs I O = 20 A; V CC = 2.0 V 1.9 2.0-1.9 - V I O = 20 A; V CC = 4.5 V 4.4 4.5-4.4 - V I O = 20 A; V CC = 6.0 V 5.9 6.0-5.9 - V Q7S output I O = 4 ma; V CC = 4.5 V 3.84 4.32-3.7 - V I O = 5.2 ma; V CC = 6.0 V 5.34 5.81-5.2 - V Qn bus driver outputs I O = 6 ma; V CC = 4.5 V 3.84 4.32-3.7 - V I O = 7.8 ma; V CC = 6.0 V 5.34 5.81-5.2 - V V OL LOW-level output voltage V I =V IH or V IL all outputs I O =20A; V CC = 2.0 V - 0 0.1-0.1 V I O =20A; V CC = 4.5 V - 0 0.1-0.1 V I O =20A; V CC = 6.0 V - 0 0.1-0.1 V Q7S output I O =4mA; V CC = 4.5 V - 0.15 0.33-0.4 V I O =5.2mA; V CC = 6.0 V - 0.16 0.33-0.4 V Qn bus driver outputs I O =6mA; V CC = 4.5 V - 0.15 0.33-0.4 V I O =7.8mA; V CC = 6.0 V - 0.16 0.33-0.4 V I I input leakage V I =V CC or GND; V CC =6.0V - - 1.0-1.0 A current I OZ OFF-state V I =V IH or V IL ; V CC =6.0V; - - 5.0-10 A output current V O =V CC or GND I CC supply current V I =V CC or GND; I O =0A; - - 80-160 A V CC =6.0V C I input capacitance - 3.5 - - - pf Product data sheet Rev. 8 25 February 2016 7 of 23

Table 6. Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max 74HCT595 V IH HIGH-level input voltage V IL LOW-level input voltage V OH HIGH-level output voltage V OL I I I OZ LOW-level output voltage input leakage current OFF-state output current V CC = 4.5 V to 5.5 V 2.0 1.6-2.0 - V V CC = 4.5 V to 5.5 V - 1.2 0.8-0.8 V V I =V IH or V IL ; V CC =4.5V all outputs I O = 20 A 4.4 4.5-4.4 - V Q7S output I O = 4 ma 3.84 4.32-3.7 - V Qn bus driver outputs I O = 6 ma 3.7 4.32-3.7 - V V I =V IH or V IL ; V CC =4.5V all outputs I O =20A - 0 0.1-0.1 V Q7S output I O = 4.0 ma - 0.15 0.33-0.4 V Qn bus driver outputs I O = 6.0 ma - 0.16 0.33-0.4 V V I =V CC or GND; V CC =5.5V - - 1.0-1.0 A V I =V IH or V IL ; V CC =5.5 V; V O =V CC or GND I CC supply current V I =V CC or GND; I O =0A; V CC =5.5V I CC C I additional supply current input capacitance - - 5.0-10 A - - 80-160 A per input pin; I O =0A; V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V pins MR, SHCP, STCP, OE - 150 675-735 A pin DS - 25 113-123 A - 3.5 - - - pf Product data sheet Rev. 8 25 February 2016 8 of 23

11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max Min Max 74HC595 t pd propagation SHCP to Q7S; see Figure 8 [2] delay V CC = 2 V - 52 160-200 - 240 ns V CC = 4.5 V - 19 32-40 - 48 ns V CC = 6 V - 15 27-34 - 41 ns STCP to Qn; see Figure 9 [2] V CC = 2 V - 55 175-220 - 265 ns V CC = 4.5 V - 20 35-44 - 53 ns V CC = 6 V - 16 30-37 - 45 ns MR to Q7S; see Figure 11 [3] V CC = 2 V - 47 175-220 - 265 ns V CC = 4.5 V - 17 35-44 - 53 ns V CC = 6 V - 14 30-37 - 45 ns t en enable time OE to Qn; see Figure 12 [4] V CC = 2 V - 47 150-190 - 225 ns V CC = 4.5 V - 17 30-38 - 45 ns V CC = 6 V - 14 26-33 - 38 ns t dis disable time OE to Qn; see Figure 12 [5] V CC = 2 V - 41 150-190 - 225 ns V CC = 4.5 V - 15 30-38 - 45 ns V CC = 6 V - 12 27-33 - 38 ns t W pulse width SHCP HIGH or LOW; see Figure 8 V CC = 2 V 75 17-95 - 110 - ns V CC = 4.5 V 15 6-19 - 22 - ns V CC = 6 V 13 5-16 - 19 - ns STCP HIGH or LOW; see Figure 9 V CC = 2 V 75 11-95 - 110 - ns V CC = 4.5 V 15 4-19 - 22 - ns V CC = 6 V 13 3-16 - 19 - ns MR LOW; see Figure 11 V CC = 2 V 75 17-95 - 110 - ns V CC = 4.5 V 15 6-19 - 22 - ns V CC = 6 V 13 5-16 - 19 - ns Product data sheet Rev. 8 25 February 2016 9 of 23

Table 7. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max Min Max t su set-up time DS to SHCP; see Figure 9 V CC = 2 V 50 11-65 - 75 - ns V CC = 4.5 V 10 4-13 - 15 - ns V CC = 6 V 9 3-11 - 13 - ns SHCP to STCP; see Figure 10 V CC = 2 V 75 22-95 - 110 - ns V CC = 4.5 V 15 8-19 - 22 - ns V CC = 6 V 13 7-16 - 19 - ns t h hold time DS to SHCP; see Figure 10 V CC = 2 V 3 6-3 - 3 - ns V CC = 4.5 V 3 2-3 - 3 - ns V CC = 6 V 3 2-3 - 3 - ns t rec recovery MR to SHCP; see Figure 11 time V CC = 2 V 50 19-65 - 75 - ns V CC = 4.5 V 10 7-13 - 15 - ns V CC = 6 V 9 6-11 - 13 - ns f max C PD maximum frequency power dissipation capacitance SHCP or STCP; see Figure 8 and 9 V CC = 2 V 9 30-4.8-4 - MHz V CC = 4.5 V 30 91-24 - 20 - MHz V CC = 6 V 35 108-28 - 24 - MHz f i = 1 MHz; V I =GNDtoV CC [6][7] - 115 - - - - - pf Product data sheet Rev. 8 25 February 2016 10 of 23

Table 7. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max Min Max 74HCT595; V CC = 4.5 V to 5.5 V t pd propagation SHCP to Q7S; see Figure 8 [2] - 25 42-53 - 63 ns delay STCP to Qn; see Figure 9 [2] - 24 40-50 - 60 ns MR to Q7S; see Figure 11 [3] - 23 40-50 - 60 ns t en enable time OE to Qn; see Figure 12 [4] - 21 35-44 - 53 ns t dis disable time OE to Qn; see Figure 12 [5] - 18 30-38 - 45 ns t W pulse width SHCP HIGH or LOW; 16 6-20 - 24 - ns see Figure 8 STCP HIGH or LOW; 16 5-20 - 24 - ns see Figure 9 MR LOW; see Figure 11 20 8-25 - 30 - ns t su set-up time DS to SHCP; see Figure 9 16 5-20 - 24 - ns SHCP to STCP; 16 8-20 - 24 - ns see Figure 10 t h hold time DS to SHCP; see Figure 10 3 2-3 - 3 - ns t rec recovery MR to SHCP; see Figure 11 10 7-13 - 15 - ns time f max maximum frequency SHCP and STCP; see Figure 8 and 9 30 52-24 - 20 - MHz C PD power dissipation capacitance f i = 1 MHz; V I =GNDtoV CC 1.5 V [6] [7] [1] Typical values are measured at nominal supply voltage. [2] t pd is the same as t PHL and t PLH. [3] t pd is the same as t PHL only. [4] t en is the same as t PZL and t PZH. [5] t dis is the same as t PLZ and t PHZ. [6] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; (C L V 2 CC f o ) = sum of outputs; C L = output load capacitance in pf; V CC = supply voltage in V. [7] All 9 outputs switching. - 130 - - - - - pf Product data sheet Rev. 8 25 February 2016 11 of 23

12. Waveforms Fig 8. Measurement points are given in Table 8. V OL and V OH are typical output voltage levels that occur with the output load. Shift clock pulse, maximum frequency and input to output propagation delays Fig 9. Measurement points are given in Table 8. V OL and V OH are typical output voltage levels that occur with the output load. Storage clock to output propagation delays Product data sheet Rev. 8 25 February 2016 12 of 23

Fig 10. Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. V OL and V OH are typical output voltage levels that occur with the output load. Data set-up and hold times Fig 11. Measurement points are given in Table 8. V OL and V OH are typical output voltage levels that occur with the output load. Master reset to output propagation delays Product data sheet Rev. 8 25 February 2016 13 of 23

Fig 12. Measurement points are given in Table 8. V OL and V OH are typical output voltage levels that occur with the output load. Enable and disable times Table 8. Measurement points Type Input Output V M V M 74HC595 0.5V CC 0.5V CC 74HCT595 1.3 V 1.3 V Product data sheet Rev. 8 25 February 2016 14 of 23

Test data is given in Table 9. Definitions for test circuit: C L = load capacitance including jig and probe capacitance. R L = load resistance. R T = termination resistance should be equal to the output impedance Z o of the pulse generator. S1 = test selection switch. Fig 13. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC595 V CC 6 ns 50 pf 1 k open GND V CC 74HCT595 3 V 6 ns 50 pf 1 k open GND V CC Product data sheet Rev. 8 25 February 2016 15 of 23

13. Package outline Fig 14. Package outline SOT109-1 (SO16) Product data sheet Rev. 8 25 February 2016 16 of 23

Fig 15. Package outline SOT338-1 (SSOP16) Product data sheet Rev. 8 25 February 2016 17 of 23

Fig 16. Package outline SOT403-1 (TSSOP16) Product data sheet Rev. 8 25 February 2016 18 of 23

Fig 17. Package outline SOT763-1 (DHVQFN16) Product data sheet Rev. 8 25 February 2016 19 of 23

14. Abbreviations Table 10. Acronym CMOS DUT ESD HBM LSTTL MM Abbreviations Abbreviation Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes v.8 20160225 Product data sheet - v.7 Modifications: Type numbers 74HC595N and 74HCT595N (SOT38-4) removed. v.7 20150126 Product data sheet - v.6 Modifications: Table 7: Power dissipation capacitance condition for 74HCT595 is corrected. v.6 20111212 Product data sheet - v.5 Modifications: Legal pages updated. v.5 20110628 Product data sheet - v.4 v.4 20030604 Product specification - _CNV v.3 _CNV v.3 19980604 Product specification - - Product data sheet Rev. 8 25 February 2016 20 of 23

16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 16.2 Definitions Draft The document is a draft version only. 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Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 8 25 February 2016 21 of 23

Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia s specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia s standard warranty and Nexperia s product specifications. Translations A non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Product data sheet Rev. 8 25 February 2016 22 of 23

18. Contents 1 General description...................... 1 2 Features and benefits.................... 1 3 Applications............................ 1 4 Ordering information..................... 2 5 Functional diagram...................... 2 6 Pinning information...................... 4 6.1 Pinning............................... 4 6.2 Pin description......................... 4 7 Functional description................... 5 8 Limiting values.......................... 6 9 Recommended operating conditions........ 6 10 Static characteristics..................... 7 11 Dynamic characteristics.................. 9 12 Waveforms............................ 12 13 Package outline........................ 16 14 Abbreviations.......................... 20 15 Revision history........................ 20 16 Legal information....................... 21 16.1 Data sheet status...................... 21 16.2 Definitions............................ 21 16.3 Disclaimers........................... 21 16.4 Trademarks........................... 22 17 Contact information..................... 22 18 Contents.............................. 23 For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 February 2016